Method for forming fin of semiconductor device

Abstract

The present invention relates to a method for forming a fin of a semiconductor device, and to a semiconductor integrated circuit manufacturing technology. After forming a second sidewall, at least one second sidewall adjacent to both sides of an effective second sidewall is removed through a fine removal process, so that at least one second sidewall adjacent to both sides of the effective second sidewall is not transferred to a layer to be patterned, thereby avoiding removing the fins on both sides of the effective fin through a fine removal process after the fin is formed, thereby reducing the difficulty of the fine removal process and the requirements for the fine removal process, and after forming a plurality of discrete patterns on the layer to be patterned, a rough removal process is used to etch away parts of discrete patterns other than the discrete patterns corresponding to the effective second sidewall, so that the fine removal process and the rough removal process are performed separately, thereby reducing the difficulty of the two-step removal process.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuit manufacturing technology, and in particular to a method for forming a fin of a semiconductor device. Background Art

[0002] In the field of semiconductor integrated circuits, with the development of technology, the critical dimensions of semiconductor devices are constantly shrinking, and the requirements for semiconductor device manufacturing processes are becoming more and more stringent. In order to increase the integration density of semiconductor devices, many different methods are used in the prior art, such as the Self-aligned Quadruple Patterning (SAQP) process. The SAQP process can be used to prepare devices with smaller nodes, and it has been proven that the SAQP process can provide smaller process fluctuations. With the continuous development of the process, the use of SAQP can now make the spacing of the fins less than 40nm.

[0003] The typical SAQP process steps are: first form the first mandrel. Then form a sidewall covering the first mandrel, and use the sidewall of the first mandrel as a mask to form a second mandrel. Then form a sidewall covering the second mandrel, and use the sidewall of the second mandrel as a mask to form a fin. The fins formed by the SAQP process are dense, and the spacing between the fins can be less than 40nm. When forming devices such as SRAM, it is necessary to etch the fins to increase the spacing between the fins. However, the limit of the distance of the mask pattern is as low as 80nm. When the spacing between the fins is less than 40nm and the fins need to be etched in an intermittent manner, when using one mask, the distance between the mask patterns will be less than 80nm, and the predetermined effect cannot be achieved. Therefore, two masks are required. This makes the process more complicated and the production cost higher. Summary of the invention

[0004] The present invention provides a method for forming a fin of a semiconductor device, comprising: S1: providing a semiconductor substrate, the semiconductor substrate comprising a layer to be patterned, a fin hard mask layer, a first mandrel layer and a second mandrel layer stacked in sequence, a first etch stop layer between the first mandrel layer and the second mandrel layer, a second etch stop layer between the first mandrel layer and the fin hard mask layer, and an oxide pad layer between the fin hard mask layer and the layer to be patterned; S2: etching the second mandrel layer to form a plurality of second mandrels with predetermined intervals between each other; S3 : forming a first sidewall on both sides of the second mandrel; S4: removing the second mandrel with the first etch stop layer as the stop layer, and retaining the first sidewall; S5: etching the first etch stop layer and the first mandrel layer with the second etch stop layer as the stop layer and the first sidewall as a mask to form a plurality of first mandrels; S6: removing the first sidewall and forming a second sidewall covering both sides of the first mandrel; S7: removing the first mandrel and retaining the second sidewall; S8: forming a photoresist layer, and performing exposure and development to At least one second side wall adjacent to both sides of the effective second side wall is exposed, the effective second side wall and other second side walls are protected by photoresist, and an etching process is performed to remove the exposed at least one second side wall; S9: removing the photoresist; S10: etching until the layer to be patterned is formed by using the remaining second side wall and the effective second side wall as masks to form a plurality of discrete patterns on the layer to be patterned; S11: removing the remaining second side wall and the effective second side wall, forming a photoresist layer, and performing exposure and development to remove the discrete patterns corresponding to the effective second side wall; The discrete pattern is protected by photoresist, the discrete patterns corresponding to the other second side walls are revealed, and an etching process is performed to etch away the revealed second etch stop layer, the fin hard mask layer, the pad oxide layer and part of the discrete pattern; S12: removing the photoresist; S13: forming an oxide layer, and performing a thermal annealing process, and then performing a planarization process using the fin hard mask layer as a stop layer; and S14: removing the fin hard mask layer and the pad oxide layer on the discrete pattern, and then removing part of the oxide layer to expose the discrete pattern to form an effective fin body.

[0005] Furthermore, in S2, a photolithography pattern is formed above the second mandrel layer, and the first mandrel layer is etched using the photolithography pattern as a mask to form a plurality of second mandrels.

[0006] Furthermore, in S3 , a first spacer material layer covering the second core shaft is deposited; and the first spacer material layer is etched back to form the first spacer.

[0007] Furthermore, in S6 , a second spacer material layer covering the first core shaft is deposited; and the second spacer material layer is etched back to form the second spacer.

[0008] Furthermore, in S8 , two second side walls adjacent to both sides of the effective second side wall are removed.

[0009] Furthermore, in S14 , the oxide layer at the bottom of the effective fins forms an isolation portion between the effective fins.

[0010] Furthermore, the height of the remaining oxide layer in step S14 is higher than the height of the remaining discrete patterns of the photoresist-developed portion in step S9.

[0011] Furthermore, the layer to be patterned is a silicon single crystal, a germanium single crystal or a silicon germanium single crystal.

[0012] Furthermore, the intervals between the second mandrels are equal.

[0013] Furthermore, in S10 , a plurality of discrete patterns corresponding to the remaining second spacers and the effective second spacers are formed by a wet etching process using the remaining second spacers and the effective second spacers as masks.

[0014] In this way, after the second side wall is formed, at least one second side wall adjacent to both sides of the effective second side wall is removed through a fine removal process, so that at least one second side wall adjacent to both sides of the effective second side wall is not transferred to the layer to be patterned, thereby avoiding the removal of the fin body on both sides of the effective fin body through a fine removal process after the fin body is formed, thereby reducing the difficulty of the fine removal process and the requirements for the fine removal process, and after forming multiple discrete patterns on the layer to be patterned, the discrete patterns other than the discrete patterns corresponding to the effective second side wall are partially etched away through a rough removal process, thus the fine removal process and the rough removal process are performed separately, thereby reducing the difficulty of the two-step removal process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1a to 14a The figure is a schematic top view of the structure of each step in the process of forming the fin of a semiconductor device according to an embodiment of the present invention.

[0016] Figures 1b to 14b In the process of forming the fin of the semiconductor device according to one embodiment of the present invention, Figures 1a to 14a Schematic diagram of the cross-sectional structure along the line Y-Y'.

[0017] Figures 8c to 14c In the process of forming the fin of the semiconductor device according to one embodiment of the present invention, Figures 8a to 14a Schematic diagram of the cross-sectional structure of X-X'. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] It should be understood that the present invention can be implemented in different forms, and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to " other elements or layers, it can be directly on other elements or layers, adjacent to it, connected or coupled to other elements or layers, or there can be an intervening element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to " other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0020] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0021] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] In one embodiment of the present invention, a method for forming a fin of a semiconductor device is provided, comprising: S1: providing a semiconductor substrate, the semiconductor substrate comprising a layer to be patterned, a fin hard mask layer, a first mandrel layer and a second mandrel layer stacked in sequence, a first etch stop layer between the first mandrel layer and the second mandrel layer, a second etch stop layer between the first mandrel layer and the fin hard mask layer, and a pad oxide layer between the fin hard mask layer and the layer to be patterned; S2: etching the second mandrel layer to form a plurality of second mandrels with predetermined intervals between each other;

[0023] S3: forming a first side wall on both sides of the second mandrel; S4: removing the second mandrel with the first etch stop layer as the stop layer, and retaining the first side wall; S5: etching the first etch stop layer and the first mandrel layer with the second etch stop layer as the stop layer and the first side wall as a mask to form a plurality of first mandrels; S6: removing the first side wall, and forming a second side wall covering both sides of the first mandrel; S7: removing the first mandrel, and retaining the second side wall; S8: forming a photoresist layer, and performing exposure and development to reveal at least one second side wall adjacent to both sides of the effective second side wall, protecting the effective second side wall and other second side walls with photoresist, and performing an etching process to remove the revealed at least one second side wall; S9: removing the photoresist; S10: removing the remaining second side walls; S11: removing the first side wall; S12: removing the first side wall; S13: removing the first side wall; S14: removing the second side wall; S15: removing the first side wall; S16: removing the first side wall; S17: removing the first side wall; S18: removing the first side wall; S19: removing the first side wall; S20: removing the first side wall; S21: removing the first side wall; S22: removing the first side wall; S23: removing the first side wall; S24: removing the first side wall; S25: removing the first side wall; The second side walls and the effective second side walls are etched as masks until the layer to be patterned, so as to form a plurality of discrete patterns on the layer to be patterned; S11: removing the remaining second side walls and the effective second side walls, forming a photoresist layer, and performing exposure and development to protect the discrete patterns corresponding to the effective second side walls with photoresist, revealing the discrete patterns corresponding to the other second side walls, and performing an etching process to etch away the revealed second etch stop layer, the fin hard mask layer, the pad oxide layer and part of the discrete patterns; S12: removing the photoresist; S13: forming an oxide layer, and performing a thermal annealing process, and then performing a planarization process with the fin hard mask layer as the stop layer; and S14: removing the fin hard mask layer and the pad oxide layer on the discrete patterns, and then removing part of the oxide layer to expose the discrete patterns to form an effective fin body.

[0024] For details, please refer to Figures 1a to 14a , Figures 1b to 14b and Figures 8c to 14c . Figures 1a to 14a The figure is a schematic top view of the structure of each step in the process of forming the fin of a semiconductor device according to an embodiment of the present invention. Figures 1b to 14b In the process of forming the fin of the semiconductor device according to one embodiment of the present invention, Figures 1a to 14a Schematic diagram of the cross-sectional structure along the line Y-Y'. Figures 8c to 14c In the process of forming the fin of the semiconductor device according to one embodiment of the present invention, Figures 8a to 14a A method for forming a semiconductor device fin according to an embodiment of the present invention includes:

[0025] S1: Figure 1a and 1b As shown, a semiconductor substrate 10 is provided, wherein the semiconductor substrate 10 comprises a layer to be patterned 101, a fin hard mask layer (Fin Hard Mask, Fin HM) 102, a first mandrel layer 103 and a second mandrel layer 104 stacked in sequence, a first etch stop layer (Etch Stop Layer, ESL) 105 is provided between the first mandrel layer 103 and the second mandrel layer 104, a second etch stop layer 106 is provided between the first mandrel layer 103 and the fin hard mask layer 102, and a pad oxide layer (Pad Oxide, PO) 107 is provided between the fin hard mask layer 102 and the layer to be patterned 101;

[0026] Specifically, in one embodiment, the layer to be patterned 101 is a silicon single crystal, a germanium single crystal or a silicon germanium single crystal. Alternatively, the layer to be patterned 101 may also be a silicon on insulator (SOI) substrate, a stacked silicon on insulator (SSOI), a stacked silicon germanium on an insulator (S-SiGeOI), a silicon germanium on an insulator (SiGeOI), a germanium on an insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor. The compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Preferably, the layer to be patterned 101 is a silicon single crystal. The pad oxide layer 107 is silicon oxide (SiO2). The fin hard mask layer 102 may be a combination of one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon carbide (SiC) and titanium oxide (TiO2). The pad oxide layer and the fin hard mask layer are used to protect the fin. The first etch stop layer 105 and the second etch stop layer 106 may be carbon-containing silicon nitride (NDC), silicon oxide or silicon nitride. The first etch stop layer 105 and the second etch stop layer 106 are used to prevent over-etching. The first mandrel layer 103 and the second mandrel layer 104 may be spin-on carbon (SOC), spin-on hard mask (SOH), amorphous silicon or amorphous carbon, etc. The materials of the first mandrel layer 103 and the second mandrel layer 104 may be the same or different.

[0027] S2: Figure 2a and 2b As shown, the second mandrel layer 104 is etched to form a plurality of second mandrels 108 with predetermined intervals between each other;

[0028] Specifically, a photolithography pattern is formed on the second mandrel layer 104, and the first mandrel layer 104 is etched using the photolithography pattern as a mask to form a plurality of second mandrels 108. Specifically, there is a predetermined interval between the second mandrels 108. Optionally, the intervals between the second mandrels 108 are equal.

[0029] S3: Figure 3a and 3b As shown, a first side wall 110 is formed on both sides of the second core shaft 108;

[0030] Specifically, a first spacer material layer covering the second mandrel 108 is deposited; and the first spacer material layer is etched back to form the first spacer 110. In an optional implementation, the spacer material may be silicon nitride. The spacer material layer may be formed by any technique known to those skilled in the art, preferably by chemical vapor deposition (CVD). Optionally, the back etching method may be anisotropic etching, and optionally, may be plasma etching (PE).

[0031] S4: Figure 4a and 4b As shown, the second mandrel 108 is removed by using the first etch stop layer 105 as a stop layer, and the first sidewall 110 is retained;

[0032] Optionally, the second mandrel 108 may be removed by a wet stripping (WS) method.

[0033] S5: Figure 5a and 5b As shown, the first etch stop layer 105 and the first mandrel layer 103 are etched using the second etch stop layer 106 as a stop layer and the first sidewall 110 as a mask to form a plurality of first mandrels 111;

[0034] Specifically, the first mandrel layer 103 may be etched by a wet etching process. After the etching is completed, the width of the first mandrel 111 is substantially the same as the width of the first sidewall 110 .

[0035] S6: Figure 6a and 6b As shown, the first side wall 110 is removed, and a second side wall 112 covering both sides of the first core shaft 111 is formed;

[0036] Specifically, a second spacer material layer covering the first core shaft 111 is deposited, and the second spacer material layer is etched back to form the second spacer 112. Specifically, the material of the second spacer 112 can be silicon nitride.

[0037] S7: Figure 7a and 7b As shown, the first core shaft 111 is removed and the second side wall 112 is retained;

[0038] Optionally, the first mandrel 111 may be removed by using a wet stripping (WS) method.

[0039] S8: Figure 8a and 8bAs shown, a photoresist layer is formed, and exposure and development are performed to reveal at least one second sidewall spacer 112 adjacent to both sides of the effective second sidewall spacer 112', the effective second sidewall spacer 112' and other second sidewall spacers 112 are protected by photoresist 220, and an etching process is performed to remove the revealed at least one second sidewall spacer 112;

[0040] like Figure 8a and 8b As shown, there are four effective second sidewalls 112', and two second sidewalls 112 adjacent to the effective second sidewalls 112' on both sides and covered by the region 210 are removed. Figure 8a and 8b Two of the second side walls 112 are removed, and of course, one of the second side walls 112 may be removed. Figure 8a and 8b There are four effective second sidewalls 112', but the present invention does not limit the number of effective second sidewalls 112'. This process is usually called a fine removal process or a horizontal removal process.

[0041] See also Figure 8c , Figure 8c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Figure 8a Schematic diagram of the cross-sectional structure of X-X'. Figure 8c As shown, in the XX′ direction, two second side walls 112 are included on both sides.

[0042] S9: Figure 9a and 9b As shown, the photoresist is removed;

[0043] See also Fig.9c , Fig.9c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Figure 9a Schematic diagram of the cross-sectional structure of X-X'.

[0044] S10: Fig.10a and 10b As shown, the remaining second spacer 112 and the effective second spacer 112 ′ are used as masks to etch until the layer to be patterned 101 , so as to form a plurality of discrete patterns 113 on the layer to be patterned 101 ;

[0045] Specifically, the second etch stop layer 106 , the fin hard mask layer 102 , the pad oxide layer 107 and the layer to be patterned 101 are etched using the remaining second spacer 112 and the effective second spacer 112 ′ as masks to form a plurality of discrete patterns 113 on the layer to be patterned 101 .

[0046] Specifically, a plurality of discrete patterns 113 corresponding to the remaining second spacers 112 and the effective second spacers 112 ′ are formed by a wet etching process using the remaining second spacers 112 and the effective second spacers 112 ′ as masks.

[0047] See also Fig.10c , Fig.10c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Fig.10a Schematic diagram of the cross-sectional structure of X-X'.

[0048] S11: Fig.11a and 11b As shown, the remaining second spacers 112 and the effective second spacers 112' are removed to form a photoresist layer, and exposure and development are performed to protect the discrete patterns 113 corresponding to the effective second spacers 112' with the photoresist 230, and the discrete patterns corresponding to the other second spacers 112 are revealed, and an etching process is performed to etch away the revealed second etch stop layer 106, the fin hard mask layer 102, the pad oxide layer 107, and the discrete patterns 113;

[0049] Specifically, an etching process is used to remove the remaining second sidewall spacer 112 and the effective second sidewall spacer 112 ′.

[0050] This process is usually called a roughness removal process.

[0051] See also Fig.11c , Fig.11c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Fig.11a Schematic diagram of the cross-sectional structure of X-X'.

[0052] S12: Fig.12a and 12b As shown, the photoresist 230 is removed;

[0053] See also Fig.12c , Fig.12c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Fig.12a Schematic diagram of the cross-sectional structure of X-X'.

[0054] S13: Fig.13a and 13b As shown, an oxide layer 114 is formed, and a thermal annealing process is performed, and then a planarization process is performed using the fin hard mask layer 102 as a stop layer;

[0055] See also Fig.13c , Fig.13c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Fig.13a Schematic diagram of the cross-sectional structure of X-X'.

[0056] S14: Fig.14a and 14b As shown, the fin hard mask layer 102 and the pad oxide layer 107 on the discrete pattern 113 are removed, and then a portion of the oxide layer 114 is removed to expose the discrete pattern 113 to form an effective fin body 115 .

[0057] See also Fig.14c , Fig.14c The process of forming the fin of the semiconductor device according to one embodiment of the present invention is as follows: Fig.14a Schematic diagram of the cross-sectional structure of X-X'.

[0058] Specifically, the oxide layer 114 located at the bottom of the effective fins 115 constitutes an isolation portion between the effective fins 115 .

[0059] Specifically, the height of the remaining oxide layer 114 in step S14 is higher than the height of the remaining discrete patterns of the photoresist-developed portion in step S9.

[0060] As described above, after forming the second side wall, at least one second side wall adjacent to both sides of the effective second side wall is removed through a fine removal process, so that at least one second side wall adjacent to both sides of the effective second side wall is not transferred to the layer to be patterned, thereby avoiding removing the fin body on both sides of the effective fin body through a fine removal process after the fin body is formed, thereby reducing the difficulty of the fine removal process and the requirements for the fine removal process, and after forming multiple discrete patterns on the layer to be patterned, the discrete patterns other than the discrete patterns corresponding to the effective second side wall are partially etched away through a rough removal process, so that the fine removal process and the rough removal process are performed separately, thereby reducing the difficulty of the two-step removal process.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for forming a fin of a semiconductor device, characterized in that: include: S1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a layer to be patterned, a fin hard mask layer, a first mandrel layer and a second mandrel layer stacked in sequence, a first etch stop layer is provided between the first mandrel layer and the second mandrel layer, a second etch stop layer is provided between the first mandrel layer and the fin hard mask layer, and a pad oxide layer is provided between the fin hard mask layer and the layer to be patterned; S2: etching the second mandrel layer to form a plurality of second mandrels with predetermined intervals between each other; S3: forming a first side wall on both sides of the second mandrel; S4: removing the second mandrel by using the first etch stop layer as a stop layer, and retaining the first sidewall; S5: etching the first etch stop layer and the first mandrel layer using the second etch stop layer as a stop layer and the first sidewall as a mask to form a plurality of first mandrels; S6: removing the first sidewall and forming a second sidewall covering both sides of the first core shaft; S7: removing the first mandrel and retaining the second side wall; S8: forming a photoresist layer, and performing exposure and development to open at least one second sidewall adjacent to both sides of the effective second sidewall, protecting the effective second sidewall and other second sidewalls with photoresist, and performing an etching process to remove the opened at least one second sidewall; S9: removing the photoresist; S10: etching until the to-be-patterned layer is formed by using the remaining second sidewall spacer and the effective second sidewall spacer as masks to form a plurality of discrete patterns on the to-be-patterned layer; S11: removing the remaining second sidewall spacers and the effective second sidewall spacers, forming a photoresist layer, and performing exposure and development to protect the discrete patterns corresponding to the effective second sidewall spacers with the photoresist, revealing the discrete patterns corresponding to the other second sidewall spacers, and performing an etching process to etch away the revealed second etch stop layer, the fin hard mask layer, the pad oxide layer, and part of the discrete patterns; S12: removing the photoresist; S13: forming an oxide layer, performing a thermal annealing process, and then performing a planarization process using the fin hard mask layer as a stop layer; as well as S14: removing the fin hard mask layer and the pad oxide layer on the discrete pattern, and then removing part of the oxide layer to expose the discrete pattern to form an effective fin body.

2. The method for forming a semiconductor device fin according to claim 1, characterized in that: In S2 , a photolithography pattern is formed above the second mandrel layer, and the first mandrel layer is etched using the photolithography pattern as a mask to form a plurality of second mandrels.

3. The method for forming a semiconductor device fin according to claim 1, characterized in that: In S3 , a first spacer material layer covering the second core shaft is deposited; and the first spacer material layer is etched back to form the first spacer.

4. The method for forming a semiconductor device fin according to claim 1, characterized in that: In S6 , a second spacer material layer covering the first core shaft is deposited; and the second spacer material layer is etched back to form the second spacer.

5. The method for forming a semiconductor device fin according to claim 1, wherein: In S8 , two second side walls adjacent to the effective second side wall are removed.

6. The method for forming a semiconductor device fin according to claim 1, characterized in that: In S14 , the oxide layer at the bottom of the active fins forms an isolation portion between the active fins.

7. The method for forming a semiconductor device fin according to claim 1, characterized in that: The height of the remaining oxide layer in step S14 is higher than the height of the remaining discrete patterns of the photoresist developed portion in step S9.

8. The method for forming a semiconductor device fin according to claim 1, characterized in that: The layer to be patterned is a silicon single crystal, a germanium single crystal or a silicon-germanium single crystal.

9. The method for forming a semiconductor device fin according to claim 1, characterized in that: The second mandrels are spaced equally apart.

10. The method for forming a semiconductor device fin according to claim 1, characterized in that: In S10 , a plurality of discrete patterns corresponding to the remaining second spacers and the effective second spacers are formed by a wet etching process using the remaining second spacers and the effective second spacers as masks.

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