Semiconductor packaging structure and method for preparing semiconductor packaging structure

Abstract

The embodiments of the present invention provide a semiconductor packaging structure and a method for preparing the semiconductor packaging structure, which relate to the field of semiconductor packaging technology. The semiconductor packaging structure includes a substrate, a first chip, a second chip, a heat dissipation column, a first plastic package and a solder ball. The heat dissipation column is arranged on a side surface of the substrate and is located between the first chip and the second chip. A metal layer is arranged on a side surface of the substrate. The bottom of the heat dissipation column is connected to the metal layer and is used to dissipate heat from the substrate. By arranging a heat dissipation column between the first chip and the second chip, and the heat dissipation column is arranged on the metal layer of the substrate, a good heat dissipation effect can be achieved. Compared with the prior art, the semiconductor packaging structure provided by the present invention can achieve a good heat dissipation effect on the substrate, thereby improving the heat dissipation capacity of the entire device and ensuring the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and a method for preparing the semiconductor packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, double-sided packaging product structures or multi-chip packaging product structures mainly form packaging structures on the front and back sides or on a single side of a substrate. Since there are multiple packaging materials in the semiconductor packaging structure formed on the substrate and multiple chips need to be packaged, the heat dissipation capacity of the substrate and the chip is poor, affecting the performance of the device. Summary of the invention

[0003] The objectives of the present invention include, for example, providing a semiconductor packaging structure and a method for preparing the semiconductor packaging structure, which can improve the heat dissipation capability of the device.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a semiconductor packaging structure, comprising:

[0006] substrate;

[0007] A first chip and a second chip are mounted on a surface of one side of the substrate at intervals;

[0008] A heat dissipation column disposed on one side surface of the substrate and located between the first chip and the second chip;

[0009] A first plastic package body disposed on one side surface of the substrate and covering at least the first chip and the second chip;

[0010] and, solder balls disposed on the other side surface of the substrate;

[0011] Among them, the first chip, the second chip and the third chip are all electrically connected to the substrate, a metal layer is provided on one side surface of the substrate, the bottom of the heat dissipation column is connected to the metal layer and is used to dissipate heat from the substrate, and the solder balls are located on at least two sides of the second plastic package and are electrically connected to the substrate.

[0012] In an optional embodiment, the semiconductor package structure further includes a third chip mounted on the other side surface of the substrate, and a second plastic package body disposed on the other side surface of the substrate and covering the third chip.

[0013] In an optional implementation, the first plastic package body is also covered outside the heat dissipation column.

[0014] In an optional embodiment, a plurality of heat dissipation grooves are provided on the heat dissipation column, and each of the heat dissipation grooves penetrates from the surface of the heat dissipation column to the surface of the metal layer.

[0015] In an optional embodiment, a plurality of first grooves are further provided on the surface of the metal layer, and the plurality of first grooves are located at the bottom of the heat dissipation column and are correspondingly connected to the plurality of heat dissipation slots.

[0016] In an optional embodiment, the first chip and the second chip have the same thickness, and a distance H1 between a surface of the first plastic package away from the substrate and the first chip is greater than a distance H2 between a surface of the first plastic package away from the substrate and the heat dissipation column.

[0017] In an optional embodiment, a distance H1 between a surface of the first plastic package body away from the substrate and the first chip is twice a distance H2 between a surface of the first plastic package body away from the substrate and the heat dissipation column.

[0018] In an optional embodiment, a wiring layer is disposed in the substrate, a metal pad electrically connected to the wiring layer is disposed on the other surface of the substrate, and the solder ball is disposed on the metal pad.

[0019] In an optional implementation, a second groove is further provided on the surface of the metal pad, and the solder ball covers the second groove.

[0020] In an optional embodiment, a clearance opening groove penetrating to the substrate is formed on the first plastic packaging body, and the clearance opening groove corresponds to the heat dissipation column, so that the heat dissipation column is exposed outside the first plastic packaging body.

[0021] In an optional embodiment, the first plastic packaging body partially covers the heat dissipation column, and an end of the heat dissipation column away from the substrate partially extends out of the first plastic packaging body.

[0022] In an optional embodiment, an extended heat dissipation plate is provided at the edge of the heat dissipation column, and the extended heat dissipation plate is attached to a surface of the first plastic package body on a side away from the substrate.

[0023] In an optional implementation, the extended heat dissipation plate covers a surface of a side of the first plastic packaging body away from the substrate, and extends to an edge of the first plastic packaging body.

[0024] In an optional embodiment, a fourth chip is further disposed on a side of the first plastic package body away from the substrate. The fourth chip is mounted on the heat dissipation column and is electrically connected to the substrate.

[0025] In an optional embodiment, the fourth chip is a front-mounted chip, and a conductive arc is provided on a side of the fourth chip away from the substrate, the conductive arc is connected to the substrate, and a filling glue layer covering the conductive arc and the fourth chip is also provided on the substrate.

[0026] In an optional embodiment, the fourth chip is a flip chip, the heat dissipation column is conductive, the fourth chip is electrically connected to the substrate via the heat dissipation column, and a third plastic package or filling glue layer covering the fourth chip is further provided on the substrate.

[0027] In an optional embodiment, a portion of the heat dissipation column extending out of the first plastic package body is provided with a plurality of third grooves.

[0028] In a second aspect, the present invention provides a method for preparing a semiconductor packaging structure, comprising:

[0029] forming a heat dissipation column on the substrate;

[0030] Mounting a first chip and a second chip on the substrate at two sides of the heat dissipation column at intervals;

[0031] Plastic encapsulation is performed on the substrate to form a first plastic encapsulation body at least covering the first chip and the second chip;

[0032] Turning over the substrate, and mounting a third chip on the substrate;

[0033] Plastic encapsulation is performed on the substrate to form a second plastic encapsulation body covering the third chip;

[0034] forming solder balls on the substrate;

[0035] Among them, the first chip, the second chip and the third chip are all electrically connected to the substrate, a metal layer is provided on one side surface of the substrate, the bottom of the heat dissipation column is connected to the metal layer and is used to dissipate heat from the substrate, and the solder balls are located on at least two sides of the second plastic package and are electrically connected to the substrate.

[0036] In an optional embodiment, the step of forming a heat dissipation column on the substrate includes:

[0037] forming a dry film layer on a substrate;

[0038] Etching the dry film layer to form an etching opening;

[0039] forming a heat dissipation column in the etched opening;

[0040] removing the dry film layer;

[0041] Micro-etching is performed on the bottom of the heat dissipation column to form a first groove.

[0042] The beneficial effects of the embodiments of the present invention include, for example:

[0043] The semiconductor packaging structure and the method for preparing the semiconductor packaging structure provided by the present invention realize multi-chip packaging by mounting a first chip and a second chip on a substrate, and a heat dissipation column is arranged between the first chip and the second chip, and the heat dissipation column is arranged on the metal layer of the substrate, which can achieve a good heat dissipation effect. Compared with the prior art, the semiconductor packaging structure provided by the present invention can achieve a good heat dissipation effect on the substrate, thereby improving the heat dissipation capacity of the entire device and ensuring the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of a semiconductor package structure provided by a first embodiment of the present invention;

[0046] Figure 2 for Figure 1 A partial enlarged schematic diagram of middle Ⅱ;

[0047] Figures 3 to 11 A process flow chart of a method for preparing a semiconductor packaging structure provided by a first embodiment of the present invention;

[0048] Fig.12 A schematic diagram of a semiconductor package structure provided by a second embodiment of the present invention;

[0049] Fig.13 A schematic diagram of a semiconductor package structure provided by a third embodiment of the present invention;

[0050] Fig.14 A schematic diagram of a semiconductor package structure provided by a fourth embodiment of the present invention;

[0051] Fig.15 A schematic diagram of a semiconductor package structure provided by a fifth embodiment of the present invention;

[0052] Fig.16 A schematic diagram of a semiconductor package structure provided by a sixth embodiment of the present invention;

[0053] Fig.17 A schematic diagram of a semiconductor package structure provided by a seventh embodiment of the present invention.

[0054] Icons: 100-semiconductor packaging structure; 110-substrate; 111-solder ball; 113-metal layer; 115-wiring layer; 117-metal pad; 119-second groove; 120-first chip; 130-second chip; 140-heat dissipation column; 141-heat dissipation groove; 143-first groove; 145-expanded heat dissipation plate; 150-first plastic package; 151-opening groove; 160-third chip; 170-second plastic package; 180-fourth chip; 181-conductive wire arc; 183-filling glue layer; 190-third plastic package; 191-third groove; 200-dry film layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0058] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0059] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0060] As disclosed in the background technology, the existing semiconductor packaging structure uses multiple chips, which generates a lot of heat, and the plastic package needs to cover multiple chips, resulting in poor overall heat dissipation of the device, which will affect the performance of the device. In addition, since there are multiple packaging materials in the semiconductor packaging structure formed on the substrate, and different packaging materials are used, the CTE coefficients between the materials are different. During the reliability test of the product, the plastic package and the chip surface are prone to delamination problems, and the plastic package and the substrate are prone to delamination problems. Moreover, the existing semiconductor packaging structure can only achieve double-sided packaging, and it is difficult to improve the integration level and cannot achieve stacking.

[0061] In order to solve the above problems, the present invention provides the following novel semiconductor packaging structure and method for preparing the semiconductor packaging structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0062] First embodiment

[0063] See also Figure 1 and Figure 2 This embodiment provides a semiconductor packaging structure 100, which can achieve a good heat dissipation effect on the substrate 110, thereby improving the heat dissipation capacity of the entire device and ensuring device performance. At the same time, it can avoid the problem of plastic package delamination and ensure the stability of the structure.

[0064] The semiconductor package structure 100 provided in this embodiment includes a substrate 110, a first chip 120, a second chip 130, a heat dissipation column 140, a first plastic package 150, a third chip 160, a second plastic package 170 and a solder ball 111. The first chip 120 and the second chip 130 are mounted on a side surface of the substrate 110 at intervals. The heat dissipation column 140 is also arranged on a side surface of the substrate 110 and is located between the first chip 120 and the second chip 130. The first plastic package 150 is arranged on a side surface of the substrate 110 and at least covers the first chip 120 and the second chip 130. The third chip 160 is mounted on the other side surface of the substrate 110, the second plastic package 170 is arranged on the other side surface of the substrate 110 and covers the third chip 160, and the solder balls 111 are arranged on the other side surface of the substrate 110, wherein the first chip 120, the second chip 130 and the third chip 160 are all electrically connected to the substrate 110, a metal layer 113 is arranged on one side surface of the substrate 110, the bottom of the heat dissipation column 140 is connected to the metal layer 113 and is used to dissipate heat for the substrate 110, and the solder balls 111 are located on at least two sides of the second plastic package 170 and are electrically connected to the substrate 110.

[0065] In this embodiment, one side surface of the substrate 110 has a mounting area and a heat dissipation area, the mounting area is located on both sides of the heat dissipation area, the metal layer 113 is arranged in the heat dissipation area, and the heat dissipation area is located at the center of the substrate 110, and the first chip 120 and the second chip 130 are mounted in the mounting area respectively, and are electrically connected to the substrate 110. At the same time, in this embodiment, the mounting position of the third chip 160 corresponds to the heat dissipation area, so that the solder balls 111 can be distributed around the second plastic package 170. The second plastic package 170 adopts a selective plastic packaging process, which only covers the outer edge of the third chip 160 and does not cover the entire surface of the substrate 110, thereby facilitating the arrangement of the solder balls 111.

[0066] It is worth noting that a double-sided packaging structure is adopted in this embodiment. Meanwhile, in other preferred embodiments of the present invention, the third chip 160 and the second plastic package body 170 may not be provided on the other side surface of the substrate 110, thereby forming a single-sided packaging structure.

[0067] In this embodiment, the first plastic package 150 is also coated outside the heat dissipation column 140. Specifically, the first plastic package 150 is integrally plastic-sealed outside the first chip 120, the second chip 130 and the heat dissipation column 140, thereby covering the entire surface of the substrate 110, and the first chip 120, the second chip 130 and the heat dissipation column 140 are all coated therein, thereby playing a good protective role.

[0068] In this embodiment, a plurality of heat dissipation grooves 141 are provided on the heat dissipation column 140, and each heat dissipation groove 141 penetrates from the surface of the heat dissipation column 140 to the surface of the metal layer 113. Specifically, by providing the heat dissipation grooves 141, the heat dissipation column 140 can be divided into a plurality of column structures, so that the molding compound can be filled in the heat dissipation grooves 141 during the molding, thereby improving the bonding force between the first molding body 150, the heat dissipation column 140 and the substrate 110.

[0069] In this embodiment, the heat dissipation column 140 is a copper column, and is formed on the metal layer 113 by electroplating, so that the heat dissipation column 140 has a good heat dissipation effect and can transfer heat to the outside. Of course, in other preferred embodiments, the heat dissipation column 140 can also be made of other thermally conductive materials, such as silver columns or aluminum columns, etc., which are not specifically limited here.

[0070] In this embodiment, a plurality of first grooves 143 are further provided on the surface of the metal layer 113. The plurality of first grooves 143 are located at the bottom of the heat dissipation column 140 and are correspondingly connected to the plurality of heat dissipation grooves 141. Specifically, the heat dissipation grooves 141 are connected to the plurality of first grooves 143 in a one-to-one correspondence. After the heat dissipation column 140 is formed, the first grooves 143 can be formed by continuing to etch on the metal layer 113 through a micro-etching process. By providing the first grooves 143, the plastic packaging material can continue to fill downward, thereby improving the bonding force between the first plastic packaging body 150, the heat dissipation column 140 and the substrate 110.

[0071] It should be noted that in this embodiment, the width of the first groove 143 is equivalent to the width of the heat dissipation groove 141, and the heat dissipation column 140 is formed by a metal electroplating process, so that the heat dissipation column 140 and the metal layer 113 can be formed as one, further facilitating the heat transfer, and at the same time, the plastic packaging material of the first plastic packaging body 150 can continue to fill the first groove 143, so that the first plastic packaging body 150 and the metal layer 113 can be embedded in each other, thereby improving the bonding force between the first plastic packaging body 150 and the substrate 110, thereby preventing the stratification problem between the substrate 110 and the first plastic packaging body 150.

[0072] In this embodiment, the first chip 120 and the second chip 130 have the same thickness, and the distance H1 between the first chip 120 and the surface of the first plastic package 150 away from the substrate 110 is greater than the distance H2 between the surface of the first plastic package 150 away from the substrate 110 and the heat dissipation column 140. Specifically, the first chip 120 and the second chip 130 are both flip chips, and the thickness of the two is the same, so that the height of the first chip 120 and the second chip 130 is the same, and the first plastic package 150 completely covers the first chip 120, the second chip 130 and the heat dissipation column 140, so that the thickness of the first plastic package 150 at the first chip 120 and the second chip 130 is greater than the thickness at the heat dissipation column 140. By forming the first plastic package 150 with different thicknesses at the first chip 120 and the heat dissipation column 140, the first plastic package 150 is prevented from having the same layer thickness at various locations, and the problem of layering between the back of the chip and the first plastic package 150 is prevented. Of course, in other preferred embodiments of the present invention, the first chip 120 and the second chip 130 may also be face-up chips, and be electrically connected to the substrate 110 by wire bonding.

[0073] It should be noted that, in this embodiment, the distance H1 between the side surface of the first plastic package 150 away from the substrate 110 and the first chip 120 refers to the distance between the back side of the first chip 120 and the surface of the first plastic package 150, and the distance H2 between the side surface of the first plastic package 150 away from the substrate 110 and the heat dissipation column 140 in this embodiment refers to the distance between one end of the heat dissipation column 140 away from the substrate 110 and the surface of the first plastic package 150.

[0074] In this embodiment, the distance H1 between the first chip 120 and the side surface of the first plastic package 150 away from the substrate 110 is twice the distance H2 between the side surface of the first plastic package 150 away from the substrate 110 and the heat dissipation column 140. Specifically, by reasonably setting the ratio of H1 and H2, the first plastic package 150 can be better prevented from being delaminated.

[0075] In this embodiment, a wiring layer 115 is provided in the substrate 110, and a metal pad 117 electrically connected to the wiring layer 115 is provided on the other side surface of the substrate 110, and the solder ball 111 is provided on the metal pad 117. Specifically, the wiring layer 115 adopts a conventional wiring structure, and the metal pad 117 is provided on at least two sides of the second plastic package 170, and the solder ball 111 can be connected to the wiring layer 115 through the copper column. The solder ball 111 adopts a tin ball, and preferably, the height of the solder ball 111 relative to the substrate 110 is greater than the height of the second plastic package 170, so as to better achieve external welding.

[0076] In this embodiment, the surface of the metal pad 117 is further provided with a second groove 119, and the solder ball 111 covers the second groove 119. Specifically, the second groove 119 can also be formed on the metal pad 117 by micro-etching, and the second groove 119 is located at the center of the metal pad 117. By providing the second groove 119, a buffering effect can be played when the solder ball 111 is formed, thereby releasing the internal stress of the solder ball 111 and improving the bonding force of the solder ball 111.

[0077] See also Figures 3 to 11 This embodiment also provides a method for preparing a semiconductor package structure 100, which includes the following steps:

[0078] S1 : forming a heat dissipation column 140 on the substrate 110 .

[0079] See also Figures 3 to 6Specifically, a substrate 110 is provided, and a heat dissipation column 140 is formed on the substrate 110. When performing step S1, a dry film layer 200 can be formed on the substrate 110, and then the dry film layer 200 is etched to form an etching opening, and then the heat dissipation column 140 is formed in the etching opening, and then the dry film layer 200 is removed, and finally the bottom of the heat dissipation column 140 is micro-etched to form a first groove 143, thereby completing the process of the heat dissipation column 140. Among them, the thickness of the dry film layer 200 can be set according to the height of the heat dissipation column 140.

[0080] In actual preparation, a substrate 110 can be first taken, and a heat dissipation area and a mounting area can be demarcated on the substrate 110. A copper column is formed in the heat dissipation area. The copper column manufacturing process can be to first lay a layer of dry film on the substrate 110, and then use an etching method to etch away the area where the copper column needs to be formed, and then electroplate copper in the opening to form a copper column structure, remove the dry film, and then micro-etch at the bottom of the copper column to form a first groove 143 structure.

[0081] S2: mounting the first chip 120 and the second chip 130 on the substrate 110 at both sides of the heat dissipation pillar 140 at intervals.

[0082] See also Figure 7 Specifically, after the heat dissipation column 140 is formed, the first chip 120 and the second chip 130 are mounted using a flip-chip process or a face-up process. The first chip 120 and the second chip 130 are both connected to the pads on the surface of the substrate 110, thereby achieving electrical connection between the first chip 120 and the second chip 130 and the substrate 110.

[0083] S3: Forming a first plastic package body 150 on the substrate 110 to at least cover the first chip 120 and the second chip 130 .

[0084] See also Figure 8 Specifically, the plastic encapsulation process is used to fill the mounting area and the heat dissipation area of ​​the first chip 120 and the second chip 130 with plastic encapsulation material, and after curing, a first plastic encapsulation body 150 is formed that simultaneously covers the first chip 120, the second chip 130 and the heat dissipation column 140.

[0085] S4 : turning over the substrate 110 , and mounting the third chip 160 on the substrate 110 .

[0086] See also Fig. 9 Specifically, after the substrate 110 is turned over, the third chip 160 is mounted on the back side of the substrate 110 again using a face-up or flip-chip process.

[0087] S5: Forming a second plastic packaging body 170 on the substrate 110 to cover the third chip 160 .

[0088] See also Fig.10 Specifically, after the third chip 160 is mounted, a second plastic package body 170 is formed using a plastic packaging process. When forming the second plastic package body 170, a selective plastic packaging process can be used so that the second plastic package body 170 only covers the third chip 160, thereby avoiding the metal pads 117 on the substrate 110 for ball planting.

[0089] S6 : forming solder balls 111 on the substrate 110 .

[0090] See also Fig.11 Specifically, after the second plastic package body 170 is formed, the solder balls are prepared by using a ball planting process, and then the product is cut into individual pieces by a cutting process.

[0091] In summary, the semiconductor package structure 100 and the method for preparing the semiconductor package structure 100 provided in this embodiment realize double-sided packaging by mounting the first chip 120, the second chip 130 and the third chip 160 on both sides of the substrate 110 respectively, and a heat dissipation column 140 is arranged between the first chip 120 and the second chip 130, and the heat dissipation column 140 is arranged on the metal layer 113 of the substrate 110, which can achieve a good heat dissipation effect. In addition, by forming a first groove 143 at the bottom of the heat dissipation column 140, the bonding force between the first plastic package 150 and the substrate 110, and between the first plastic package 150 and the heat dissipation column 140 can be further improved, thereby avoiding the delamination phenomenon between the first plastic package 150 and the substrate 110. At the same time, the height of the heat dissipation column 140 is different from the height of the first chip 120 and the second chip 130, which can avoid the delamination phenomenon between the first plastic package 150 and the back of the chip. In addition, the metal pad 117 is also provided with a second groove 119 , which can play a buffering role when preparing the solder ball 111 , thereby releasing the internal stress of the solder ball 111 and improving the bonding force between the solder ball 111 and the metal pad 117 .

[0092] Second embodiment

[0093] See also Fig.12 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0094] In this embodiment, a clearance opening groove 151 penetrating to the substrate 110 is formed on the first plastic package 150, and the clearance opening groove 151 corresponds to the heat dissipation column 140, so that the heat dissipation column 140 is exposed outside the first plastic package 150. Specifically, when forming the first plastic package 150, a selective plastic packaging process can be adopted, so that the first plastic package 150 is formed into two plastic packages arranged at intervals, and respectively covers the first chip 120 and the second chip 130.

[0095] In this embodiment, the opening groove 151 corresponds to the heat dissipation area on the substrate 110, so that the heat dissipation column 140 can be directly exposed to the outside, further improving its heat dissipation capacity. In addition, the heat dissipation column 140 is provided with a plurality of heat dissipation grooves 141, so that the heat dissipation area of ​​the heat dissipation column 140 can be further increased, thereby improving the heat dissipation capacity.

[0096] It should be noted that, in this embodiment, the height of the heat dissipation column 140 can be less than the height of the first plastic package 150. The formation process of the heat dissipation column 140 is the same as that of the first embodiment. Compared with the first embodiment, the difference in the preparation process lies in the preparation of the first plastic package 150. The first plastic package 150 adopts a selective plastic packaging process, and simultaneously forms two plastic package structures covering the outside of the first chip 120 and the outside of the second chip 130.

[0097] Third embodiment

[0098] See also Fig.13 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0099] In this embodiment, the first plastic package 150 partially covers the heat dissipation column 140, and one end of the heat dissipation column 140 away from the substrate 110 partially extends out of the first plastic package 150. Specifically, the height of the heat dissipation column 140 is higher than the height of the first plastic package 150, so that the top of the heat dissipation column 140 can partially extend out of the first plastic package 150 and be exposed to the outside, which can improve its heat dissipation capacity.

[0100] In this embodiment, an extended heat sink 145 is provided at the edge of the heat sink 140, and the extended heat sink 145 is attached to the surface of the first plastic package 150 away from the substrate 110. The extended heat sink 145 is horizontally attached to the surface of the first plastic package 150, and the extended heat sink 145 and the heat sink 140 form an L-shaped structure. On the one hand, by providing the extended heat sink 145, the contact area with the first plastic package 150 can be increased, thereby improving the bonding force between the first plastic package 150 and the L-shaped structure. On the other hand, the extended heat sink 145 is attached to the surface of the first plastic package 150, which can press the first plastic package 150, reduce the warping phenomenon of the substrate 110, and prevent the delamination problem on the back of the first chip 120 and the second chip 130.

[0101] It should be noted that in this embodiment, the extended heat sink 145 and the heat sink 140 are both made of metal materials, and the extended heat sink 145 is distributed at least on both sides of the edge of the top of the heat sink 140, and is limited between the first chip 120 and the second chip 130, so that the extended heat sink 145 will not shield the first chip 120 and the second chip 130, thereby ensuring the performance of the device.

[0102] Fourth embodiment

[0103] See also Fig.14 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the third embodiment.

[0104] In this embodiment, an extended heat dissipation plate 145 is provided at the edge of the heat dissipation column 140, and the extended heat dissipation plate 145 is attached to the surface of the first plastic package 150 away from the substrate 110, and the extended heat dissipation plate 145 covers the surface of the first plastic package 150 away from the substrate 110, and extends to the edge of the first plastic package 150. Specifically, the extended heat dissipation plate 145 covers the entire surface of the first plastic package 150, thereby further increasing the contact area with the first plastic package 150 and better playing a pressing role.

[0105] In this embodiment, the extended heat sink 145 is integrally provided with the heat sink 140 and is made of metal material. Meanwhile, the heat sink 140 is connected to the metal layer 113, and the extended heat sink 145 completely shields the first chip 120 and the second chip 130. In this case, the metal layer 113 is connected to the grounding line in the wiring layer 115, so that the metal layer 113 can be grounded, and the extended heat sink 145 further plays the role of partitioned electromagnetic shielding.

[0106] It should be noted that in this embodiment, the extended heat sink 145 can be implemented by electroplating. By setting up an extended heat sink 145 that completely covers the surface of the first plastic packaging body 150, the contact area with the first plastic packaging body 150 can be further increased, and the pressing effect can be better achieved. It can be directly and completely pressed on the surface of the first plastic packaging body 150, thereby achieving a better anti-warping effect.

[0107] Fifth embodiment

[0108] See also Fig.15 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment or the third embodiment. For the sake of brief description, parts not mentioned in this embodiment may refer to the corresponding contents in the first embodiment or the third embodiment.

[0109] In this embodiment, a fourth chip 180 is further disposed on the side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation column 140 and electrically connected to the substrate 110. Specifically, the fourth chip 180 is disposed corresponding to the heat dissipation area on the substrate 110 and mounted on the heat dissipation column 140, and the heat dissipation column 140 can play a good supporting role.

[0110] In this embodiment, the fourth chip 180 is a normal-mounted chip, and a conductive arc 181 is provided on the side of the fourth chip 180 away from the substrate 110, and the conductive arc 181 is connected to the substrate 110. The substrate 110 is also provided with a filling glue layer 183 covering the conductive arc 181 and the fourth chip 180. Specifically, the fourth chip 180 is normal-mounted on the heat dissipation column 140, and the filling glue layer 183 covers the substrate 110 and the first plastic package 150 at the same time, so that the fourth chip 180 and the conductive arc 181 are both covered inside, which plays a good protective role.

[0111] In this embodiment, the first chip 120 and the heat dissipation column 140 may also be fixed by using adhesive. Specifically, the adhesive is filled between the first chip 120 and the heat dissipation column 140, thereby achieving a good bonding and fixing effect.

[0112] In this embodiment, the middle position of the heat dissipation column 140 does not need to be filled with plastic packaging material, thereby ensuring the heat dissipation effect.

[0113] It should be noted that the chip structure can continue to be stacked on the fourth chip 180 here, so as to further increase the number of stacked devices.

[0114] The semiconductor package structure 100 provided in this embodiment can further increase the number of stacking of the package structure by stacking the fourth chip 180, thereby improving the integration of the device. At the same time, by providing the filling glue layer 183, the wire bonding structure can be effectively protected to improve the structural reliability.

[0115] Sixth embodiment

[0116] See also Fig.16 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the third embodiment.

[0117] In this embodiment, a fourth chip 180 is further disposed on a side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation column 140 and electrically connected to the substrate 110. Specifically, the fourth chip 180 is disposed corresponding to the heat dissipation area on the substrate 110 and mounted on the heat dissipation column 140, and the heat dissipation column 140 can play a good supporting role. At the same time, the fourth chip 180 adopts a flip-chip structure.

[0118] In this embodiment, the fourth chip 180 is a flip chip, the heat dissipation column 140 is conductive, the fourth chip 180 is electrically connected to the substrate 110 through the heat dissipation column 140, and the substrate 110 is also provided with a third plastic package 190 covering the fourth chip 180. Specifically, the heat dissipation column 140 is connected to the metal layer 113, and the metal layer 113 is connected to the wiring layer 115 through the conductive column at the bottom, so that the fourth chip 180 can be electrically connected to the substrate 110 through the heat dissipation column 140, and the third plastic package 190 can completely cover the surface of the first plastic package 150, thereby playing a good protective role.

[0119] In this embodiment, the heat dissipation column 140 is a copper column, and the fourth chip 180 is welded on the heat dissipation column 140. In addition, the heat dissipation column 140 is exposed outside the first plastic package 150, and a plurality of third grooves 191 are provided on the portion of the heat dissipation column 140 extending out of the first plastic package 150. By providing the third grooves 191, the bonding force of the bottom of the third plastic package 190 can be improved, thereby avoiding the delamination phenomenon between the third plastic package 190 and the first plastic package 150.

[0120] The semiconductor package structure 100 provided in this embodiment can further increase the number of stacking of the package structure by stacking the fourth chip 180, thereby improving the integration of the device. At the same time, by providing the third groove 191, the bonding force at the bottom of the third plastic package 190 can be further improved, thereby avoiding the delamination phenomenon between the third plastic package 190 and the first plastic package 150.

[0121] Seventh embodiment

[0122] See also Fig.17 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the third embodiment.

[0123] In this embodiment, a fourth chip 180 is further disposed on the side of the first plastic package 150 away from the substrate 110, and the fourth chip 180 is mounted on the heat dissipation column 140 and electrically connected to the substrate 110. The fourth chip 180 is a flip chip, the heat dissipation column 140 is conductive, the fourth chip 180 is electrically connected to the substrate 110 through the heat dissipation column 140, and a filling glue layer 183 or a protective cover covering the fourth chip 180 is further disposed on the substrate 110.

[0124] In this embodiment, a filling glue layer 183 is preferably used. By setting the filling glue layer 183, the fourth chip 180 can be well protected, and the filling glue layer 183 can only cover the fourth chip 180, so there is no need to cover the entire surface of the first plastic package 150, and the cost is low.

[0125] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; A first chip and a second chip are mounted on a surface of one side of the substrate at intervals; A heat dissipation column disposed on a surface of one side of the substrate and located between the first chip and the second chip; A first plastic package body disposed on one side surface of the substrate and covering at least the first chip and the second chip; and, solder balls disposed on the other side surface of the substrate; The first chip and the second chip are both electrically connected to the substrate, a metal layer is provided on one side surface of the substrate, the bottom of the heat dissipation column is connected to the metal layer and is used to dissipate heat for the substrate, and the solder ball is electrically connected to the substrate; The semiconductor packaging structure further includes: A third chip mounted on the other surface of the substrate; and, a second plastic package body disposed on the other side surface of the substrate and covering the third chip; Wherein, the solder balls are located on at least two sides of the second plastic package body.

2. The semiconductor package structure according to claim 1, wherein: The first plastic package body also covers the outside of the heat dissipation column.

3. The semiconductor package structure according to claim 2, characterized in that: A plurality of heat dissipation slots are arranged on the heat dissipation column, and each of the heat dissipation slots penetrates from the surface of the heat dissipation column to the surface of the metal layer.

4. The semiconductor package structure according to claim 3, characterized in that: A plurality of first grooves are also provided on the surface of the metal layer. The plurality of first grooves are located at the bottom of the heat dissipation columns and are correspondingly connected to the plurality of heat dissipation slots.

5. The semiconductor package structure according to claim 2, wherein: The first chip and the second chip have the same thickness, and a distance H1 between a surface of the first plastic package away from the substrate and the first chip is greater than a distance H2 between a surface of the first plastic package away from the substrate and the heat dissipation column.

6. The semiconductor package structure according to claim 5, characterized in that: A distance H1 between a surface of the first plastic package body away from the substrate and the first chip is twice a distance H2 between a surface of the first plastic package body away from the substrate and the heat dissipation column.

7. The semiconductor package structure according to claim 1, wherein: A wiring layer is arranged in the substrate, a metal pad electrically connected to the wiring layer is arranged on the other side surface of the substrate, and the solder ball is arranged on the metal pad.

8. The semiconductor package structure according to claim 7, characterized in that: A second groove is also provided on the surface of the metal pad, and the solder ball covers the second groove.

9. The semiconductor package structure according to claim 1, wherein: The first plastic package body is formed with a clearance opening groove penetrating to the substrate, and the clearance opening groove corresponds to the heat dissipation column, so that the heat dissipation column is exposed outside the first plastic package body.

10. The semiconductor package structure according to claim 1, wherein: The first plastic package body partially covers the heat dissipation column, and one end of the heat dissipation column away from the substrate partially extends out of the first plastic package body.

11. The semiconductor package structure according to claim 10, characterized in that: An extended heat dissipation plate is arranged at the edge of the heat dissipation column, and the extended heat dissipation plate is attached to a surface of the first plastic package body on a side away from the substrate.

12. The semiconductor package structure according to claim 11, characterized in that: The extended heat dissipation plate covers a surface of the first plastic packaging body on one side away from the substrate, and extends to an edge of the first plastic packaging body.

13. The semiconductor package structure according to any one of claims 10 to 12, characterized in that: A fourth chip is also arranged on a side of the first plastic package body away from the substrate. The fourth chip is mounted on the heat dissipation column and is electrically connected to the substrate.

14. The semiconductor package structure according to claim 13, characterized in that: The fourth chip is a front-mounted chip, and a conductive arc is arranged on a side of the fourth chip away from the substrate, the conductive arc is connected to the substrate, and a filling glue layer covering the conductive arc and the fourth chip is also arranged on the substrate.

15. The semiconductor package structure according to claim 13, wherein: The fourth chip is a flip chip, the heat dissipation column is conductive, the fourth chip is electrically connected to the substrate via the heat dissipation column, and a third plastic package or a filling glue layer covering the fourth chip is further provided on the substrate.

16. The semiconductor package structure according to claim 15, characterized in that: The portion of the heat dissipation column extending out of the first plastic package body is provided with a plurality of third grooves.

17. A method for preparing a semiconductor package structure, used for preparing the semiconductor package structure as claimed in claim 1, characterized in that: include: forming a heat dissipation column on the substrate; Mounting a first chip and a second chip on the substrate at two sides of the heat dissipation column at intervals; Plastic encapsulation is performed on the substrate to form a first plastic encapsulation body at least covering the first chip and the second chip; Turning over the substrate, and mounting a third chip on the substrate; Plastic encapsulation is performed on the substrate to form a second plastic encapsulation body covering the third chip; forming solder balls on the substrate; Among them, the first chip, the second chip and the third chip are all electrically connected to the substrate, a metal layer is provided on one side surface of the substrate, the bottom of the heat dissipation column is connected to the metal layer and is used to dissipate heat for the substrate, and the solder balls are located on at least two sides of the second plastic package and are electrically connected to the substrate.

18. The method for preparing a semiconductor packaging structure according to claim 17, characterized in that: The step of forming a heat dissipation column on a substrate comprises: forming a dry film layer on a substrate; Etching the dry film layer to form an etching opening; forming a heat dissipation column in the etched opening; removing the dry film layer; Micro-etching is performed on the bottom of the heat dissipation column to form a first groove.

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