An automatic layout-level leakage detection method for multi-well nested CMOS process

Abstract

The invention discloses an automatic layout-level leakage inspection method for a multi-well nested CMOS process. By analyzing the generation mechanism of inter-well parasitics in the multi-well nested CMOS process, two ports for modeling inter-well parasitic effects are added on the basis of the traditional CMOS BSIM 3V3 simulation four-port model. Meanwhile, the mature EDA design inspection rules are improved. The method can realize automatic troubleshooting of inter-well parasitic effects in the multi-well nested process layout and effectively identify global leakage in the layout. The method is easy to operate, highly automated and highly efficient in evaluation. The method reduces the reflow cycle and cost loss caused by inter-well leakage and improves the evaluation operability and bare chip reliability.

Description

Technical Field

[0001] The invention relates to an automatic leakage inspection method for layout level of multi-well nested CMOS process, belonging to the field of function evaluation in the design process of integrated circuits. Background Art

[0002] The power supply voltage of high-voltage analog devices such as high-voltage analog-to-digital converters, high-voltage operational amplifiers, and high-voltage switches is generally ±10V to ±20V, and the integration scale is in the order of thousands of transistors. Therefore, a CMOS process with multiple process wells is usually used to achieve high-voltage characteristics. However, in the circuit design simulation process, since the device model lacks modeling and simulation of the parasitic conditions of the wells between adjacent devices, the leakage risk caused by parasitic conduction between wells cannot be exposed and prevented through simulation, resulting in multiple tape-out losses, becoming a key difficulty in the design of high-voltage analog devices. For example, during the development of a certain domestically produced high-voltage digital-to-analog device, the initial sample product occasionally leaked electricity; for another example, a certain high-voltage digital-to-analog converter, due to the decrease in the total dose index caused by the high-voltage parasitic conduction, it is difficult to meet the requirements of domestic development.

[0003] The reasons why multi-process well leakage is difficult to detect at the design stage are:

[0004] The multi-well nested process integrated circuit design uses the device model and parameters provided by the process factory. The model is mostly based on the commonly used Bsim3V3 model, which does not include the inter-well parasitic parameter model.

[0005] The multi-well nested process integrated circuit design uses mature EDA tools, and mature EDA tools are usually combined with mature Bsim3V3 models for simulation method settings, so EDA tools cannot simulate parasitic parameters between wells. Summary of the invention

[0006] The technical problem solved by the present invention is: in view of the fact that the mature transistor simulation models and inspection rules in the current prior art cannot meet the leakage detection requirements caused by inter-well parasitics in a multi-well nested process, an automatic leakage inspection method at the layout level for a multi-well nested CMOS process is proposed.

[0007] The present invention solves the above technical problems by the following technical solutions:

[0008] A method for automatic layout-level leakage inspection for multi-well nested CMOS process, the steps are as follows:

[0009] (1) Sort out and analyze the layout process nesting of high-voltage transistors in the multi-well nested CMOS layout circuit under test to obtain typical multi-well nested process characteristics;

[0010] (2) According to the typical multi-well nested process characteristics obtained in step (1), based on the BSIM3V3 four-port model, generate a six-port terminal including inter-well parasitics;

[0011] (3) generating a six-port model of a multi-well nested CMOS transistor based on the device model language identified by the integrated circuit universal design simulation platform and the six-port terminal including inter-well parasitics;

[0012] (4) using the layout design inspection rules required by the integrated circuit design task, inspecting the six-port terminal including the inter-well parasitics, and obtaining the inspection rules for the inter-well parasitics;

[0013] (5) According to the inspection rules for inter-well parasitics and the six-port model of multi-well nested CMOS transistors, the layout file of the multi-well nested CMOS layout circuit under test is simulated to confirm the normal function of the circuit;

[0014] (6) If the simulation confirmation check result shows that the six-port simulation model has an impact on the function of the multi-well nested CMOS layout circuit under test, the six-port model and the inspection rules of the multi-well nested CMOS transistor are adjusted until the simulation confirmation check result shows that the six-port simulation model has no impact on the function of the multi-well nested CMOS layout circuit under test, otherwise the leakage of the layout circuit is continuously checked;

[0015] (7) Use the six-port simulation model and inspection rules to perform global leakage inspection and confirmation on the layout circuit;

[0016] (8) If there is no leakage, the inspection is completed; if there is leakage, find the leakage point and modify the layout circuit. After modification, repeat steps (6) and (7) until there is no leakage in the layout circuit.

[0017] In the step (1), the layout process nesting situation is specifically sorted out as follows:

[0018] The number of nested well layers of high-voltage transistors in the tested multi-well nested CMOS layout circuit, the ground connection conditions of each electrode and substrate, and the ground level differences are analyzed.

[0019] In the step (2), the six-port terminal including the inter-well parasitic is provided with a traditional source, a gate, a drain, and a substrate electrode, and also includes a deep well substrate electrode and a substrate isolation electrode, wherein the multi-level nested wells are used to increase the breakdown barrier, each electrode substrate is used for ground connection, and the ground level of each electrode remains the same;.

[0020] In the step (3), the six-port model of the multi-well nested CMOS transistor includes the ports of the built-in characterization transistor and two newly added ports, and the newly added ports are used to characterize the ground potential of each well substrate in the multi-well structure. The six-port model is established according to the model language and syntax of the original transistor process file of the wafer process factory, wherein:

[0021] The specific steps of the modeling process are:

[0022] Step 1: Complete modeling and terminal addition to initially form a six-port model;

[0023] Step 2: Complete the addition of the calculation formula for the bipolar layout area of ​​the inter-well parasitic diode.

[0024] In the step (4), the inspection rules are used to perform inter-well parasitic leakage inspection of the layout circuit. Based on the six-port model in step (3), the equivalent capacitance of the inter-well parasitic diode is calculated and obtained, and the risk of the parasitic diode being broken down is analyzed according to the potential difference between the ground level of the two newly added ports and the ground level of other substrates, thereby completing the automated global inspection of the layout.

[0025] The advantages of the present invention compared with the prior art are:

[0026] The present invention provides a layout-level leakage automatic inspection method for a multi-well nested CMOS process. By modeling the characteristics of the multi-well nested process of a high-voltage transistor and modifying the inspection rule file, it can ensure a comprehensive and global automatic inspection and identification of inter-well parasitic conditions in the layout design stage, thereby solving the problem that leakage phenomena can only be exposed in the post-tapeline test stage, thereby increasing product development costs and cycles, and fully ensuring the reliability of such process devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A flow chart of the automatic leakage inspection method at the layout level of a multi-well nested CMOS process provided by the invention;

[0028] Figure 2 Schematic diagram of layout-level leakage model of multi-well nested CMOS process provided for the invention;

[0029] Figure 3 A schematic diagram of a six-terminal model modeling file provided for the invention;

[0030] Figure 4 Schematic diagram of the process inspection file of the six-terminal model provided for the invention; DETAILED DESCRIPTION

[0031] An automatic layout-level leakage detection method for multi-well nested CMOS process is used to solve the evaluation problem of inter-well leakage phenomenon that is difficult to find in the design stage. The specific steps are as follows:

[0032] (1) Sort out and analyze the layout process nesting of high-voltage transistors in the multi-well nested CMOS layout circuit under test to obtain typical multi-well nested process characteristics;

[0033] Among them, the layout process nesting situation is sorted out as follows:

[0034] Analyze the number of nested well layers of high-voltage transistors in the multi-well nested CMOS layout circuit under test, the ground connection conditions at each substrate end, and the ground level differences;

[0035] (2) According to the typical multi-well nested process characteristics obtained in step (1), based on the BSIM3V3 four-port model, generate a six-port terminal including inter-well parasitics;

[0036] Among them, the six-port terminal including the inter-well parasitic is provided with the traditional source, gate, drain, substrate, and also includes the deep well substrate and substrate isolation. The newly added multi-level nested well is used to increase the breakdown barrier to achieve high voltage design. The newly added substrates of each pole are used for ground connection, and the ground level of each pole should be kept the same as much as possible;

[0037] (3) generating a six-port model of a multi-well nested CMOS transistor based on the device model language identified by the integrated circuit universal design simulation platform and the six-port terminal including inter-well parasitics;

[0038] Among them, the six-port model of the multi-well nested CMOS transistor has two extra ports for characterizing the ground potential of each well substrate in the multi-well structure, in addition to the original ports for characterizing the transistor terminals. The design and generation of this model should be fully based on the model language and syntax of the original transistor process file of the wafer process factory. The modeling process is divided into two steps: Step 1 completes the modeling and terminal addition to initially form a six-port model; Step 2 completes the addition of the calculation formula for the bipolar layout area of ​​the inter-well parasitic diode;

[0039] (4) using the layout design inspection rules required by the integrated circuit design task, inspecting the six-port terminal including the inter-well parasitics, and obtaining the inspection rules for the inter-well parasitics;

[0040] The inspection rules are used to inspect the inter-well parasitic leakage of the layout circuit, and are confirmed and added by an external design system;

[0041] (5) According to the inspection rules for inter-well parasitics and the six-port model of multi-well nested CMOS transistors, the layout file of the multi-well nested CMOS layout circuit under test is simulated to confirm the normal function of the circuit;

[0042] (6) If the simulation confirmation check result shows that the six-port simulation model has an impact on the function of the multi-well nested CMOS layout circuit under test, the six-port model and the inspection rules of the multi-well nested CMOS transistor are adjusted until the simulation confirmation check result shows that the six-port simulation model has no impact on the function of the multi-well nested CMOS layout circuit under test, otherwise the leakage of the layout circuit is continuously checked;

[0043] (7) Use the six-port simulation model and inspection rules to perform global leakage inspection and confirmation on the layout circuit;

[0044] (8) If there is no leakage, the inspection is completed; if there is leakage, find the leakage point and modify the layout circuit. After modification, repeat steps (6) and (7) until there is no leakage in the layout circuit.

[0045] The following is further described based on specific embodiments:

[0046] In the current embodiment, if Figure 1 As shown, the automatic leakage detection method at the layout level based on the multi-well nested CMOS process is as follows:

[0047] (1) The typical multi-well nesting process characteristics are summarized as follows:

[0048] This design uses the TSMC 0.25CMOS process. After circuit and ground level analysis, it is determined that the typical high-voltage transistor is the nch_5 transistor in the process file;

[0049] (2) combing to form a six-port terminal including inter-well parasitics;

[0050] The original nch_5 transistor has four ports: source, gate, drain, and substrate. By analyzing the process characteristics, a deep well substrate and substrate isolation terminal are added. The process structure diagram is shown in the figure. Figure 2 As shown;

[0051] (3) Forming a six-port model of multi-well nested CMOS transistors;

[0052] Based on the machine language that Cadence Spectre can recognize, the following is formed: Figure 3 The model shown in the figure, in which the original ports are d, g, s, and b, the newly added ports are nbl_iso and sub, the parasitic diodes between the wells are expressed as d1 and d2, and the two-end ports, parasitic capacitance area, and dielectric constant of the two parasitic diodes are described and characterized;

[0053] (4) Forming inspection rules for inter-well parasitics;

[0054] Based on Cadence simulation software and TSMC process inspection rule files, add inter-well parasitic inspection rules, such as Figure 4 As shown;

[0055] (5) Simulate the layout file to confirm that the circuit functions correctly;

[0056] (6) Perform global leakage check and confirmation on the layout file;

[0057] Based on Cadence simulation software, the layout design file is checked for leakage;

[0058] (7) After leakage inspection, 73 potential leakage points in the layout were eliminated. By adding ground holes to the problematic layout and other modifications, the automatic inspection did not find leakage problems. After wafer verification, the device did not have leakage during the test phase, greatly improving the design simulation accuracy and capabilities.

[0059] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0060] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A method for automatic layout-level leakage inspection for multi-well nested CMOS process, characterized in that Here are the steps: (1) Sort out and analyze the layout process nesting of high-voltage transistors in the multi-well nested CMOS layout circuit under test to obtain typical multi-well nested process characteristics; (2) Based on the typical multi-well nested process characteristics obtained in step (1), a six-port terminal including inter-well parasitics is generated based on the BSIM3V3 four-port model; (3) Generate a six-port model of a multi-well nested CMOS transistor based on the device model language identified by the integrated circuit universal design simulation platform and the six-port terminal including inter-well parasitics; (4) Using the layout design inspection rules required for the integrated circuit design task, the six-port terminal including the inter-well parasitics is inspected to obtain the inspection rules for the inter-well parasitics; (5) Based on the inspection rules for inter-well parasitics and the six-port model of multi-well nested CMOS transistors, the layout file of the multi-well nested CMOS layout circuit under test is simulated to confirm the normal function of the circuit; (6) If the simulation confirmation check result shows that the six-port simulation model has an impact on the function of the multi-well nested CMOS layout circuit under test, the six-port model and inspection rules of the multi-well nested CMOS transistor are adjusted until the simulation confirmation check result shows that the six-port simulation model has no impact on the function of the multi-well nested CMOS layout circuit under test, otherwise continue to check the leakage of the layout circuit; (7) Use the six-port simulation model and inspection rules to perform global leakage inspection and confirmation on the layout circuit; (8) If there is no leakage, the inspection is completed; if there is leakage, find the leakage point and modify the layout circuit. After modification, repeat steps (6) and (7) until there is no leakage in the layout circuit; In step (3), the six-port model of the multi-well nested CMOS transistor includes the ports of the built-in characterization transistor and two newly added ports, and the newly added ports are used to characterize the ground potential of each well substrate in the multi-well structure. The six-port model is established according to the model language and syntax of the original transistor process file of the wafer fabrication process factory, wherein: The specific steps of the modeling process are: Step 1: Complete modeling and terminal addition to initially form a six-port model; Step 2: Complete the addition of the calculation formula for the bipolar layout area of ​​the inter-well parasitic diode; In the step (4), the inspection rule is used to perform inter-well parasitic leakage inspection of the layout circuit. Based on the six-port model in step (3), the equivalent capacitance of the inter-well parasitic diode is calculated and obtained, and the risk of the parasitic diode being broken down is analyzed according to the potential difference between the ground level of the two newly added ports and the ground level of other substrates, thereby completing the automated global layout inspection.

2. The method for automatic layout-level leakage inspection for multi-well nested CMOS process according to claim 1, characterized in that: In step (1), the layout process nesting situation is specifically sorted out as follows: The number of nested well layers of high-voltage transistors in the tested multi-well nested CMOS layout circuit, the ground connection conditions of each electrode and substrate, and the ground level differences are analyzed.

3. The method for automatic layout-level leakage inspection for multi-well nested CMOS process according to claim 2, characterized in that: In the step (2), the six-port terminal including the inter-well parasitic is provided with a traditional source, a gate, a drain, and a substrate electrode, and also includes a deep well substrate electrode and a substrate isolation electrode, wherein the multi-level nested wells are used to increase the breakdown barrier, and each electrode substrate is used for ground connection, and the ground level of each electrode remains the same.

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