Neuromorphic computing evaluation device

Abstract

The embodiment of the present invention discloses a neuromorphic computing evaluation device, which includes a memristor array evaluation circuit and a memristor array, wherein the memristor array evaluation circuit includes a main controller, a signal application subcircuit, a write weight subcircuit, a read weight subcircuit and a switch matrix; the switch matrix is ​​respectively connected to the main controller and the memristor array, and the main controller is also respectively connected to the switch matrix through the write weight subcircuit, the signal application subcircuit and the read weight subcircuit. The neuromorphic computing evaluation device can accurately control and read the resistance of each memristor in the memristor array. The accurate modulation of the resistance of the memristor array is achieved, and the accuracy of neuromorphic computing is improved, so that the neuromorphic computing evaluation device of the present application can be applied to the testing, training and neuromorphic computing of more types of memristor arrays.

Description

Technical Field

[0001] The present invention relates to the field of neuromorphic computing, and in particular to a neuromorphic computing evaluation device. Background Art

[0002] Memristor, also known as memory resistor, is a synaptic device that realizes neuromorphic computing. It has excellent characteristics such as non-volatility, small size and low energy consumption. In brain-like neuromorphic computing such as neuromorphic computing and in-memory computing, the performance of synapses such as memristors will affect the accuracy of neuromorphic computing. It is necessary to read the resistance of the memristor quickly and accurately, and adjust the resistance of the memristor according to the neural system function to be realized.

[0003] At present, when verifying whether the performance of a memristor is reliable, a high voltage is usually applied to the memristor. The voltage value of the voltage divider resistor connected to the memristor is measured, and the resistance value of the memristor is calculated based on Ohm's law. The dynamic weight of the synapse is effectively simulated by the change in the resistance value of the memristor. However, the resistance value of the memristor changes according to the amount of current passing through the memristor, and the memristor can retain the changed resistance value after the circuit is powered off. Applying a high voltage can easily cause the resistance value of the memristor to change, making it impossible to accurately read the resistance value of the memristor and adjust the resistance value of the memristor. Summary of the invention

[0004] In view of the defects of the prior art, the embodiment of the present application aims to provide a neuromorphic computing evaluation device to solve the problem of being unable to accurately test and adjust the memristor.

[0005] In a first aspect, an embodiment of the present application provides a neuromorphic computing evaluation device, including a memristor array evaluation circuit and a memristor array, wherein the memristor array evaluation circuit includes a main controller, a signal application subcircuit, a write weight subcircuit, a read weight subcircuit and a switch matrix;

[0006] The switch matrix is ​​connected to the main controller and the memristor array respectively, and the main controller is also connected to the switch matrix through the write weight subcircuit, the signal application subcircuit, and the read weight subcircuit respectively;

[0007] The signal applying subcircuit is used to receive the pulse signal input by the main controller and apply the pulse signal to the memristor array;

[0008] The write weight subcircuit is used to adjust the resistance of each memristor in the memristor array;

[0009] The read weight subcircuit is used to convert the resistance of the memristor into a voltage signal to cooperate with the main controller to measure the voltage and calculate the resistance of the memristor;

[0010] The switch matrix is ​​used to control the connection and disconnection between each memristor in the memristor array and the write weight subcircuit, the signal application subcircuit and the read weight subcircuit according to the control instruction input by the main controller.

[0011] In combination with the first aspect, in a first possible implementation manner, the write weight subcircuit includes a first digital-to-analog converter, a first filter, and a first buffer;

[0012] The main controller is connected to the memristor array via the first digital-to-analog converter, the first filter, the first buffer and the switch matrix in sequence;

[0013] The first digital-to-analog converter is used to generate a pulse signal written into the memristor according to the pulse information input by the main controller, so as to adjust the resistance value of the memristor.

[0014] In combination with the first aspect, in a second possible implementation manner, the weight reading subcircuit includes an amplifier circuit, a single-ended to differential subcircuit, and an analog-to-digital converter;

[0015] The memristor array is connected to a main controller via the switch matrix, the amplifier circuit, the single-ended differential subcircuit and the analog-to-digital converter in sequence, and the amplifier circuit is connected to the main controller;

[0016] The analog-to-digital converter is used to generate a resistance value measurement signal of the memristor according to the response signal generated by the memristor array.

[0017] In combination with the second possible implementation manner of the first aspect, in three possible implementation manners, the amplifying circuit includes an amplifier and a preset number of resistors;

[0018] One end of each resistor is connected to the input end of the amplifier, and the other end of each resistor is connected to the output end of the amplifier, wherein the resistance value of each resistor is different.

[0019] In combination with the first aspect, in a fourth possible implementation manner, the write weight subcircuit includes a first write weight subcircuit and a second write weight subcircuit, the read weight subcircuit includes a first read weight subcircuit and a second read weight subcircuit, the switch matrix includes a row switch matrix and a column switch matrix, and the first read weight subcircuit and the second read weight subcircuit constitute a response signal measurement circuit;

[0020] The main controller is connected to the column switch matrix through the first write weight subcircuit and the first read weight subcircuit respectively, and the main controller is also connected to the row switch matrix through the second write weight subcircuit and the second read weight subcircuit respectively;

[0021] The row switch matrix is ​​used to apply the pulse signal input by the first write weight subcircuit to the preset row line of the memristor array, or to apply the response signal of the preset row line of the memristor array to the first read weight subcircuit;

[0022] The column switch matrix is ​​used to apply the pulse signal input by the second write weight subcircuit to the preset column line of the memristor array, or to apply the response signal of the preset column line of the memristor array to the second read weight subcircuit.

[0023] In combination with the fourth possible implementation of the first aspect, in five possible implementations, the signal application subcircuit is connected to the memristor array through the row switch matrix, and the signal application subcircuit is also used to modulate the analog pulse signal that drives the memristor array into an analog pulse signal with a preset amplitude and a preset pulse width.

[0024] In combination with the first aspect, in a sixth possible implementation manner, the signal applying subcircuit includes a second digital-to-analog converter, a second filter, and a second buffer;

[0025] The main controller is connected to the memristor array via the second digital-to-analog converter, the second filter, the second buffer and the switch matrix in sequence;

[0026] The second digital-to-analog converter is used to generate an analog pulse signal for driving the memristor array according to the excitation pulse signal input by the main controller.

[0027] In combination with the first aspect, in a seventh possible implementation manner, the neuromorphic computing evaluation device further includes a clock circuit, and the clock circuit is connected to both the write weight subcircuit and the read weight subcircuit;

[0028] The clock circuit is used to generate a clock driving signal for the write weight subcircuit or the read weight subcircuit.

[0029] In combination with the first aspect, in an eighth possible implementation manner, the main controller further includes a universal serial bus interface, and the main controller is connected to an external terminal through the serial bus interface.

[0030] In combination with the first aspect, in a ninth possible implementation manner, the neuromorphic computing evaluation device further includes a power supply module for supplying power to the neuromorphic computing evaluation device.

[0031] The present application provides a neuromorphic computing evaluation device, including a memristor array evaluation circuit and a memristor array, wherein the memristor array evaluation circuit includes a main controller, a signal application subcircuit, a write weight subcircuit, a read weight subcircuit and a switch matrix; the switch matrix is ​​respectively connected to the main controller and the memristor array, and the main controller is also respectively connected to the switch matrix through the write weight subcircuit, the signal application subcircuit and the read weight subcircuit. The neuromorphic computing evaluation device can accurately control and read the resistance of each memristor in the memristor array. The accurate modulation of the resistance of the memristor array is achieved, and the accuracy of neuromorphic computing is improved, so that the neuromorphic computing evaluation device of the present application can be applied to more types of memristor array testing, training and neuromorphic computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope of protection of the present invention. In each of the drawings, similar components are numbered similarly.

[0033] Figure 1 A schematic diagram of the structure of a neuromorphic computing evaluation device provided in an embodiment of the present application is shown;

[0034] Figure 2 Another structural schematic diagram of the neuromorphic computing evaluation device provided in an embodiment of the present application is shown;

[0035] Figure 3 A schematic diagram of the structure of the switch matrix provided in an embodiment of the present application is shown;

[0036] Figure 4 A schematic diagram of the structure of a write weight subcircuit provided in an embodiment of the present application is shown;

[0037] Figure 5 A schematic diagram of the structure of a weight reading subcircuit provided in an embodiment of the present application is shown;

[0038] Figure 6 A partial structural schematic diagram of an amplifier circuit provided in an embodiment of the present application is shown;

[0039] Figure 7 A schematic diagram of the structure of a response signal measurement circuit provided in an embodiment of the present application is shown.

[0040] Description of main component symbols:

[0041] 100-memristor array evaluation circuit, 200-memristor array; 110-main controller, 120-signal application subcircuit, 130-write weight subcircuit, 140-read weight subcircuit, 150-switch matrix, 160-serial bus interface; 131-first write weight subcircuit, 132-second write weight subcircuit; 141-first read weight subcircuit, 142-second read weight subcircuit, 143-response signal measurement circuit; 151-column switch matrix, 152-row switch matrix; 1301-first digital-to-analog converter, 1302-first filter, 1303-first buffer; 1401-amplifier circuit, 1402-single-ended to differential subcircuit, 1403-analog-to-digital converter; R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, Q1-transistor. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0043] The components of the embodiments of the present invention generally described and shown in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0044] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0045] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0046] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present invention belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present invention.

[0047] See also Figure 1 , Figure 1 The structure of the neuromorphic computing evaluation device provided in the embodiment of the present application is shown. In this embodiment, the neuromorphic computing evaluation device includes a memristor array evaluation circuit 100 and a memristor array 200, wherein the memristor array evaluation circuit 100 includes a main controller 110, a signal application subcircuit 120, a write weight subcircuit 130, a read weight subcircuit 140 and a switch matrix 150;

[0048] The switch matrix 150 is connected to the main controller 110 and the memristor array 200 respectively, and the main controller 110 is also connected to the switch matrix 150 through the write weight subcircuit 130, the signal application subcircuit 120, and the read weight subcircuit 140 respectively;

[0049] The signal applying subcircuit 120 is used to receive the pulse signal input by the main controller 110 and apply the pulse signal to the memristor array 200;

[0050] The write weight subcircuit 130 is used to adjust the resistance of each memristor in the memristor array 200;

[0051] The read weight subcircuit 140 is used to convert the resistance of the memristor into a voltage signal to cooperate with the main controller 110 to perform voltage measurement and resistance calculation of the memristor;

[0052] The switch matrix 150 is used to control the connection and disconnection between each memristor in the memristor array 200 and the write weight subcircuit 130 , the signal application subcircuit 120 and the read weight subcircuit 140 according to the control instruction input by the main controller 110 .

[0053] It should be understood that the memristor array 200 can be set according to actual needs and is not limited here. To facilitate understanding of the present application, in this embodiment, a 32*32 memristor array 200 is used, that is, a synaptic array is composed of 32 rows of memristors and 32 columns of memristors. The main controller 110 uses an FPGA (Field Programmable Gate Array) chip, and the main controller 110 is used to control the switch matrix 150 and configure the memristor array evaluation circuit 100, such as initializing and configuring the signal application subcircuit 120, the write weight subcircuit 130, the read weight subcircuit 140 and the switch matrix 150.

[0054] The write weight subcircuit 130 is used to generate various forms of programming pulse trains such as positive pulses, negative pulses, and positive and negative pulses with adjustable amplitude, bandwidth, and frequency, and input the pulses to the memristor array 200 to adjust the amplitude range of the signal of the memristor, so as to achieve accurate adjustment of the resistance value of the memristor. The read weight subcircuit 140 is used to obtain the voltage value of the voltage divider resistor of the memristor, and accurately calculate the actual resistance value of the memristor based on Ohm's law, so as to determine the characteristic parameters of the memristor after training.

[0055] The switch matrix 150 can be implemented by using an analog switch matrix 150 with low on-resistance and low channel coupling to provide an address gating function and realize the switching between the resistance adjustment mode and the resistance value estimation mode of the memristor array 200. At the same time, the switch matrix 150 uses 32 independent parallel multiplexers corresponding to the memristor array 200 to achieve a larger on-signal amplitude and bandwidth.

[0056] In addition, the switch matrix 150 corresponds to the row and column settings of the memristor array 200, and a variety of different operations can be implemented through the switch matrix 150. For example, when the main controller 110 controls the read weight subcircuit 140 and the switch matrix 150, the resistance value of a memristor in the memristor array 200 can be read according to the specified value, the resistance value of each memristor in the memristor array 200 can be read in sequence, and the resistance value of a single memristor can be read continuously. Similarly, when the main controller 110 controls the write weight subcircuit 130 and the switch matrix 150, a pulse signal can be generated according to a user-defined pulse style, which will not be described in detail here. Based on high-precision memristor resistance reading and writing, any memristor in the memristor array 200 can be specified by the main controller 110, and the resistance value can be adjusted according to the set target resistance value, fault tolerance range and pulse parameters.

[0057] Table 1

[0058]

[0059]

[0060] Please refer to Table 1, which shows a performance index comparison between the neuromorphic computing evaluation device and the existing verification device. For example, the higher the pulse signal amplitude resolution, the more accurately the resistance of the memristor can be adjusted. Through the neuromorphic computing evaluation device provided by the present application, it is possible to adjust the resistance value of each memristor in the memristor array 200 and read the resistance value. Accurate modulation of the resistance value of the memristor array 200 is achieved, and the accuracy of neuromorphic computing is improved, so that the neuromorphic computing evaluation device of the present application can be applied to more types of memristor array 200 testing, training and neuromorphic computing.

[0061] Please also read Figure 2 , Figure 2 Another structural schematic diagram of the neuromorphic computing evaluation device provided in an embodiment of the present application is shown. In this embodiment, the write weight subcircuit 130 includes a first write weight subcircuit 131 and a second write weight subcircuit 132, the read weight subcircuit 140 includes a first read weight subcircuit 141 and a second read weight subcircuit 142, and the switch matrix 150 includes a row switch matrix 152 and a column switch matrix 151;

[0062] The main controller 110 is connected to the column switch matrix 151 through the first write weight subcircuit 131 and the first read weight subcircuit 141 respectively, and the main controller 110 is also connected to the row switch matrix 152 through the second write weight subcircuit 132 and the second read weight subcircuit 142 respectively;

[0063] The row switch matrix 152 is used to apply the pulse signal input by the first write weight subcircuit 131 to the preset row line of the memristor array 200, or apply the response signal of the preset row line of the memristor array 200 to the first read weight subcircuit 141;

[0064] The column switch matrix 151 is used to apply the pulse signal input by the second write weight subcircuit 132 to the preset column line of the memristor array 200, or apply the response signal of the preset column line of the memristor array 200 to the second read weight subcircuit 142.

[0065] Please also read Figure 3 , Figure 3The schematic diagram of the structure of the switch matrix provided by the embodiment of the present application is shown. Taking the column switch matrix 151 as an example, a 32:1MUX (32:1 multiplexers, 32 to 1 multiplexer) and 32 4:1MUX (4:1 multiplexers, 4 to 1 multiplexer) are set corresponding to 32 columns of memristors, wherein the 4:1MUX includes a write signal switch, a read signal switch, a floating switch and a ground switch. Similarly, the row switch matrix 152 adopts the same structure as the column switch matrix 151, which will not be described in detail here.

[0066] For example, when the first row of the memristor array 200 is selected for writing signals, the 4:1 MUX corresponding to the memristors in the first row is connected to the write signal switch, the 4:1 MUX corresponding to the memristors outside the first row is connected to the floating switch, and the memristors in the first row are connected to the second write weight subcircuit 132. Similarly, when the first column of the memristor array 200 is selected for reading signals, the 4:1 MUX corresponding to the memristors in the first column is connected to the read signal switch, the 4:1 MUX corresponding to the memristors outside the first column is connected to the ground switch, and the memristors in the first column are connected to the first read weight subcircuit 141. When performing neuromorphic computing based on the neuromorphic computing evaluation device, all 4:1 MUXs in the column switch matrix 151 are connected to the write signal switch, and all 4:1 MUXs in the row switch matrix 152 are connected to the read signal switch.

[0067] In an optional example, the signal application subcircuit 120 is connected to the memristor array 200 through the row switch matrix 152, and the signal application subcircuit 120 is also used to modulate the analog pulse signal driving the memristor array 200 into an analog pulse signal with a preset amplitude and a preset pulse width.

[0068] The write signal switch of the row switch matrix 152 is turned on, and the signal application subcircuit 120 adjusts the received excitation pulse signal to an analog pulse signal that can drive the resistance value of the memristor array 200 to change, and adjusts the pulse signal amplitude and bias, and applies the pulse signal to the memristor array 200 in parallel through the row switch matrix 152. Please refer to Figure 4 , Figure 4 The schematic diagram of the structure of the write weight subcircuit provided in the embodiment of the present application is shown. In this embodiment, the write weight subcircuit 130 includes a first digital-to-analog converter 1301, a first filter 1302 and a first buffer 1303;

[0069] The main controller 110 is connected to the memristor array 200 through the first digital-to-analog converter 1301, the first filter 1302, the first buffer 1303 and the switch matrix 150 in sequence;

[0070] The first digital-to-analog converter 1301 is used to generate a pulse signal to be written into the memristor according to the pulse information input by the main controller 110, so as to adjust the resistance value of the memristor.

[0071] The first digital-to-analog converter 1301 is used to provide a conversion rate of 1GSps (Gigabit Samples Per Second) and a conversion accuracy of 16bit (binary digit). According to the digital signal input by the main controller 110, it generates a programming pulse train in various forms such as positive pulses, negative pulses, and positive and negative pulses with adjustable amplitude, bandwidth and frequency, so as to achieve accurate adjustment of the resistance value of the memristor array 200. The first filter 1302 is used to suppress the noise output by the first digital-to-analog converter 1301 to ensure the maximum dynamic range within the effective signal frequency range. The first buffer 1303 is a unit gain amplifier circuit 1401 with high input resistance and low output resistance, which is used to suppress the load effect and provide a current signal that can be output to the memristor array 200.

[0072] See also Figure 5 , Figure 5 The structural diagram of the read weight subcircuit provided in the embodiment of the present application is shown. In this embodiment, the read weight subcircuit 140 includes an amplifier circuit 1401, a single-ended to differential subcircuit 1402 and an analog-to-digital converter 1403;

[0073] The memristor array 200 is connected to the main controller 110 through the switch matrix 150, the amplifier circuit 1401, the single-ended differential subcircuit 1402 and the analog-to-digital converter 1403 in sequence, and the amplifier circuit 1401 is connected to the main controller 110;

[0074] The analog-to-digital converter 1403 is used to generate a resistance value measurement signal of the memristor according to the response signal generated by the memristor array 200 .

[0075] The analog-to-digital converter 1403 is used to provide a conversion rate of 65MSps (Million Samples per Second) and a conversion accuracy of 14bit, and converts the pulse signal read from the memristor array 200 into a digital signal to infer the actual resistance value of the memristor. The single-ended to differential subcircuit 1402 is used to convert the single-ended signal into a differential signal to determine the logical state of the memristor array 200 by the voltage difference of the differential signal. The devices included in the single-ended to differential subcircuit 1402 are set according to actual needs and are not limited here.

[0076] Please also read Figure 6 , Figure 6A partial structural schematic diagram of an amplifier circuit provided in an embodiment of the present application is shown. In an optional example, the amplifier circuit 1401 includes an amplifier Q1 and a preset number of resistors R;

[0077] One end of each resistor R is connected to the input end of the amplifier Q1 , and the other end of each resistor R is connected to the output end of the amplifier Q1 , wherein the resistance value of each resistor R is different.

[0078] To facilitate understanding of this application, Figure 6 In the embodiment, the amplifier circuit 1401 is directly connected to the memristor array 200 and the analog-to-digital converter 1403. The amplifier circuit 1401 uses a transistor amplifier circuit 1401 to amplify the voltage of the memristor through the transistor Q1 to obtain a signal that can be recognized by the main controller 110. Since the voltage value of the transistor Q1 cannot be directly obtained, the weight reading subcircuit 140 needs to read the voltage value of the voltage divider resistor and use Ohm's law to calculate the resistance value of the memristor to be tested. In addition, the memristor that may have a fault in the memristor array 200 can also be detected and calibrated by strategies such as sequentially reading the resistance value of each memristor in the memristor array 200.

[0079] Specifically, in neuromorphic computing, the resistance value of the memristor effectively simulates the synaptic weight. Assume that the memristor array 200 includes three synapse types, and the weight distribution range of one synapse type is 500 ohms to 50K ohms, the weight distribution range of another synapse type is 50K ohms to 300K ohms, and the weight distribution range of another synapse type is 100K ohms to 10M ohms. When calculating the actual resistance value of the memristor, the resistance measurement range of the memristor is distributed between 500 ohms and 50K ohms, and the dynamic range of the weight is too high. The single voltage divider resistor cannot accurately calculate the resistance value of the memristor.

[0080] In this embodiment, the amplifier circuit 1401 is provided with a first resistor R1 of 1k ohm, a second resistor R2 of 10k ohm, a third resistor R3 of 100k ohm, a fourth resistor R4 of 1M ohm, and a fifth resistor R5 of 10M ohm. When the resistance value of the memristor is in the range of 500 ohms to 50k ohms, the first resistor R1 is connected and the voltage of the first resistor R1 is obtained; when the resistance value of the memristor is in the range of 5k ohms to 50k ohms, the second resistor R2 is connected and the voltage of the first resistor R1 is obtained. By selecting to connect different resistors, the measurement of the resistance value of the memristor in a wide range of 500 ohms to 50K ohms is achieved, and the neuromorphic computing evaluation device can be applicable to the testing of various types of memristor arrays 200.

[0081] Please also read Figure 7 , Figure 7The schematic diagram of the structure of the response signal measurement circuit provided by the embodiment of the present application is shown. The first read weight value subcircuit 141 and the second read weight value subcircuit 142 adopt the same structural design to form a response signal measurement circuit 143. The response signal measurement circuit 143 sends the digital signal output by the memristor array 200 to the main controller 110 to complete the signal analysis and judgment. At the same time, the response signal measurement circuit 143 effectively reduces the complexity and power consumption of the circuit by using time-division multiplexing.

[0082] In this embodiment, the signal applying subcircuit 120 includes a second digital-to-analog converter, a second filter and a second buffer;

[0083] The main controller 110 is connected to the memristor array 200 through the second digital-to-analog converter, the second filter, the second buffer and the switch matrix 150 in sequence;

[0084] The second digital-to-analog converter is used to generate an analog pulse signal for driving the memristor array 200 according to the excitation pulse signal input by the main controller 110 .

[0085] The main controller is also used to receive the excitation pulse signal sent by the external host computer, and transmit the excitation pulse signal to the signal application subcircuit 120. The signal application subcircuit 120 adjusts the excitation pulse signal to an analog pulse signal capable of driving the memristor array 200 to change the required value.

[0086] It should be understood that the signal application subcircuit 120 can use the same device as the read weight circuit to input the pulse signal to the memristor array 200 in parallel and synchronously. The structure of the signal application subcircuit 120 is not specifically shown in the figure.

[0087] In this embodiment, the neuromorphic computing evaluation device further includes a clock circuit, and the clock circuit is connected to both the write weight subcircuit 130 and the read weight subcircuit 140;

[0088] The clock circuit is used to generate a clock driving signal for the write weight subcircuit 130 or the read weight subcircuit 140 .

[0089] The clock circuit is connected to both the write weight subcircuit 130 and the read weight subcircuit 140, which is not specifically shown in the figure. The clock circuit is used to generate clock drive signals for the write weight subcircuit 130 and the read weight subcircuit 140 to ensure that the write weight subcircuit 130 and the read weight subcircuit 140 operate synchronously during the neuromorphic computing process.

[0090] In this embodiment, the main controller 110 further includes a universal serial bus interface 160 , and the main controller 110 is connected to an external terminal via the universal serial bus interface 160 .

[0091] The main controller 110 is connected to an external terminal via a serial bus interface 160 to perform data and command interaction, so as to control the switch matrix 150 and configure the memristor array evaluation circuit 100 through the main controller 110 .

[0092] In this embodiment, the neuromorphic computing evaluation device further includes a power supply module for supplying power to the neuromorphic computing evaluation device.

[0093] The power module is used to power the main controller 110, the write weight subcircuit 130, the read weight subcircuit 140, and the signal application subcircuit 120, which is not specifically shown in the figure. It should be understood that the power module needs to provide different voltages, such as providing a 1.2V voltage to the main controller 110 and a 0.2V voltage to the read weight subcircuit 140, so as to avoid the resistance value of the memristor changing due to excessively high voltage when measuring the resistance value of the memristor.

[0094] The present application provides a neuromorphic computing evaluation device, including a memristor array evaluation circuit and a memristor array, wherein the memristor array evaluation circuit includes a main controller, a signal application subcircuit, a write weight subcircuit, a read weight subcircuit and a switch matrix; the switch matrix is ​​respectively connected to the main controller and the memristor array, and the main controller is also respectively connected to the switch matrix through the write weight subcircuit, the signal application subcircuit and the read weight subcircuit. The neuromorphic computing evaluation device can accurately control and read the resistance of each memristor in the memristor array. The accurate modulation of the resistance of the memristor array is achieved, and the accuracy of neuromorphic computing is improved, so that the neuromorphic computing evaluation device of the present application can be applied to more types of memristor array testing, training and neuromorphic computing.

[0095] An embodiment of the present application also provides a terminal device, including the neuromorphic computing evaluation device as in this embodiment.

[0096] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram or flowchart, and the combination of boxes in the structure diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0097] In addition, the functional modules or units in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0098] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0099] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A neuromorphic computing evaluation device, characterized in that: It includes a memristor array evaluation circuit and a memristor array, wherein the memristor array evaluation circuit includes a main controller, a signal application subcircuit, a write weight subcircuit, a read weight subcircuit and a switch matrix; The switch matrix is ​​connected to the main controller and the memristor array respectively, and the main controller is also connected to the switch matrix through the write weight subcircuit, the signal application subcircuit, and the read weight subcircuit respectively; The signal applying subcircuit is used to receive the pulse signal input by the main controller and apply the pulse signal to the memristor array; The write weight subcircuit is used to adjust the resistance of each memristor in the memristor array; The read weight subcircuit is used to convert the resistance of the memristor into a voltage signal to cooperate with the main controller to measure the voltage and calculate the resistance of the memristor; The switch matrix is ​​used to control the connection and disconnection between each memristor in the memristor array and the write weight subcircuit, the signal application subcircuit and the read weight subcircuit according to the control instruction input by the main controller.

2. The neuromorphic computing evaluation device according to claim 1, characterized in that: The write weight subcircuit includes a first digital-to-analog converter, a first filter and a first buffer; The main controller is connected to the memristor array via the first digital-to-analog converter, the first filter, the first buffer and the switch matrix in sequence; The first digital-to-analog converter is used to generate a pulse signal written into the memristor according to the pulse information input by the main controller, so as to adjust the resistance value of the memristor.

3. The neuromorphic computing evaluation device according to claim 1, characterized in that: The weight reading subcircuit includes an amplifier circuit, a single-ended to differential subcircuit and an analog-to-digital converter; The memristor array is connected to a main controller via the switch matrix, the amplifier circuit, the single-ended differential subcircuit and the analog-to-digital converter in sequence, and the amplifier circuit is connected to the main controller; The analog-to-digital converter is used to generate a resistance value measurement signal of the memristor according to the response signal generated by the memristor array.

4. The neuromorphic computing evaluation device according to claim 3, characterized in that: The amplifying circuit includes an amplifier and a preset number of resistors; One end of each resistor is connected to the input end of the amplifier, and the other end of each resistor is connected to the output end of the amplifier, wherein the resistance value of each resistor is different.

5. The neuromorphic computing evaluation device according to claim 1, characterized in that: The write weight subcircuit includes a first write weight subcircuit and a second write weight subcircuit, the read weight subcircuit includes a first read weight subcircuit and a second read weight subcircuit, the switch matrix includes a row switch matrix and a column switch matrix, and the first read weight subcircuit and the second read weight subcircuit constitute a response signal measurement circuit; The main controller is connected to the column switch matrix through the first write weight subcircuit and the first read weight subcircuit respectively, and the main controller is also connected to the row switch matrix through the second write weight subcircuit and the second read weight subcircuit respectively; The row switch matrix is ​​used to apply the pulse signal input by the first write weight subcircuit to the preset row line of the memristor array, or to apply the response signal of the preset row line of the memristor array to the first read weight subcircuit; The column switch matrix is ​​used to apply the pulse signal input by the second write weight subcircuit to the preset column line of the memristor array, or to apply the response signal of the preset column line of the memristor array to the second read weight subcircuit.

6. The neuromorphic computing evaluation device according to claim 5, characterized in that: The signal application subcircuit is connected to the memristor array via the row switch matrix, and the signal application subcircuit is also used to modulate the analog pulse signal driving the memristor array into an analog pulse signal with a preset amplitude and a preset pulse width.

7. The neuromorphic computing evaluation device according to claim 1, characterized in that: The signal applying subcircuit includes a second digital-to-analog converter, a second filter and a second buffer; The main controller is connected to the memristor array via the second digital-to-analog converter, the second filter, the second buffer and the switch matrix in sequence; The second digital-to-analog converter is used to generate an analog pulse signal for driving the memristor array according to the excitation pulse signal input by the main controller.

8. The neuromorphic computing evaluation device according to claim 1, characterized in that: The neuromorphic computing evaluation device further includes a clock circuit, and the clock circuit is connected to both the write weight subcircuit and the read weight subcircuit; The clock circuit is used to generate a clock driving signal for the write weight subcircuit or the read weight subcircuit.

9. The neuromorphic computing evaluation device according to claim 1, characterized in that: The main controller also includes a universal serial bus interface, and the main controller is connected to an external terminal through the serial bus interface.

10. The neuromorphic computing evaluation device according to claim 1, characterized in that: The neuromorphic computing evaluation device also includes a power supply module for supplying power to the neuromorphic computing evaluation device.

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