Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a core layer on the substrate; performing ion doping on the core layer of the sacrificial area, suitable for making the core layer of the sacrificial area and the core layer of the anti-etching area have different etching rates, the core layer doped with ions is used as a sacrificial layer, and the core layer not doped with ions is used as an anti-etching layer; forming a groove penetrating the core layer located between adjacent sacrificial areas; forming a sidewall on the sidewall of the groove, the sidewall located on the sidewall of the groove enclosing a first groove; using an etching process to remove the sacrificial layer to form a second groove penetrating the anti-etching layer, the etching process etching rate of the sacrificial layer is greater than the etching rate of the anti-etching layer; using the anti-etching layer and the sidewall as a mask, etching the target layer at the bottom of the first groove and the second groove to form a target pattern. The embodiment of the present invention is conducive to improving the graphic accuracy of the target pattern and the matching degree between the target pattern and the design pattern.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of internal connection structures of each chip) gradually increases, the geometric size (i.e. the minimum component size that can be produced using the process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to improve the matching degree between the target pattern formed on the wafer and the designed pattern has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the graphic accuracy of a target graphic and the matching degree between the target graphic and the design graphic.

[0006] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer on the substrate, wherein the core layer includes an anti-etching region for forming an anti-etching layer and a sacrificial region for forming a sacrificial layer; ion doping the core layer in the sacrificial region is suitable for making the core layer in the sacrificial region and the core layer in the anti-etching region have different etching rates, the core layer doped with ions in the sacrificial region is used as the sacrificial layer, and the core layer not doped with ions in the anti-etching region is used as the anti-etching layer; forming a core layer that penetrates adjacent regions. A groove of the core layer between the sacrificial areas, the sidewalls of the groove expose the core layer located in the sacrificial area; a sidewall is formed on the sidewall of the groove, and the sidewalls located on the sidewalls of the groove surround a first groove; after ion doping and forming the first groove, an etching process is used to remove the sacrificial layer, and a second groove penetrating the anti-etching layer is formed in the anti-etching layer; wherein the etching rate of the sacrificial layer by the etching process is greater than the etching rate of the anti-etching layer; using the anti-etching layer and the sidewall as a mask, the target layer at the bottom of the first groove and the second groove is etched to form a target pattern.

[0007] Optionally, after forming the core layer and before forming the groove, the core layer of the sacrificial area is ion doped; or, after forming the groove and before forming the side wall, the core layer of the sacrificial area is ion doped; or, after forming the side wall and before forming the second groove, the core layer of the sacrificial area is ion doped.

[0008] Optionally, the ions used for ion doping the core layer of the sacrificial region include boron ions, phosphorus ions, arsenic ions or argon ions.

[0009] Optionally, in the step of performing ion doping on the core layer of the sacrificial region, the ion doping concentration in the core layer of the sacrificial region is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

[0010] Optionally, an ion implantation process is used to perform ion doping on the core layer of the sacrificial region.

[0011] Optionally, the parameters of the ion implantation process include: an implantation energy of 1 KeV to 100 KeV, and an angle between an implantation direction and a normal to a substrate surface of 0° to 5°.

[0012] Optionally, a wet etching process is used to remove the sacrificial layer.

[0013] Optionally, the etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid.

[0014] Optionally, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molecular ratio between the nitric acid and the hydrofluoric acid is at least 2, and the molar percentage of the nitric acid is at least 14%.

[0015] Optionally, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molar percentage of hydrofluoric acid is 0.2% to 6%, the molar percentage of nitric acid is 14% to 28%, and the molar percentage of acetic acid is 66% to 86%.

[0016] Optionally, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the volume ratio of hydrofluoric acid to acetic acid is 1:8 to 1:100, and the volume ratio of hydrofluoric acid to nitric acid is 1:3 to 1:50.

[0017] Optionally, in the step of forming the core layer, the material of the core layer includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride or silicon carbon nitride.

[0018] Optionally, the step of performing ion doping on the core layer of the sacrificial area includes: forming a shielding layer covering the anti-etching area, the shielding layer exposing the sacrificial area; and performing ion doping on the core layer using the shielding layer as a mask.

[0019] Optionally, the target layer is a dielectric layer; using the anti-etching layer and the side wall as a mask, the dielectric layer at the bottom of the first groove and the second groove is etched to form an interconnection groove; the method for forming the semiconductor structure also includes: after forming the interconnection groove, forming a metal wire in the interconnection groove.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] In the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on the core layer of the sacrificial area, which is suitable for making the core layer of the sacrificial area and the core layer of the anti-etching area have different etching rates, so that a sacrificial layer located in the sacrificial area and an anti-etching layer located in the anti-etching area are formed by ion doping the core layer, which is not only conducive to simplifying the process, but also makes the sacrificial layer and the anti-etching layer have different etching rates by ion doping. In the step of removing the sacrificial layer by an etching process, the etching rate of the sacrificial layer by the etching process is greater than the etching rate of the anti-etching layer, which is conducive to reducing the difficulty of removing the sacrificial layer and improving the process controllability of removing the sacrificial layer. The pattern accuracy of the second groove is also improved, and the anti-etching layer can be retained in the step of removing the sacrificial layer, which correspondingly ensures the role of the anti-etching layer as a mask for the patterned target layer. In the step of etching the target layer at the bottom of the first groove and the second groove to form a target pattern, it is conducive to obtaining a higher pattern transfer accuracy and a better patterning effect, thereby improving the pattern accuracy of the target pattern and improving the matching degree between the target pattern and the design pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 24 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0023] As can be seen from the background art, how to improve the matching degree between the target pattern formed on the wafer and the designed pattern has become a challenge.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer on the substrate, the core layer including an anti-etching region for forming an anti-etching layer and a sacrificial region for forming a sacrificial layer; ion doping the core layer in the sacrificial region, suitable for making the core layer in the sacrificial region and the core layer in the anti-etching region have different etching rates, the core layer doped with ions in the sacrificial region is used as the sacrificial layer, and the core layer not doped with ions in the anti-etching region is used as the anti-etching layer; forming a core layer that penetrates the core layer located in the phase A groove of the core layer between adjacent sacrificial areas, the sidewalls of the groove expose the core layer located in the sacrificial area; sidewalls are formed on the sidewalls of the groove, and the sidewalls located on the sidewalls of the groove form a first groove; after ion doping and forming the first groove, an etching process is used to remove the sacrificial layer, and a second groove penetrating the anti-etching layer is formed in the anti-etching layer; wherein the etching rate of the sacrificial layer by the etching process is greater than the etching rate of the anti-etching layer; using the anti-etching layer and the sidewalls as masks, the target layer at the bottom of the first groove and the second groove is etched to form a target pattern.

[0025] In the method for forming a semiconductor structure provided by an embodiment of the present invention, ion doping is performed on the core layer of the sacrificial area, which is suitable for making the core layer of the sacrificial area and the core layer of the anti-etching area have different etching rates, so that a sacrificial layer located in the sacrificial area and an anti-etching layer located in the anti-etching area are formed by ion doping the core layer, which is not only conducive to simplifying the process, but also makes the sacrificial layer and the anti-etching layer have different etching rates by ion doping. In the step of removing the sacrificial layer by an etching process, the etching rate of the sacrificial layer by the etching process is greater than the etching rate of the anti-etching layer, which is conducive to reducing the difficulty of removing the sacrificial layer and improving the process controllability of removing the sacrificial layer. The pattern accuracy of the second groove is also improved, and the anti-etching layer can be retained in the step of removing the sacrificial layer, which correspondingly ensures the role of the anti-etching layer as a mask for the patterned target layer. In the step of etching the target layer at the bottom of the first groove and the second groove to form a target pattern, it is conducive to obtaining a higher pattern transfer accuracy and a better patterning effect, thereby improving the pattern accuracy of the target pattern and improving the matching degree between the target pattern and the design pattern.

[0026] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 24 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0028] refer to Figure 1, providing a substrate (not shown) including a target layer 100 for forming a target pattern.

[0029] The substrate is used to provide a platform for subsequent process steps.

[0030] The target layer 100 is a film layer to be patterned to form a target pattern.

[0031] Among them, the target graphics can be gate structures, interconnect grooves in the back-end process, fins in fin field effect transistors (FinFETs), channel stacks in all-around gate (GAA) transistors or fork-type gate transistors (Forksheet), hard mask (HM) layers and other graphics.

[0032] In this embodiment, the target layer 100 is a dielectric layer. The dielectric layer is subsequently patterned to form a plurality of interconnection grooves in the dielectric layer, and then metal lines are formed in the interconnection grooves. The dielectric layer is used to achieve electrical isolation between adjacent metal lines. Accordingly, the target pattern is an interconnection groove. The dielectric layer is correspondingly an intermetallic dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride, etc.

[0033] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.

[0034] In this embodiment, the substrate further includes a hard mask material layer 110 located on the target layer 100 , and an etch stop layer 120 located on the hard mask material layer 110 .

[0035] The hard mask material layer 110 is used to form a hard mask layer after a subsequent patterning process. Specifically, after the first groove and the second groove are subsequently formed, the patterns of the first groove and the second groove can be first transferred to the hard mask material layer 110 to form a hard mask layer, and then the target layer 100 can be etched using the hard mask layer as a mask. Even if the subsequent anti-etching layer and the sidewall are consumed during the patterning process, the target layer 100 can still be etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of the patterning.

[0036] In this embodiment, the material of the hard mask material layer 110 is silicon nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride or tungsten nitride.

[0037] The subsequent process includes multiple etching steps. The etch stop layer 120 is used to define the etching stop position in the subsequent etching process, which is beneficial to reduce the loss of the target layer 100, improve the depth consistency of the etching process, and further improve the effect of the subsequent graphic process.

[0038] In this embodiment, the material of the etch stop layer 120 is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride or aluminum nitride.

[0039] refer to Figure 2 and Figure 3 , Figure 2 is a top view, Figure 3 yes Figure 2 In the cross-sectional view along the yy cut line, a core layer (Mandrel) 130 is formed on the substrate, and the core layer 130 includes an anti-etching region A for forming an anti-etching layer and a sacrificial region B for forming a sacrificial layer.

[0040] Subsequently, the core layer 130 is ion doped to form the anti-etching layer and the sacrificial layer.

[0041] Specifically, in this embodiment, the core layer 130 of the sacrificial region B is used to form a sacrificial layer through subsequent ion doping, and the remaining core layer 130 of the anti-etching region A that is not doped with ions is used as an anti-etching layer.

[0042] Therefore, the division of the anti-etching area A and the sacrificial area B depends on the formation position and pattern of the subsequent anti-etching layer and the sacrificial layer.

[0043] In this embodiment, part of the core layer 130 is used as the sacrificial area B, and the remaining area is used as the anti-etching area A.

[0044] In this embodiment, there are multiple sacrificial areas B, and the sacrificial areas B are arranged in a horizontal direction (such as Figure 2 X direction), and along the longitudinal direction (as shown Figure 2 As an example, two sacrificial areas B are shown in the figure.

[0045] The material of the core layer 130 includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride or silicon carbon nitride. In this embodiment, the material of the core layer 130 is amorphous silicon.

[0046] In this embodiment, a deposition process (eg, chemical vapor deposition process) is used to form the core layer 130 .

[0047] refer to Figures 4 to 9 , the core layer 130 of the sacrificial area B is ion-doped, which is suitable for making the core layer 130 of the sacrificial area B and the core layer 130 of the anti-etching area A have different etching rates, the core layer 130 doped with ions in the sacrificial area B is used as a sacrificial layer 160, and the core layer 130 not doped with ions in the anti-etching area A is used as an anti-etching layer 150.

[0048] Subsequent steps also include: forming a groove penetrating the core layer 130 between adjacent sacrificial regions B; forming sidewalls on the sidewalls of the groove, the sidewalls on the sidewalls of the groove forming a first groove; and removing the sacrificial layer to form a second groove.

[0049] In this embodiment, the core layer 130 of the sacrificial area B is ion-doped, which is suitable for making the core layer 130 of the sacrificial area B and the core layer 130 of the anti-etching area A have different etching rates, so that the sacrificial layer 160 and the anti-etching layer 150 are formed by ion-doping the core layer 130, which is not only conducive to simplifying the process, but also makes the sacrificial layer 160 and the anti-etching layer 150 have different etching rates by ion doping. In the subsequent step of removing the sacrificial layer 160 by an etching process, the etching rate of the sacrificial layer 160 by the etching process is greater than that of the anti-etching layer 150. The etching rate is conducive to reducing the difficulty of removing the sacrificial layer 160 and improving the process controllability of removing the sacrificial layer 160. The graphic accuracy of the second groove is also improved, and the anti-etching layer 150 can be retained in the step of removing the sacrificial layer 160, which correspondingly ensures the role of the anti-etching layer 150 as a mask for the patterned target layer 100. In the step of etching the target layer 100 at the bottom of the first groove and the second groove to form a target pattern, it is conducive to obtaining higher graphic transfer accuracy and better graphic effect, thereby improving the graphic accuracy of the target pattern and improving the matching degree between the target pattern and the design pattern.

[0050] In this embodiment, making the core layer 130 of the sacrificial area B and the core layer 130 of the anti-etching area A have different etching rates means that under the same etching process conditions, the core layer 130 of the sacrificial area B and the core layer 130 of the anti-etching area A have different etching rates.

[0051] In this embodiment, the core layer 130 of the sacrificial area B and the core layer 130 of the anti-etching area A have different etching rates, so that it is easy to select a specific etching process in the subsequent process so that the etching process has a higher etching selectivity ratio between the sacrificial layer 160 and the anti-etching layer 150, thereby correspondingly reducing the difficulty of subsequent removal of the sacrificial layer 160 and increasing the process window for forming the second groove.

[0052] As an example, after forming the core layer 130 and before forming the trench, ion doping is performed on the core layer 130 of the sacrificial region B.

[0053] In other embodiments, the core layer of the sacrificial area may be ion doped after forming the groove and before forming the sidewall; or, the core layer of the sacrificial area may be ion doped after forming the sidewall and before forming the second groove.

[0054] In this embodiment, the doping depth of the ion doping is the entire thickness of the core layer 130 .

[0055] In this embodiment, the ions doped into the core layer 130 of the sacrificial region B include boron ions, phosphorus ions, arsenic ions or argon ions. As an example, the ions doped into the core layer 130 of the sacrificial region B are boron ions.

[0056] When the core layer 130 is doped with the ions, the inventors found that when the ion doping concentration in the core layer 130 is greater than a doping concentration value, when a specific etching process is selected, the etching rate of the core layer 130 material doped with ions by the etching process is much greater than the etching rate of the core layer 130 material not doped with ions, and the etching rate of the core layer 130 not doped with ions by the etching process is even close to stopping, so that the etching process has a higher etching selectivity for the sacrificial layer 160 and the anti-etching layer 150, thereby ensuring that the subsequent process difficulty of removing the sacrificial layer 160 is low and the process window is large, and the anti-etching layer 150 can be retained in the step of removing the sacrificial layer 160.

[0057] Specifically, in this embodiment, the material of the core layer 130 is amorphous silicon. Doping boron ions in the amorphous silicon can change the etching rate of the amorphous silicon material, thereby making the etching rates of the sacrificial layer 160 and the anti-etching layer 150 different.

[0058] Therefore, in the step of ion doping the core layer 130 of the sacrificial region B, the ion doping concentration in the core layer 130 of the sacrificial region B should not be too small, otherwise it is easy to cause the difference in etching rate between the core layer 130 doped with ions and the core layer 130 not doped with ions to be unclear, and thus it is easy to reduce the effect of increasing the process window for subsequent removal of the sacrificial layer 160. Therefore, in the present embodiment, in the step of ion doping the core layer 130 of the sacrificial region B, the ion doping concentration in the core layer 130 of the sacrificial region B is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

[0059] As an example, the sacrificial layer 160 is doped with boron ions, and the doping concentration of the boron ions in the sacrificial layer 160 is 1.0E19 atoms per cubic centimeter.

[0060] In this embodiment, there are multiple sacrificial areas B, and therefore, there are multiple sacrificial layers 160. The multiple sacrificial layers 160 extend in the transverse direction and are arranged at intervals in the longitudinal direction.

[0061] In this embodiment, the step of ion doping the core layer 130 of the sacrificial area B includes:

[0062] like Figure 4 and Figure 5 As shown, Figure 4 is a top view, Figure 5 for Figure 4 According to the cross-sectional view along the yy cut line, a shielding layer 140 covering the anti-etching area A is formed, and the sacrificial area B is exposed by the shielding layer 140 .

[0063] The shielding layer 140 is used to shield the core material layer 130 in the second region.

[0064] In this embodiment, the material of the shielding layer 140 is spin-on carbon (SOC). In other embodiments, the material of the shielding layer can also be other organic materials, such as BARC (Bottom Anti-reflective coating) material, ODL (Organic Dielectric layer) material, etc.

[0065] As an example, the steps of forming the shielding layer 140 include: forming an initial shielding layer (not shown) on the core layer 130; forming a patterned layer (not shown) on the initial shielding layer; and using the patterned layer as a mask to pattern the initial shielding layer to form the shielding layer 140.

[0066] In this embodiment, the process of forming the initial shielding layer includes a spin-on process.

[0067] In this embodiment, the material of the patterned layer includes photoresist, and the process of forming the patterned layer includes photolithography processes such as photoresist coating, exposure, and development.

[0068] In this embodiment, the process of patterning the initial shielding layer includes an anisotropic dry etching process. The anisotropic dry etching process is conducive to improving the accuracy of pattern transfer.

[0069] like Figure 6 and Figure 7 As shown, Figure 6 is a top view, Figure 7 for Figure 6 In the cross-sectional view along the yy cut line, the shielding layer 140 is used as a mask to perform ion doping on the core layer 130 .

[0070] In this embodiment, the shielding layer 140 exposes the sacrificial area B, and therefore, the core layer 130 of the sacrificial area B is ion doped.

[0071] In this embodiment, an ion implantation process is used to perform ion implantation on the core layer 130 of the sacrificial region B. The ion implantation process is simple and easy to operate, and it is easy to adjust the implantation direction and energy so that the doping depth meets the process requirements, and it is also easy to adjust the implantation dose so that the ion doping concentration meets the process requirements.

[0072] In this embodiment, the parameters of the ion implantation process include: an implantation energy of 1 KeV to 100 KeV, and an angle between the implantation direction and the normal line of the substrate surface of 0° to 5°.

[0073] The injection energy of the ion implantation process should not be too small or too large. If the injection energy of the ion implantation process is too small, it is easy to cause insufficient ion implantation depth, which in turn easily leads to unclear difference in etching rate between the core layer 130 doped with ions and the core layer 130 not doped with ions; if the injection energy of the ion implantation process is too large, it is easy to cause excessive injection damage and produce side effects. For this reason, in this embodiment, the injection energy of the ion implantation process is 1KeV to 100KeV.

[0074] The angle between the ion implantation direction and the substrate surface normal should not be too large, otherwise it will easily increase the risk of ion implantation into the core layer 130 of the anti-etching area A. For this reason, in this embodiment, the angle between the implantation direction of the ion implantation process and the substrate surface normal is 0° to 5°.

[0075] like Figure 8 and Fig. 9 As shown, Figure 8 is a top view, Fig. 9 yes Figure 8 The cross-sectional view along the yy cut line shows that the shielding layer 140 is removed.

[0076] The blocking layer 140 is removed to expose the top surfaces of the anti-etching layer 150 and the sacrificial layer 160 , so as to facilitate subsequent process steps.

[0077] Specifically, one or both of an ashing process and a wet stripping process may be used to remove the shielding layer 140 .

[0078] refer to Figures 10 to 15, a groove 180 penetrating the core layer 130 located between adjacent sacrificial regions B is formed, and the sidewall of the groove 180 exposes the core layer 130 located in the sacrificial region B.

[0079] The sidewalls of the groove 180 are used to provide support for the subsequent formation of the sidewalls, and the groove 180 and the subsequent sidewalls together define the shape and position of the first groove. Specifically, the sidewalls are subsequently formed on the sidewalls of the groove 180, and the sidewalls located on the sidewalls of the groove 180 enclose the first groove.

[0080] In this embodiment, before forming the groove 180 , the core layer 130 of the sacrificial area B is ion doped to form the sacrificial layer 160 and the anti-etching layer 150 . Therefore, the groove 180 penetrates the anti-etching layer 150 located between adjacent sacrificial layers 160 , and the sidewall of the groove 180 exposes the sacrificial layer 160 .

[0081] As an example, in an actual process, the groove 180 may also penetrate a portion of the width of the core layer 130 (ie, the sacrificial layer 160 ) of the sacrificial region B in the longitudinal direction.

[0082] In this embodiment, the number of the grooves 180 is also multiple, and the multiple grooves 180 extend in the horizontal direction and are arranged at intervals with the core layer 130 of the sacrificial area B in the longitudinal direction.

[0083] In this embodiment, along the longitudinal direction, the sacrificial area B located at the edge position serves as the edge sacrificial area, and the groove 180 is also located in the core layer 130 on a side of the edge sacrificial area away from the adjacent sacrificial area B.

[0084] In this embodiment, the steps of forming the groove 180 include:

[0085] like Fig.10 and Fig.11 As shown, Fig.10 is a top view, Fig.11 for Fig.10 In the cross-sectional view along the yy cut line, a mask layer 170 is formed on the anti-etching layer 150 and the sacrificial layer 160 , and a pattern opening 175 is formed in the mask layer 170 to expose a portion of the anti-etching layer 150 between adjacent sacrificial layers 160 .

[0086] The mask layer 170 is used as a mask for etching the anti-etching layer 150 to form a trench.

[0087] Specifically, the mask layer 170 is formed on the etch stop layer 120 .

[0088] In this embodiment, the material of the mask layer 170 is spin-on carbon. The material and formation steps of the mask layer 170 can refer to the above description of the shielding layer, which will not be repeated here.

[0089] In this embodiment, the mask layer 170 also exposes a partial width of the sacrificial layer 160 and a portion of the anti-etching layer 150 adjacent to the sacrificial layer 160 .

[0090] like Fig.12 and Fig.13 As shown, Fig.12 is a top view, Fig.13 yes Fig.12 In the cross-sectional view along the yy cut line, the mask layer 170 is used as a mask to remove the anti-etching layer 150 at the bottom of the pattern opening 175 to form a trench 180 .

[0091] In this embodiment, an anisotropic dry etching process (e.g., plasma etching process) is used to remove the anti-etching layer 150 at the bottom of the pattern opening 175. The plasma etching process has good profile control and high etching accuracy, which is beneficial to improving the pattern accuracy and profile quality of the groove 180, and is also beneficial to improving the etching efficiency.

[0092] In this embodiment, the graphic opening 175 also exposes a partial width of the sacrificial layer 160 and a portion of the anti-etching layer 150 adjacent to the sacrificial layer 160. Therefore, in the process of removing the anti-etching layer 150 at the bottom of the graphic opening 175, a portion of the sacrificial layer 160 and a portion of the anti-etching layer 150 adjacent to the sacrificial layer 160 are also removed.

[0093] Correspondingly, the groove 180 is also formed in the anti-etching layer 150 adjacent to the sacrificial layer 160. Specifically, in this embodiment, there are a plurality of grooves 180, and the plurality of grooves 180 are arranged at intervals in the longitudinal direction.

[0094] like Fig.14 and Fig.15 As shown, Fig.14 is a top view, Fig.15 yes Fig.14 In the cross-sectional view along the yy cut line, the mask layer 170 is removed.

[0095] The mask layer 170 is removed to facilitate subsequent process steps. Specifically, the process of removing the mask layer 170 includes one or both of an ashing process and a wet stripping process.

[0096] Combined with reference Fig.16As an example, the method for forming the semiconductor structure further includes: after forming the core layer 130 and before forming the sidewall, forming a cutting groove 200 that penetrates the core layer 130 of the sacrificial area B in the longitudinal direction, and the cutting groove 200 divides the core layer 130 of the sacrificial area B in the transverse direction.

[0097] The cutting groove 200 divides the core layer 130 of the sacrificial area B in the transverse direction, so that after ion doping is performed to form the anti-etching layer 150 and the sacrificial layer 160, the cutting groove 200 divides the sacrificial layer 160 in the transverse direction, and then in the step of forming the side wall, the side wall can also be filled in the cutting groove 200. The side wall located in the cutting groove 200 is used as a dividing layer, which is used to divide the sacrificial layer 160 in the transverse direction, and then after the sacrificial layer 160 is subsequently removed to form a second groove, the dividing layer divides the second groove in the transverse direction, which is conducive to achieving a smaller distance between adjacent second grooves.

[0098] As an example, after forming the trench 180 and performing ion doping, and before forming the sidewall, the cutting groove 200 is formed. Accordingly, the cutting groove 200 penetrates the sacrificial layer 160 in the longitudinal direction and divides the sacrificial layer 160 in the transverse direction.

[0099] In other embodiments, the cutting groove may be formed after forming the core layer and before ion doping; or, the cutting groove may be formed after ion doping and before forming the trench.

[0100] refer to Figure 17 to Figure 18 , Fig.17 is a top view, Fig.18 for Fig.17 In the cross-sectional view along the yy cut line, a sidewall 190 is formed on the sidewall of the trench 180 , and the sidewall 190 located on the sidewall of the trench 180 forms a first groove 210 .

[0101] The sidewall 190 is used as a partial mask for subsequent etching of the target layer 100. In this embodiment, the pattern of the first groove 210 is defined by the sidewall 190 and the groove 180. In the process of forming the groove 180, the size of the groove 180 is relatively large, and the dimensional accuracy requirement of the groove 180 is low, which is conducive to reducing the difficulty of forming the groove 180 and increasing the process window.

[0102] Subsequent steps also include: removing the sacrificial layer 160 to form a second groove. In this embodiment, before forming the second groove, by forming the sidewall 190, the first groove 210 and the second groove can be isolated from each other, and the spacing between adjacent first grooves 210 and second grooves meets the minimum spacing designed; accordingly, after etching the target layer 100 at the bottom of the first groove 210 and the second groove, the spacing between the target patterns formed in the target layer 100 meets the minimum spacing designed.

[0103] In this embodiment, the side wall 190 is also filled in the cutting groove 200. The side wall 190 located in the cutting groove 200 is used as a partition layer for partitioning the sacrificial layer 160. After the sacrificial layer 160 is subsequently removed to form a second groove, the partition layer is used to partition the second groove, which is beneficial to achieve a smaller distance between the second grooves.

[0104] The material of the sidewall 190 may be titanium oxide, titanium nitride, silicon oxide, silicon nitride or aluminum oxide. In this embodiment, the material of the sidewall 190 is titanium oxide. The etching selectivity of titanium oxide material and amorphous silicon or silicon nitride is relatively high, and the sidewall 190 can be retained in the subsequent step of removing the sacrificial layer 160, and the sidewall 190 can be used as a mask for etching the target layer 100.

[0105] In this embodiment, the step of forming the side wall 190 includes: forming a side wall material layer (not shown) on the side wall and bottom of the groove 180, and on the top surface of the anti-etching layer 150 and the sacrificial layer 160; removing the side wall material layer located at the bottom of the groove 180, and the top surface of the anti-etching layer 150 and the sacrificial layer 160, and the remaining side wall material layer located on the side wall of the groove 180 is used as the side wall 190.

[0106] In this embodiment, the sidewall material layer is formed by an atomic layer deposition process. The atomic layer deposition process has a strong step coverage capability, which is beneficial to improving the coverage capability of the sidewall material layer on the sidewall of the groove 180. In addition, by selecting the atomic layer deposition process, it is also beneficial to improve the thickness uniformity of the sidewall material layer and to accurately control the thickness of the sidewall 190.

[0107] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to remove the sidewall material layer at the bottom of the trench 180 and the top surfaces of the anti-etching layer 150 and the sacrificial layer 160. The anisotropic dry etching process has the characteristic of anisotropic etching, so that the sidewall material layer at the bottom of the trench 180 and the top surfaces of the anti-etching layer 150 and the sacrificial layer 160 can be removed without a mask, while the sidewall material layer on the sidewall of the trench 180 is retained.

[0108] As an example, the thickness of the sidewall 190 is 50 angstroms to 300 angstroms. The thickness of the sidewall 190 is small, so that a small interval is achieved between adjacent first grooves 210 and second grooves 220. The thickness of the sidewall 190 refers to the dimension of the sidewall 190 in a direction perpendicular to the sidewall of the groove 180.

[0109] refer to Fig.19 and Fig. 20 , Fig.19 is a top view, Fig. 20 for Fig.19 In the cross-sectional view along the yy cut line, after ion doping and formation of the first groove 210, an etching process is used to remove the sacrificial layer 160, and a second groove 220 penetrating the anti-etching layer 150 is formed in the anti-etching layer 150; wherein the etching rate of the sacrificial layer 160 by the etching process is greater than the etching rate of the anti-etching layer 150.

[0110] The second groove 220 and the first groove 210 together define the pattern of the target pattern. After the second groove 220 and the first groove 210 are formed, the sidewall spacer 190 and the remaining anti-etching layer 150 are used as masks for patterning the target layer 100 .

[0111] In this embodiment, the number of the second grooves 220 is multiple. The second grooves 220 are arranged along the horizontal direction (such as Fig.19 The second grooves 220 extend in the longitudinal direction (as shown in the X direction). Fig.19 The second groove 220 and the first groove 210 are spaced apart from each other (as shown in the Y direction), and the second groove 220 and the first groove 210 are separated by the side wall 190, which is conducive to ensuring that the second groove 220 and the first groove 210 meet the designed minimum spacing.

[0112] In this embodiment, ion doping is performed on the core layer 130 of the sacrificial region B, which is suitable for making the core layer 130 of the sacrificial region B (that is, the sacrificial layer 160) and the core layer 130 of the anti-etching region A (that is, the anti-etching layer 150) have different etching rates, which is not only conducive to simplifying the process, but also makes the sacrificial layer 160 and the anti-etching layer 150 have different etching rates by ion doping. Accordingly, in the step of removing the sacrificial layer 160 by an etching process, the etching rate of the sacrificial layer 160 by the etching process is greater than the etching rate of the anti-etching layer 150, which is conducive to reducing the removal of the sacrificial layer 1 60, improves the process controllability of removing the sacrificial layer 160, and the graphic accuracy of the second groove 220 is also improved. It also enables the anti-etching layer 150 to be retained in the step of removing the sacrificial layer 160, and correspondingly ensures that the anti-etching layer 150 acts as a mask for patterning the target layer 100. In the step of etching the target layer 100 at the bottom of the first groove 210 and the second groove 220 to form a target pattern, it is beneficial to obtain higher graphic transfer accuracy and better graphic effect, thereby improving the graphic accuracy of the target pattern and improving the matching degree between the target pattern and the design pattern.

[0113] In addition, after forming the groove 180, the present embodiment forms a sidewall 190 on the sidewall of the groove 180, so that the sidewall 190 located on the sidewall of the groove 180 surrounds the first groove 210, and then removes the sacrificial layer 160 to form the second groove 220. The present embodiment forms the first groove 210 and the second groove 220 in different steps, which is conducive to reducing the difficulty of forming the first groove 210 and the second groove 220 and increasing the process window (for example, improving the optical proximity effect), so that the graphic accuracy of the first groove 210 and the second groove 220 is guaranteed. Correspondingly, after the target layer 100 at the bottom of the first groove 210 and the second groove 220 is subsequently etched to form a target pattern, the graphic accuracy of the target pattern is also improved.

[0114] In this embodiment, after removing the sacrificial layer 160 to form the second groove 220, the second groove 220 is divided by the dividing layer in the horizontal direction, which is conducive to achieving a smaller distance between adjacent second grooves 220 in the horizontal direction, that is, the second groove 220 achieves a smaller line end distance at the head-to-head (HTH) position, thereby improving the design freedom of the target pattern.

[0115] In this embodiment, a wet etching process is used to remove the sacrificial layer 160. Specifically, in this embodiment, the sacrificial layer 160 is doped with ions, and the wet etching process has different etching rates for the core layer 130 doped with ions and the core layer 130 not doped with ions, and the wet etching process has a large etching selectivity ratio for the anti-etching layer 150 and the sacrificial layer 160, so that the anti-etching layer 150 can be retained during the removal of the sacrificial layer 160.

[0116] In this embodiment, the etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid, that is, HNA solution. Compared with the etching rate of amorphous silicon not doped with ions, the etching rate of the HNA solution on amorphous silicon doped with the ions is greater. By selecting the HNA solution, it is beneficial to improve the etching selectivity of the wet etching process for amorphous silicon doped with ions and amorphous silicon not doped with ions, that is, to improve the etching selectivity of the sacrificial layer 160 and the anti-etching layer 150, thereby significantly reducing the process difficulty of removing the sacrificial layer 160 and reducing the probability of damage to the anti-etching layer 150, thereby significantly improving the pattern accuracy and pattern quality of the second groove 220, and also helping to improve the pattern integrity of the first groove 210.

[0117] As an example, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the volume ratio of hydrofluoric acid to acetic acid is 1:8 to 1:100, and the volume ratio of hydrofluoric acid to nitric acid is 1:3 to 1:50. By setting the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the above range, it is ensured that the HNA solution can significantly improve the etching selectivity of the sacrificial layer 160 and the anti-etching layer 150, and even the etching rate of the anti-etching layer 150 is close to stopping.

[0118] As an example, in the HNA solution used in the wet etching process, the volume ratio of hydrofluoric acid, nitric acid and acetic acid is 1:3:8.

[0119] As an example, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molecular ratio between nitric acid and hydrofluoric acid is at least 2, and the molar percentage of nitric acid is at least 14%.

[0120] As an example, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molar percentage of hydrofluoric acid is 0.2% to 6%, the molar percentage of nitric acid is 14% to 28%, and the molar percentage of acetic acid is 66% to 86%.

[0121] By setting the molecular ratio between nitric acid and hydrofluoric acid, and the molar percentages of hydrofluoric acid, nitric acid and acetic acid within the above range, it is beneficial to make the HNA solution have a more significant effect of improving the etching selectivity of the sacrificial layer 160 and the anti-etching layer 150, and even the etching rate of the anti-etching layer 150 is close to stopping. At the same time, it is also beneficial to make the wet etching process have a slower etching rate for the sacrificial layer 160, so that the etching rate of the wet etching process is controllable, the process controllability of the wet etching process is improved, and the process difficulty of removing the sacrificial layer 160 is further reduced.

[0122] refer to Fig.21 and Fig. 22 , Fig.21 is a top view, Fig. 22 for Fig.21 In the cross-sectional view along the yy cut line, the target layer 100 at the bottom of the first groove 210 and the second groove 220 is etched using the anti-etching layer 150 and the sidewall 190 as masks to form a target pattern 300 .

[0123] It can be seen from the above records that the graphic accuracy and graphic quality of the first groove 210 and the second groove 220 are relatively high, and the anti-etching layer 150 can be used as a mask for etching the target layer 100 to be guaranteed, which is correspondingly beneficial to improving the process effect of patterning the target layer 100, thereby improving the graphic accuracy and graphic quality of the target graphic 300.

[0124] In this embodiment, the target layer 100 is a dielectric layer, so the dielectric layer at the bottom of the first groove 210 and the second groove 220 is etched using the anti-etching layer 150 and the sidewall 190 as masks to form interconnect grooves. Accordingly, in this embodiment, the target pattern 300 is an interconnect groove.

[0125] The interconnection groove is used to provide a spatial location for forming a metal line.

[0126] In this embodiment, a hard mask material layer 110 and an etch stop layer 120 are further formed on the target layer 100 , and the etch stop layer 120 is exposed at the bottom of the first groove 210 and the second groove 220 .

[0127] Therefore, using the anti-etching layer 150 and the side wall 190 as masks, the etching stop layer 120 and the hard mask material layer 110 at the bottom of the first groove 210 and the second groove 220 are etched in sequence, and the remaining hard mask material layer 110 is used as the hard mask layer 230; using the hard mask layer 230 as a mask, the target layer 100 is patterned.

[0128] By first transferring the patterns of the first groove 210 and the second groove 220 to the hard mask material layer 110 to form the hard mask layer 230 , the process stability and process effect of patterning the target layer 100 can be improved.

[0129] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to sequentially etch the etching stop layer 120, the hard mask material layer 110, and the target layer 100 at the bottom of the first groove 210 and the second groove 220. The dry etching process has the characteristics of anisotropic etching, and the etching profile controllability is good, which is conducive to improving the accuracy of pattern transfer, thereby making the target pattern 300 formed in the target layer 100 meet the process requirements, and the dry etching process is also conducive to achieving a larger etching selectivity, thereby improving the process effect of patterning the target layer 100.

[0130] In this embodiment, during the process of patterning the target layer 100 , the anti-etching layer 150 and the sidewall spacer 190 are also partially consumed in thickness.

[0131] Combined with reference Fig.23 and Fig.24 , Fig.23 is a top view, Fig.24 for Fig.23 A cross-sectional view along the yy cut line. In this embodiment, the method for forming the semiconductor structure further includes: after forming the interconnection groove, forming a metal line 310 in the interconnection groove.

[0132] The metal line 310 is used to realize electrical connection between the semiconductor structure and an external circuit or other interconnection structures.

[0133] It can be seen from the above records that the graphic accuracy and graphic quality of the interconnection grooves are high, and the spacing between adjacent interconnection grooves is easy to meet the designed minimum spacing, which is correspondingly beneficial for the longitudinal spacing of the metal wires 310 to meet the designed minimum spacing. At the same time, the interconnection grooves can also achieve a smaller distance at the head-to-head position, which is also beneficial to improve the graphic accuracy and design freedom of the metal wire 310, and thus help improve the electrical connection performance of the metal wire 310.

[0134] In this embodiment, the material of the metal wire 310 is copper. In other embodiments, the material of the wire can also be a conductive material such as cobalt, tungsten, aluminum, etc.

[0135] In this embodiment, during the process of forming the metal line 310 , the remaining anti-etching layer 150 , the sidewall spacer 190 , the etch stop layer 120 and the hard mask layer 230 are also removed, thereby exposing the top surface of the dielectric layer to prepare for subsequent processes.

[0136] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate including a target layer for forming a target pattern; forming a core layer on the substrate, wherein the core layer comprises an anti-etching region for forming an anti-etching layer and a sacrificial region for forming a sacrificial layer; Ion doping is performed on the core layer of the sacrificial area, which is suitable for making the core layer of the sacrificial area and the core layer of the anti-etching area have different etching rates, the core layer doped with ions in the sacrificial area is used as a sacrificial layer, and the core layer not doped with ions in the anti-etching area is used as an anti-etching layer; forming a groove penetrating the core layer between adjacent sacrificial regions, wherein the sidewall of the groove exposes the core layer located in the sacrificial region; Forming side walls on the side walls of the groove, wherein the side walls located on the side walls of the groove form a first groove; After ion doping and forming the first groove, an etching process is used to remove the sacrificial layer, and a second groove penetrating the anti-etching layer is formed in the anti-etching layer; wherein the etching rate of the sacrificial layer by the etching process is greater than the etching rate of the anti-etching layer; The target layer at the bottom of the first groove and the second groove is etched using the anti-etching layer and the sidewall as masks to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming the core layer and before forming the trench, ion doping the core layer of the sacrificial region; Alternatively, after forming the trench and before forming the sidewall, ion doping is performed on the core layer of the sacrificial region; Alternatively, after forming the sidewall spacer and before forming the second groove, ion doping is performed on the core layer of the sacrificial region.

3. The method for forming a semiconductor structure according to claim 1, wherein: The ions used for ion doping the core layer of the sacrificial region include boron ions, phosphorus ions, arsenic ions or argon ions.

4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing ion doping on the core layer of the sacrificial region, the ion doping concentration in the core layer of the sacrificial region is 1.0E15 atoms per cubic centimeter to 1.0E20 atoms per cubic centimeter.

5. The method for forming a semiconductor structure according to claim 1, wherein: The core layer of the sacrificial area is doped with ions by using an ion implantation process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The parameters of the ion implantation process include: an implantation energy of 1 KeV to 100 KeV, and an angle between the implantation direction and the normal line of the substrate surface of 0° to 5°.

7. The method for forming a semiconductor structure according to claim 1, wherein: The sacrificial layer is removed by a wet etching process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The etching solution used in the wet etching process includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid.

9. The method for forming a semiconductor structure according to claim 8, wherein: In the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molecular ratio between the nitric acid and the hydrofluoric acid is at least 2, and the molar percentage of the nitric acid is at least 14%.

10. The method for forming a semiconductor structure according to claim 9, wherein: In the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the molar percentage of hydrofluoric acid is 0.2% to 6%, the molar percentage of nitric acid is 14% to 28%, and the molar percentage of acetic acid is 66% to 86%.

11. The method for forming a semiconductor structure according to claim 8, wherein: In the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the volume ratio of hydrofluoric acid to acetic acid is 1:8 to 1:100, and the volume ratio of hydrofluoric acid to nitric acid is 1:3 to 1:

50.

12. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the core layer, the material of the core layer includes amorphous silicon, silicon nitride, amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polycrystalline silicon, silicon carbide, silicon carbonitride or silicon carbon nitride.

13. The method for forming a semiconductor structure according to claim 1, wherein: The step of performing ion doping on the core layer of the sacrificial area includes: forming a shielding layer covering the anti-etching area, wherein the shielding layer exposes the sacrificial area; and performing ion doping on the core layer using the shielding layer as a mask.

14. The method for forming a semiconductor structure according to claim 1, wherein: The target layer is a dielectric layer; Using the anti-etching layer and the sidewall as masks, etching the dielectric layer at the bottom of the first groove and the second groove to form an interconnection groove; The method for forming a semiconductor structure further includes: after forming the interconnection trench, forming a metal line in the interconnection trench.

Images