Chip Resistors

Abstract

The object is to provide a chip resistor capable of handling high power. The chip resistor disclosed herein comprises an insulating substrate (11), a pair of electrodes (12), and a resistor (13). A pair of electrodes (12) are provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is provided on the insulating substrate (11) and is connected to the pair of electrodes (12). The insulating substrate (11) has a first region (11a) in its central portion and second regions (11b) at both ends of the first region (11a). A recess (20) is provided in the first region (11a) of the insulating substrate (11). The resistor (13) formed in the first region (11a) is serpentine in a plan view. At least a portion of the resistor (13) is buried in the recess (20). A trimming groove (14) is provided in the resistor (13) formed in the second region (11b).

Description

Technical Field

[0001] The present disclosure relates to a chip resistor formed of a thick film resistor element used in various electronic devices, and particularly to a chip resistor used in electronic devices requiring high power. Background Art

[0002] Existing chip resistors such as Fig. 20 as well as Fig.21 As shown, it comprises: a substrate 1 composed of an insulator, a pair of electrodes 2, a layer 3 composed of a resistor, protective films 4a, 4b, electrodes 5 arranged on a pair of end faces, and a metal layer 6 formed by plating. The pair of electrodes 2 are respectively arranged at the two end portions of the upper surface of the substrate 1. The layer 3 composed of the resistor is arranged on the upper surface of the substrate 1 and between the pair of electrodes 2. The protective films 4a, 4b are arranged to at least cover the layer 3 composed of the resistor. The pair of electrodes 5 are respectively arranged on the two end surfaces of the substrate 1 so as to be electrically connected to the pair of electrodes 2 respectively. The metal layer 6 is arranged on a part of the surface of the pair of electrodes 2 and the surface of the pair of electrodes 5. The layer 3 composed of the resistor is formed in a meandering shape. In addition, Fig. 20 FIG. 4 is a top view of an existing chip resistor. Fig.21 Yes Fig. 20 The chip resistor shown is a cross-sectional view cut along line XXI-XXI.

[0003] in addition, Fig. 20 as well as Fig.21 The conventional chip resistor shown is disclosed in Patent Document 1, for example.

[0004] In addition, the existing chip resistors different from the above are Fig. 22 As shown, it comprises: a substrate 1 composed of an insulator, a pair of electrodes 2, a layer 3 composed of a resistor, a protective film 4, and a glass layer 8. A recess is formed in the substrate 1, and a glass layer 8 is provided at the bottom of the recess. The layer 3 composed of a resistor is provided in the recess of the substrate 1 and above the glass layer 8. A pair of electrodes 2 are provided on the substrate 1 so as to be in contact with the layer 3 composed of a resistor. A protective film 4 is provided on the layer 3 composed of a resistor. Fig. 22 The conventional chip resistor shown is disclosed in Patent Document 2, for example.

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2010-118430

[0008] Patent Document 2: Japanese Patent Application Publication No. 2000-106301 Summary of the invention

[0009] In the conventional chip resistor disclosed in Patent Document 1, if high power is to be applied, the layer 3 composed of the resistor element generates more heat, so the temperature of the layer 3 composed of the resistor element becomes high, which causes a problem that the chip resistor cannot handle high power.

[0010] Furthermore, in the conventional chip resistor disclosed in Patent Document 2, since the entire layer 3 composed of the resistor element is buried in the recessed portion, there is a problem that heat is dissipated only at a portion in contact with the substrate 1 including the insulator.

[0011] The purpose of the present disclosure is to solve the above-mentioned conventional problems and provide a chip resistor capable of handling high power.

[0012] In order to solve the above problems, the chip resistor disclosed in the present invention comprises an insulating substrate, a pair of electrodes, and a resistor body. The insulating substrate has a first area in the central portion as viewed from its upper surface, and has a second area at both ends of the first area. A recess is provided in the first area of ​​the insulating substrate. A pair of electrodes are respectively provided at both ends of the upper surface of the insulating substrate. The resistor body is provided in at least the recess of the insulating substrate. The resistor body is connected to the pair of electrodes, respectively. In addition, the resistor body has a trimming groove in the second area of ​​the insulating substrate.

[0013] In the chip resistor of the present disclosure, it is further preferred that the recessed portion has a meandering shape.

[0014] The chip resistor disclosed herein preferably further includes a resistor body provided on the upper surface of the insulating substrate.

[0015] The chip resistor disclosed in the present invention embeds the resistor in a recessed portion, especially a meandering recessed portion, provided in the insulating substrate. Therefore, the contact area between the resistor and the insulating substrate becomes larger. Thus, the heat generated in the resistor can be effectively released to the insulating substrate. As a result, the temperature of the resistor can be reduced. Therefore, the chip resistor has the excellent effect of being able to cope with high power. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a cross-sectional view of the chip resistor in the first embodiment of the present disclosure.

[0017] Figure 2 It is a top view of the chip resistor in the first embodiment.

[0018] Figure 3 It is a cross-sectional view of an insulating substrate having a recessed portion formed therein in the first embodiment.

[0019] Figure 4 FIG. 1 is a top view of an insulating substrate having the recess formed therein.

[0020] Figure 5It is a top view of the insulating substrate when a resistor is provided on the insulating substrate having the recessed portion.

[0021] Figure 6 It is a plan view showing the arrangement relationship between a resistor formed on an insulating substrate and a pair of electrodes in the first embodiment.

[0022] Figure 7 The chip resistor in the first embodiment is Figure 2 An enlarged view of the portion enclosed by area α is shown.

[0023] Figure 8 1 is a cross-sectional view of a region α of the chip resistor in the first embodiment.

[0024] Fig. 9 It is a cross-sectional view of the chip resistor in the second embodiment.

[0025] Fig.10 It is a top view of the chip resistor in the second embodiment.

[0026] Fig.11 It is a cross-sectional view of the chip resistor in the third embodiment.

[0027] Fig.12 It is a top view of the chip resistor in the third embodiment.

[0028] Fig.13 The chip resistor is Fig.12 An enlarged view of the portion enclosed by region β is shown.

[0029] Fig.14 It is a cross-sectional view of the chip resistor in the fourth embodiment.

[0030] Fig.15 It is a top view of the chip resistor in the fourth embodiment.

[0031] Fig.16 It is a cross-sectional view of the chip resistor in the fifth embodiment.

[0032] Fig.17 It is a top view of the chip resistor in the fifth embodiment.

[0033] Fig.18 It is a cross-sectional view of the chip resistor in the sixth embodiment.

[0034] Fig.19 It is a top view of the chip resistor in the sixth embodiment.

[0035] Fig. 20 This is a top view of the main parts of a conventional chip resistor.

[0036] Fig.21 is a cross-sectional view of the chip resistor.

[0037] Fig. 22 is a cross-sectional view of another conventional chip resistor. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present disclosure will be described using the drawings. In addition, the embodiments described below are merely embodiments of the invention according to the present disclosure, and the invention according to the present disclosure is not limited to the embodiments described below.

[0039] (First Embodiment)

[0040] Hereinafter, the chip resistor in the first embodiment of the present disclosure will be described using the drawings. Figure 1 is a cross-sectional view of a chip resistor in the first embodiment of the present disclosure, Figure 2 is a top view of the chip resistor. Figure 1 Yes Figure 2 The chip resistor shown is a cross-sectional view when cut along line II on a plane perpendicular to the paper surface.

[0041] like Figure 1 as well as Figure 2 As shown, the chip resistor in the first embodiment of the present disclosure includes: an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a trimming groove 14, a first protective film 15, and a second protective film 16. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. The resistor 13 is formed on a part of the pair of upper surface electrodes 12 and on the upper surface of the insulating substrate 11, and between the pair of upper surface electrodes 12. The trimming groove 14 is provided in the resistor 13. The first protective film 15 covers the resistor 13. The second protective film 16 covers the first protective film 15.

[0042] In addition, a pair of end surface electrodes 17 are provided on both end surfaces of the insulating substrate 11. The pair of end surface electrodes 17 are electrically connected to the pair of upper surface electrodes 12. In addition, on both end surfaces of the insulating substrate 11, a plating layer 18 is formed on a portion of each of the pair of upper surface electrodes 12 and on each surface of the pair of end surface electrodes 17.

[0043] In addition, in order to avoid cumbersome Figure 2 In the figure, the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 are omitted.

[0044] In addition, the thickness direction of the insulating substrate 11 is set as the Z axis, the surface parallel to the upper surface of the insulating substrate 11 is set as the XY plane, the direction from one direction of a pair of upper surface electrodes 12 to the other direction is set as the X axis, and the direction perpendicular to the X axis is set as the Y axis to define the XYZ orthogonal coordinates. Figure 1 The cross-sectional view shown is through Figure 2 The sectional view is a sectional view when the plane is cut along the II line shown and parallel to the XZ plane. In all the drawings described below, the XYZ orthogonal coordinates are defined as described above.

[0045] In the above structure, the insulating substrate 11 contains aluminum oxide containing 96% of Al2O3. The shape of the insulating substrate 11 is rectangular (rectangular when viewed from above). The insulating substrate 11 is divided into a first region 11a in the center and second regions 11b at both ends of the first region 11a. In addition, a concave portion 20 that is serpentine when viewed from above is provided in the first region 11a. In addition, here, the so-called "viewed from above" refers to looking from the direction toward which the upper surface of the insulating substrate 11 is facing.

[0046] The insulating substrate 11 having the meandering recessed portion 20 formed therein will be described. The insulating substrate 11 has a thickness of 0.4 mm, a length in the X-axis direction of 1.95 mm, and a length in the Y-axis direction of 1.2 mm. Figure 3 It is a cross-sectional view of an insulating substrate in which a recessed portion 20 is formed. Figure 4 It is a plan view of an insulating substrate in which a recessed portion 20 is formed. Figure 3 is through Figure 4 The insulating substrate 11 is shown in a cross-sectional view taken along line III-III and cut along a plane perpendicular to the paper surface.

[0047] The width Xa of the first region 11a in the X-axis direction is Xa=1.02 mm. Figure 4 The width of the second region 11b on the left side is set to Xb1, and the width of the second region 11b on the right side is set to Xb2, then Xb1=0.63mm, Xb2=0.3mm.

[0048] Regarding the recessed portion 20, the recessed portion 20 is formed Figure 4 The recess 20 is located in an area with a width Ya in the Y-axis direction from the left boundary to the right boundary of the first area 11a. The width of the recess 20 is Xa1. The recess 20 extends in the Y-axis direction along the left boundary of the first area 11a, and extends in the X-axis direction when the length of the recess 20 is Ya1. Then, the recess 20 is separated from the recess 20 that previously extended in the Y-axis direction (negative direction of the Y-axis) by an interval Xv, and extends in the Y-axis direction (positive direction of the Y-axis) again. Then, the recess 20 goes back and forth once, and extends in the X-axis direction again when the length of the recess 20 is Ya1. This process is repeated, and the recess 20 extends from Figure 4 The left boundary of the first area 11a reaches the right boundary.

[0049] In the first embodiment, the depth of the recess 20 is 0.01 mm. In addition, regarding the recess 20, Xa1 = 0.15 mm, Ya = 0.8 mm, Ya1 = 0.68 mm, Xv = 0.14 mm. Xa2 = 0.44 mm. In addition, the X-axis direction may be referred to as the long side direction of the insulating substrate hereinafter.

[0050] Furthermore, a pair of upper surface electrodes 12 are provided at both end portions of the upper surface of the second region 11 b of the insulating substrate 11 .

[0051] The pair of upper surface electrodes 12 are formed by printing a thick film material containing a metal such as silver and firing it. In addition, a pair of back surface electrodes (not shown) may be provided at both ends of the back surface of the insulating substrate 11 .

[0052] The resistor 13 is provided between the pair of upper surface electrodes 12 on the upper surface of the insulating substrate 11. The resistor 13 has a thickness of 0.02 mm, a length in the X-axis direction of 1.35 mm, and a length in the Y-axis direction of 0.8 mm.

[0053] The resistor 13 is formed by printing a thick film material containing copper nickel, silver palladium or ruthenium oxide and then firing it. The resistor 13 partially overlaps and connects with the pair of upper surface electrodes 12. The overlapping parts of the resistor 13 and the pair of upper surface electrodes 12 form two. Figure 1 as well as Figure 2 In the embodiment, both ends of the resistor 13 are formed on the upper surfaces of both ends of the pair of upper surface electrodes 12, but may be formed on the lower surfaces of both ends of the pair of upper surface electrodes 12. Current flows through the resistor 13 between the pair of upper surface electrodes 12.

[0054] The resistor 13 is buried in the concave portion 20 in the first region 11a. Therefore, the resistor 13 is formed in a meandering shape, thereby increasing the effective length of the resistor 13 and reducing the potential difference per unit length, thereby improving surge resistance. In addition, since the resistor 13 is buried in the concave portion 20, the resistors 13 are not opposed to each other in the planar direction, and surge resistance is further improved.

[0055] In addition, the resistor 13 is formed on the upper surface of the insulating substrate 11 in the second region 11b. The resistor 13 embedded in the recess 20 is connected to the resistor 13 formed on the upper surface of the insulating substrate 11.

[0056] Next, the insulating substrate 11 in which the resistor 13 is provided on the insulating substrate 11 having the recessed portion 20 will be described below. Figure 5The top view of the insulating substrate 11 is a view of a resistor 13 provided on the insulating substrate 11 having the recess 20 formed therein. In the first region 11a of the insulating substrate 11, the resistor 13 is buried in the recess 20. As for the second region 11b of the insulating substrate 11, the resistor 13 is buried in the recess 20. Figure 5 The length of the resistor 13 extending in the X-axis direction from the second region 11b on the left is denoted as X13b1, and the length of the resistor 13 extending in the X-axis direction from the second region 11b on the right is denoted as X13b2.

[0057] In the first area 11a, Figure 5 The value of the overlap width in the X-axis direction of the resistor 13 extending in the X-axis direction in the second region 11b on the left side and the region where the resistor 13 is buried in the recess 20 is X13a1. Figure 5 The value of the overlapping width in the X-axis direction of the resistor 13 extending in the X-axis direction in the second region 11b on the right side and the region where the resistor 13 is buried in the recess 20 is set to X13a2. In addition, the size of the resistor 13 in the X-axis direction as a whole is set to X13, and the size in the Y-axis direction is set to Y13. In the first embodiment, X13 = 1.35 mm, Y13 = 0.8 mm, X13a1 = 0.08 mm, X13a2 = 0.08 mm, X13b1 = 0.33 mm, and X13b2 = 0.25 mm.

[0058] Next, use Figure 6 The relationship between the resistor 13 formed on the insulating substrate 11 and the pair of upper surface electrodes 12 will be described. Figure 6 It is a top view showing the configuration relationship between the resistor 13 and a pair of upper surface electrodes 12 formed on the insulating substrate 11. The resistor 13 and the pair of upper surface electrodes 12 are partially overlapped and connected. The pair of upper surface electrodes 12 each contain a metal such as silver with a thickness of 0.01 mm. That is, the thickness of each of the pair of electrodes 12 is 0.01 mm. In addition, the pair of upper surface electrodes 12 each have a rectangular shape having sides in the X-axis direction and the Y-axis direction. The lengths of the sides in the Y-axis direction of the pair of upper surface electrodes 12 are the same. The lengths of the respective Y-axis directions of the pair of upper surface electrodes 12 are set to Y12. In addition, regarding the pair of upper surface electrodes 12, Figure 6 The length of one side of the upper surface electrode 12 on the left side of the paper in the X-axis direction is set as X121, Figure 6 The length of one side of the upper surface electrode 12 on the right side of the paper in the X-axis direction is X122. In the first embodiment, X121 = 0.35 mm, X122 = 0.2 mm, X12b1 = 0.1 mm, X12b2 = 0.1 mm, and Y12 = 0.9 mm.

[0059] Furthermore, if Figure 2As shown, the trimming groove 14 is provided in the resistor 13 formed in the second region 11b. It is difficult to adjust the resistance value by forming the trimming groove 14 in the resistor 13 buried in the recess 20. However, it is easy to form the trimming groove 14 in the resistor 13 formed on the upper surface of the insulating substrate 11 in the second region 11b.

[0060] The trimming groove 14 is formed by irradiating the resistor 13 formed on the upper surface of the insulating substrate 11 in the second region 11b with laser. Figure 2 In the embodiment, the trimming groove 14 is L-shaped, but the shape is not limited thereto. In addition, the resistor 13 embedded in the concave portion 20 of the first region 11a and the resistor 13 provided with the trimming groove 14 of the second region 11b are preferably formed into a meandering shape as a whole.

[0061] The first protective film 15 covers the resistor 13 and includes an insulator mainly composed of glass. The first protective film 15 can alleviate the impact caused by the irradiation of the laser when the trimming groove 14 is formed on the resistor 13. After the first protective film 15 is formed on the resistor 13, the laser is irradiated to the first protective film 15 to form the trimming groove 14.

[0062] The second protective film 16 covers the entire first protective film 15 and a portion of the pair of upper surface electrodes 12 , and contains epoxy resin.

[0063] The pair of end surface electrodes 17 are respectively provided on both end surfaces of the insulating substrate 11 and are formed by printing a material containing Ag and resin so as to be electrically connected to the upper surfaces of the pair of upper surface electrodes 12 exposed from the second protective film 16. Alternatively, the end surface electrodes 17 may be formed by sputtering a metal material.

[0064] Furthermore, a plating layer 18 including a Ni plating layer and a Sn plating layer is formed on a part of the pair of upper surface electrodes 12 and the surface of the pair of end surface electrodes 17. At this time, the plating layer 18 is in contact with the second protective film 16. In addition, a Cu plating layer may exist under the Ni plating layer.

[0065] Next, use Figure 7 , Figure 8 The trimming groove 14 will be described. Figure 7 is Figure 2 An enlarged view of a portion surrounded by a region α of the chip resistor is shown. Figure 8 It is along Figure 7 A cross-sectional view taken along line VIII-VIII of the chip resistor shown.

[0066] The trimming groove 14 penetrates the first protective film 15 and the resistor 13 from the surface of the first protective film 15 and reaches the surface of the insulating substrate 11. The trimming groove 14 is filled with the second protective film 16.

[0067] The trimming groove 14 is formed in Figure 2 The second region 11b on the left side has an L-shape along the X-axis direction and along the Y-axis direction. The length of the trimming groove 14 extending in the X-axis direction is X14, and the length extending in the Y-axis direction is Y14. In addition, the width of the trimming groove 14 is W14, and the depth is D14. The trimming groove 14 is spaced from the first region 11a to the left side. Figure 2 The distance from the boundary of the second region 11b on the left side is set as Xb14. In addition, the trimming groove 14 extends beyond the resistor 13 along the Y-axis direction. The length of the trimming groove 14 extending beyond the resistor 13 is set as Yb14. In the first embodiment, W14=0.03mm, D14=0.02mm, Xb14=0.6mm, and Yb14=0.05mm.

[0068] As described above, in the first embodiment, the resistor 13 is embedded in the meandering recess 20 provided in the insulating substrate 11, so that the contact area between the resistor 13 and the insulating substrate 11 becomes larger. As a result, the heat generated in the resistor 13 can be effectively released to the insulating substrate 11. As a result, the temperature of the resistor 13 can be reduced, so that the effect of being able to cope with high power can be obtained. That is, a high-power chip resistor can be obtained.

[0069] (Second Embodiment)

[0070] Hereinafter, a chip resistor according to a second embodiment of the present disclosure will be described with reference to the drawings. Fig. 9 is a cross-sectional view of a chip resistor according to a second embodiment, Fig.10 is a top view of the chip resistor. Fig. 9 Yes Fig.10 The cross-sectional view of the chip resistor shown is when it is cut along the IX-IX line on a plane perpendicular to the paper surface. Fig.10 In order to avoid cumbersomeness, the first protective film 15, the second protective film 16, the pair of end surface electrodes 17 and the plating layer 18 are omitted. Fig. 9 As shown, compared with the chip resistor involved in the first embodiment, a resistor 13 is further provided on the upper surface of the insulating substrate 11 and the upper surface of the resistor 13 buried in the recess 20. At this time, the resistor 13 buried in the recess 20 and the resistor 13 above are formed integrally. In addition, the size and material of each element in the chip resistor involved in the second embodiment are the same as those of the chip resistor involved in the first embodiment.

[0071] This structure further increases the contact area between the resistor 13 and the insulating substrate 11 . As a result, the heat generated in the resistor 13 can be effectively released through the insulating substrate 11 .

[0072] The recess 20 need not necessarily be formed in a meandering shape in plan view, but may be formed in a portion of the first region 11a and a portion of the meandering resistor 13 may be buried in the recess 20. In this case, the contact area between the resistor 13 and the insulating substrate 11 is also increased.

[0073] (Third Embodiment)

[0074] Below, refer to Fig.11 as well as Fig.12 , a chip resistor in a third embodiment of the present disclosure is described.

[0075] Fig.11 is a cross-sectional view of a chip resistor in a third embodiment of the present disclosure, Fig.12 is a top view of the chip resistor. Fig.11 is along the way Fig.12 The cross-sectional view of the chip resistor shown is when it is cut along the XI-XI line and parallel to the XZ plane. Fig.12 In order to avoid complexity, illustration of the first protective film 15, the second protective film 16, the end surface electrode 17, and the plating layer 18 is omitted.

[0076] exist Fig.11 as well as Fig.12 In the embodiment, a recess 20 is provided in the central portion of the upper surface of the insulating substrate 11. In the insulating substrate 11, the region where the recess 20 is provided is the first region 11a, and the two adjacent regions of the recess 20 are the second region 11b. That is, the edge of the recess 20 is the boundary between the first region 11a and the second region 11b. A pair of upper surface electrodes 12 are provided at both ends of the upper surface of the insulating substrate 11. In addition, a resistor 13 is provided between the pair of upper surface electrodes 12 on the upper surface of the insulating substrate 11. A first trimming groove 14a is provided on the first region 11a of the resistor 13. In addition, a second trimming groove 14b is provided on the second region 11b. In addition, a first protective film 15 is provided so as to cover the resistor 13. Further, a second protective film 16 is provided so as to cover the first protective film 15.

[0077] The chip resistor includes a pair of end surface electrodes 17 provided on both end surfaces of the insulating substrate 11 so as to be electrically connected to the pair of upper surface electrodes 12 , and a plating layer 18 formed on a part of the pair of upper surface electrodes 12 and on the surfaces of the pair of end surface electrodes 17 .

[0078] In the above structure, the insulating substrate 11 is made of aluminum oxide containing 96% of Al2O3 and has a rectangular shape (rectangular in plan view). The insulating substrate 11 has a recess 20 provided therein.

[0079] A pair of upper surface electrodes 12 are provided at both ends of the upper surface of the insulating substrate 11 and are formed by printing and firing a thick film material containing a metal such as silver. A pair of lower surface electrodes 17 b are provided at both ends of the lower surface of the insulating substrate 11 .

[0080] Furthermore, the resistor 13 is formed by printing a thick film material including copper nickel, silver palladium or ruthenium oxide on the upper surface of the insulating substrate 11 between the pair of upper surface electrodes 12 and then firing it, and is connected to the pair of upper surface electrodes 12. Fig.11 In the embodiment, both ends of the resistor 13 are formed on the upper surfaces of both ends of the pair of upper surface electrodes 12, but may be formed on the lower surfaces of both ends of the pair of upper surface electrodes 12. Current flows through the resistor 13 between the pair of upper surface electrodes 12.

[0081] A portion of the resistor 13 is buried in the recess 20 .

[0082] Next, use Fig.13 The first trimming grooves 14a and 14b will be described. Fig.13 is Fig.12 An enlarged view of a portion surrounded by a region β of the chip resistor is shown.

[0083] The first trimming groove 14a penetrates the first protective film 15 and the resistor 13 from the surface of the first protective film 15 in the first region 11a to reach the surface of the insulating substrate 11 where the recess 20 is formed. The second protective film 16 is filled inside the first trimming groove 14a.

[0084] The second trimming groove 14b is Fig.12 The second region 11b on the left side of the first protective film 15 penetrates the first protective film 15 and the resistor 13 from the surface of the first protective film 15 to reach the surface of the insulating substrate 11. The second protective film 16 is filled in the second trimming groove 14b.

[0085] The first trimming groove 14a is formed at Fig.11 The first region 11a shown in FIG. 1 has an L-shape extending in the X-axis direction and in the Y-axis direction. The length of the first trimming groove 14a extending in the X-axis direction is X14a, and the length of the first trimming groove 14a extending in the Y-axis direction is Y14a. In addition, the width of the first trimming groove 14a is W14a, and the depth is D14a. The distance between the first trimming groove 14a and the first region 11a is Fig.12The distance from the boundary of the second area 11b on the right side is set as Xa14a. In addition, the first trimming groove 14a extends beyond the resistor 13 along the Y-axis direction. The length of the trimming groove 14 extending beyond the resistor 13 is set as Ya14a. In the third embodiment, W14a=0.03mm, D14a=0.02mm, X14a=0.05mm, Y14a=0.4mm, Xb14a=0.3mm, and Yb14a=0.05mm.

[0086] The second trimming groove 14b is formed at Fig.12 The second region 11b on the left side has an L-shape extending in the X-axis direction and in the Y-axis direction. The length of the second trimming groove 14b extending in the X-axis direction is X14b, and the length extending in the Y-axis direction is Y14b. In addition, the width of the second trimming groove 14b is W14b, and the depth is D14b. The distance between the second trimming groove 14b and the first region 11a is Fig.12 The distance from the boundary of the second area 11b on the left side is set as Xb14b. In addition, the second trimming groove 14b extends beyond the resistor 13 along the Y-axis direction. The length of the trimming groove 14 extending beyond the resistor 13 is set as Yb14b. In the third embodiment, W14b=0.03mm, D14b=0.01mm, X14b=0.05mm, Y14b=0.3mm, Xb14b=0.05mm, Yb14b=0.05mm. In addition, the length of the first trimming groove 14a provided in the meandering resistor body portion 13b in the short side direction of the insulating substrate 11 is greater than the length of the second trimming groove 14b provided in the rectangular resistor body portion 13c on the upper surface of the insulating substrate 11 in the short side direction of the insulating substrate 11. Through this structure, since the current is concentrated in the meandering resistor body portion 13b with large heat dissipation, it has the effect of being able to cope with high power.

[0087] The first trimming groove 14a and the second trimming groove 14b are formed by irradiating the resistor 13 formed on the upper surface of the insulating substrate 11 with laser. Fig.12 In the embodiment, the first trimming groove 14 a and the second trimming groove 14 b have an L-shape, but the shape is not limited thereto.

[0088] The first protective film 15 covers the resistor 13. The first protective film 15 includes an insulator mainly composed of glass. The first protective film 15 can alleviate the impact caused by the irradiation of the laser when forming the first trimming groove 14a and the second trimming groove 14b. After the first protective film 15 is formed on the resistor 13, the first protective film 15 is irradiated with laser to form the first trimming groove 14a and the second trimming groove 14b.

[0089] The second protective film 16 includes epoxy resin so as to cover the entire first protective film 15 and a portion of the pair of upper surface electrodes 12. A pair of end surface electrodes 17 are provided on both end surfaces of the insulating substrate 11 and are formed by printing a material including Ag and resin so as to be electrically connected to the upper surfaces of the pair of upper surface electrodes 12 exposed from the second protective film 16. Alternatively, the end surface electrodes 17 may be formed by sputtering a metal material.

[0090] Furthermore, a plating layer 18 including a Ni plating layer and a Sn plating layer is formed on a part of the pair of upper surface electrodes 12 and the surface of the pair of end surface electrodes 17. At this time, the plating layer 18 is in contact with the second protective film 16. In addition, a Cu plating layer may exist under the Ni plating layer.

[0091] As described above, in the third embodiment, a part of the resistor 13 is buried in the recess 20 provided in the insulating substrate 11, the first trimming groove 14a is formed in the meandering resistor portion 13b, and the second trimming groove 14b is formed in the rectangular resistor portion 13c provided on the upper surface of the insulating substrate 11. Therefore, after the resistance value is greatly changed by the first trimming groove 14a, the resistance value can be adjusted with high accuracy by the second trimming groove 14b, and as a result, there is an effect that the resistance value accuracy can be improved.

[0092] (Fourth Embodiment)

[0093] Hereinafter, a chip resistor in a fourth embodiment of the present disclosure will be described using the drawings. Fig.14 : is a cross-sectional view showing a chip resistor in a fourth embodiment of the present disclosure, Fig.15 A top view of the chip resistor is shown in FIG. Fig.14 Yes Fig.15 The chip resistor shown is a cross-sectional view when it is cut along the XIV-XIV line on a plane perpendicular to the paper surface. Fig.15 In order to avoid complexity, illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted.

[0094] The chip resistor according to the fourth embodiment includes an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a first protective film 15, a second protective film 16, a pair of end surface electrodes 17, and a plating layer 18. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. In addition, a plurality of strip-shaped recesses 20 are provided on the upper surface of the insulating substrate 11. The resistor 13 is buried in the recess 20 of the insulating substrate 11, and the resistor 13 is provided so as to cover the top of the recess 20. The resistor 13 is respectively in contact with the pair of upper surface electrodes 12 and is electrically connected to the pair of upper surface electrodes 12. The first protective film 15 and the second protective film 16 are provided on the resistor 13. Between the recesses 20, a trimming groove 14 is provided that reaches the insulating substrate 11 from the surface of the first protective film 15. The trimming groove 14 is filled with the second protective film 16. In addition, a pair of end surface electrodes 17 are provided on the outer side surface in the long side direction of the insulating substrate 11. The pair of end surface electrodes 17 are respectively connected to the pair of upper surface electrodes 12 and are electrically connected. A plating layer 18 is provided on each surface of the pair of end surface electrodes 17. The dimensions and materials of each element in the chip resistor involved in the fourth embodiment are the same as those of the chip resistor involved in the first embodiment.

[0095] The chip resistor according to the present embodiment has improved heat dissipation by increasing the contact area between the substrate having good heat dissipation and the resistor body, thereby achieving higher power of the chip resistor.

[0096] (Fifth Embodiment)

[0097] Hereinafter, the chip resistor in the fifth embodiment of the present disclosure will be described using the drawings. Fig.16 A cross-sectional view of a chip resistor in a fifth embodiment of the present disclosure is shown in FIG. Fig.17 A top view of the chip resistor is shown in FIG. Fig.16 Yes Fig.17 The chip resistor shown is a cross-sectional view when it is cut along the XVI-XVI line on a plane perpendicular to the paper surface. Fig.17 In order to avoid complexity, illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted.

[0098] The chip resistor according to the fifth embodiment includes an insulating substrate 11, a resistor 13, a pair of upper surface electrodes 12, a first protective film 15, a second protective film 16, a pair of end surface electrodes 17, and a plating layer 18. The resistor 13 is provided on the upper surface of the insulating substrate 11. The pair of upper surface electrodes 12 are provided at both ends of the upper surface of the insulating substrate 11, and are electrically connected to the resistor 13. The insulating substrate 11 has a first region 11a in the central portion thereof and a second region 11b at both ends of the first region 11a. A recess 20 having a meandering shape in a plan view is provided in the first region 11a of the insulating substrate 11. The resistor 13 is buried in the recess 20. The resistor 13 includes a shape substantially the same as the recess 20 formed in the first region 11a. A trimming groove 14 is provided in the resistor 13 formed in the second region 11b. The trimming groove 14 is filled with the second protective film 16. In addition, a pair of end surface electrodes 17 are provided on the outer side surface in the long side direction of the insulating substrate 11. The pair of end surface electrodes 17 are respectively connected to the pair of upper surface electrodes 12 and are electrically connected. A plating layer 18 is provided on the surface of each of the pair of end surface electrodes 17. The dimensions and materials of each element in the chip resistor involved in the fifth embodiment are the same as those of the chip resistor involved in the first embodiment.

[0099] According to the chip resistor of the fifth embodiment, the contact area with the substrate having good heat dissipation properties is increased, so the heat dissipation properties of the chip resistor are improved. Therefore, the chip resistor can achieve higher power.

[0100] (Sixth Embodiment)

[0101] Hereinafter, a chip resistor in a sixth embodiment of the present disclosure will be described using the drawings. Fig.18 : is a cross-sectional view of a chip resistor in a sixth embodiment of the present disclosure, Fig.19 A top view of the chip resistor is shown in FIG. Fig.18 Yes Fig.19 The chip resistor shown is a cross-sectional view when cut along the XVIII-XVIII line on a plane perpendicular to the paper surface. Fig.19 In order to avoid complexity, illustration of the first protective film 15, the second protective film 16, the pair of end surface electrodes 17, and the plating layer 18 is omitted.

[0102] The chip resistor according to the sixth embodiment includes: an insulating substrate 11, a pair of upper surface electrodes 12, a resistor 13, a first protective film 15, a second protective film 16, a pair of end surface electrodes 17, and a plating layer 18. The pair of upper surface electrodes 12 are respectively provided at both ends of the upper surface of the insulating substrate 11. The resistor 13 is in contact with the pair of upper surface electrodes 12 and is electrically connected to the upper surface electrodes 12. In addition, the resistor 13 has a trimming groove 14. The first protective film 15 and the second protective film 16 are formed on the upper surface of the insulating substrate 11 so as to cover at least the resistor 13. A pair of end surface electrodes 17 are provided on the outer side surfaces of the first protective film 15 and the insulating substrate 11 in the long side direction. The plating layer 18 is provided on the surface of each of the pair of end surface electrodes 17.

[0103] In addition, a recess 20 is provided on the upper surface of the insulating substrate 11, and a hot spot 19 is provided in the recess 20. The hot spot 19 is a portion (current concentration portion) where the current is concentrated in the resistor 13. In addition, the dimensions and materials of each element in the chip resistor involved in the sixth embodiment are the same as those of the chip resistor involved in the first embodiment.

[0104] According to the sixth embodiment, the contact area between the hot spot portion 19 and the substrate having high heat dissipation properties can be increased, thereby achieving higher power of the chip resistor.

[0105] (Implementation Method)

[0106] Hereinafter, embodiments of the chip resistor of the present disclosure will be described.

[0107] (First method)

[0108] The chip resistor involved in the first mode of the present disclosure comprises an insulating substrate (11), a pair of electrodes (12), and a resistor (13). The insulating substrate (11) has a first area (11a) in the central part as seen from its upper surface, and has a second area (11b) at both ends of the first area (11a). A recess (20) is provided in the first area (11a) of the insulating substrate (11). A pair of electrodes are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is provided in at least the recess (20) of the insulating substrate (11). The resistor (13) is connected to the pair of electrodes (12), respectively. In addition, the resistor (13) has a trimming groove (14) in the second area (11b) of the insulating substrate (11).

[0109] (Second method)

[0110] The chip resistor according to the second aspect of the present disclosure is characterized in that in the first aspect, the recess (20) has a meandering shape.

[0111] (Third Method)

[0112] The chip resistor according to the third aspect of the present disclosure is characterized in that, in the first aspect, a resistor (13) is further provided on the upper surface of the insulating substrate (11).

[0113] (Fourth Method)

[0114] The chip resistor involved in the fourth embodiment of the present disclosure comprises an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a protective layer, an end surface electrode (17), and a lower surface electrode. The insulating substrate (11) has a rectangular shape. The insulating substrate (11) is provided with a recess (20) on its upper surface. The pair of upper surface electrodes (12) are provided on the upper surface of the insulating substrate (11). The resistor (13) is provided on the upper surface of the insulating substrate (11) and in the recess (20). The resistor (13) is electrically connected to the pair of upper surface electrodes (12). In addition, the resistor (13) has a single or multiple trimming grooves (14). The protective layer is provided on the upper surface of the insulating substrate (11) and at least covers the resistor (13). The end surface electrode (17) is provided on the outer side surface of the insulating substrate (11) in the long side direction. In addition, the end surface electrode (17) is electrically connected to one of the upper surface electrodes (12). The lower surface electrode (17b) is provided on the lower surface of the insulating substrate (11). In addition, the lower surface electrode (17b) is electrically connected to the end surface electrode (17).

[0115] (Fifth Method)

[0116] The chip resistor involved in the fifth embodiment of the present disclosure is characterized in that, in the fourth embodiment, the plurality of trimming grooves (14) include a first trimming groove (14a) and a second trimming groove (14b). The first trimming groove (14a) is arranged on the recess (20). The second trimming groove (14b) is arranged at a position on the insulating substrate (11) different from the recess (20). The length of the first trimming groove (14a) in the short side direction of the insulating substrate (11) is greater than the length of the second trimming groove (14b) in the short side direction of the insulating substrate (11).

[0117] (Sixth Method)

[0118] The chip resistor involved in the sixth embodiment of the present disclosure comprises an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a first protective film (15), a second protective film (16), and an end surface electrode (17). The insulating substrate (11) has a rectangular shape. The insulating substrate (11) is provided with a plurality of strip-shaped recesses (20) on its upper surface. The pair of upper surface electrodes (12) are respectively provided at the two ends of the upper surface of the insulating substrate (11). The resistor (13) is provided on at least the recess (20) of the insulating substrate (11). The resistor (13) is electrically connected to the pair of upper surface electrodes (12), respectively. The first protective film (15) is provided on the upper surface of the resistor (13). The end surface electrode (17) is provided from the outer side surface in the long side direction of the insulating substrate (11) to the lower surface. In addition, the end surface electrode (17) is electrically connected to the upper surface electrode (12). A trimming groove (14) is formed in the resistor (13) and the first protective film (15). The trimming groove (14) is formed as a band-shaped recessed portion (20) extending from the upper surface of the first protective film (15) to the insulating substrate (11). A second protective film (16) is provided on the first protective film (15). The trimming groove (14) is filled with the second protective film (16).

[0119] (Seventh Method)

[0120] The chip resistor involved in the seventh embodiment of the present disclosure comprises an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a first protective film (15), a second protective film (1), and an end surface electrode (17). The insulating substrate (11) is provided with a meandering recess (20) on its upper surface. The pair of upper surface electrodes (12) are respectively provided at the two ends of the upper surface of the insulating substrate (11). The resistor (13) is buried in at least the meandering recess (20) of the insulating substrate (11). The resistor (13) has a meandering resistor portion (13b) and a pair of rectangular resistor portions (13c). The meandering resistor portion (13b) is buried in the meandering recess (20). A pair of rectangular resistor portions (13c) are provided on the upper surface of the insulating substrate (11). A pair of rectangular resistor portions (13c) are respectively arranged at the two ends of the meandering resistor portion (13b). A pair of rectangular-shaped resistor portions (13c) are electrically connected to a pair of upper surface electrodes (12) respectively. A first protective film (15) is provided on the upper surface of the resistor (13). An end surface electrode (17) is provided extending from the outer side surface in the long side direction of the insulating substrate (11) to the lower surface. In addition, the end surface electrode (17) is electrically connected to one of the upper surface electrodes (12). A trimming groove (14) is formed in the resistor (13) and the first protective film (15). The trimming groove (14) is formed to reach the recess (20) in the insulating substrate (11) from the upper surface of the first protective film (15) via the rectangular-shaped resistor portion (13c). A second protective film (16) is provided on the first protective film (15). The second protective film (16) is filled in the trimming groove (14).

[0121] (Eighth Method)

[0122] The chip resistor involved in the eighth embodiment of the present disclosure comprises an insulating substrate (11), a pair of upper surface electrodes (12), a resistor (13), a protective film (15, 16), and an end surface electrode (17). A recess (20) is provided on the upper surface of the insulating substrate (11). The resistor (13) is provided on the upper surface of the insulating substrate (11). A pair of upper surface electrodes (12) are respectively provided at both ends of the upper surface of the insulating substrate (11). The resistor (13) is provided on the insulating substrate (11). The resistor (13) is electrically connected to the pair of upper surface electrodes (12), respectively. In addition, the resistor (13) has a trimming groove (14). The protective film (15, 16) is provided to at least cover the resistor (13) on the upper surface of the insulating substrate (11). The recess (20) provided on the upper surface of the insulating substrate (11) is arranged in a current concentration portion (19) near the trimming groove (14).

[0123] Industrial Applicability

[0124] The chip resistor according to the present disclosure has an effect of being able to cope with high power, and is particularly useful in high-power chip resistors formed of thick-film resistor elements used in various electronic devices.

[0125] The chip resistor disclosed herein has the effect of providing a chip resistor that can adjust the resistance value with high precision and can handle high power, and is particularly useful in chip resistors composed of thick film resistors used in various electronic devices.

[0126] -Explanation of symbols-

[0127] 11 Insulation substrate

[0128] 11a First Area

[0129] 11b Second Area

[0130] 12 Upper surface electrode

[0131] 13 Resistor

[0132] 13b Meandering resistor body

[0133] 13c Rectangular resistor body

[0134] 14 Trimming groove

[0135] 14a First trimming groove

[0136] 14b Second trimming groove

[0137] 15. First protective film

[0138] 16 Second protective film

[0139] 17 End electrode

[0140] 17b Lower surface electrode

[0141] 18 Plating layer

[0142] 19 Hot Spots

[0143] 20 recess.

Claims

1. A chip resistor having: An insulating substrate of rectangular shape having a recessed portion on its upper surface; a pair of upper surface electrodes, disposed on the upper surface of the insulating substrate; a resistor, which is disposed on the insulating substrate, is electrically connected to the pair of upper surface electrodes and has a trimming groove; A protective layer is provided on the upper surface of the insulating substrate so as to at least cover the resistor; an end surface electrode provided on an outer side surface in a long-side direction of the insulating substrate and electrically connected to the upper surface electrode; and a lower surface electrode, which is disposed on the lower surface of the insulating substrate and is electrically connected to the end surface electrode; The resistor is provided on both the upper surface of the insulating substrate and the embedded portion embedded in the recessed portion. The length of the first trimming groove provided in the resistor provided in the embedded portion in the short side direction of the insulating substrate is greater than the length of the second trimming groove provided in the resistor provided on the upper surface of the insulating substrate in the short side direction of the insulating substrate.

2. The chip resistor according to claim 1, wherein: The concave portion is in a serpentine shape.

3. The chip resistor according to claim 1, wherein the protective layer comprises: A first protective film is provided on the upper surface of the resistor; and a second protective film filled with the trimming groove provided between the upper surface of the first protective film and the strip-shaped recessed portion in the insulating substrate; The end surface electrodes are provided from the outer side surfaces in the longitudinal direction of the insulating substrate to the lower surface.

4. The chip resistor according to claim 1, wherein The recessed portion is located on the upper surface of the insulating substrate in a current concentration portion near the trimming groove provided in the resistor.

5. A chip resistor having: An insulating substrate having a serpentine-shaped recessed portion disposed on an upper surface thereof; a pair of upper surface electrodes, disposed at both ends of the upper surface of the insulating substrate; The resistor comprises: a meander-shaped resistor portion buried in the meander-shaped recess in the insulating substrate, and a pair of rectangular parallelepiped resistor portions provided at both ends of the meander-shaped resistor portion, the pair of rectangular parallelepiped resistor portions being electrically connected to the pair of upper surface electrodes respectively; A first protective film is provided on the upper surface of the resistor; and The end surface electrode is provided from the outer side surface in the long side direction of the insulating substrate to the lower surface and is electrically connected to the upper surface electrode. The chip resistor is configured such that a trimming groove is provided in the recessed portion of the insulating substrate from the upper surface of the first protective film through the rectangular parallelepiped resistor portion in the resistor element, and the trimming groove is filled with a second protective film.

6. The chip resistor according to claim 5, comprising: The insulating substrate has a first region in the center thereof and second regions at both ends of the first region, and the recess is provided in the first region of the insulating substrate. At least a portion of the resistor formed in the first region is buried in the recess. The trimming groove is provided in the resistor formed in the second region.

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