Layout design method, system and device, circuit layout and storage medium

Abstract

Provided are a layout design method, system and device, circuit layout and storage medium. The layout design method includes: recording characteristic parameters of transistors in a circuit, the characteristic parameters including the type of transistor, the signal transmitted to each pole of the transistor and the unit device width of the transistor; grouping transistors according to the unit device width of the transistor; matching transistors in each group according to the type of transistor in each group and the signal configured to be transmitted to each pole of the transistor to form multiple layout groups; and stacking some transistors in multiple layout groups according to the electrical connection relationship of the transistors in the circuit and the electrical connection relationship between the transistors and the signal lines, and connecting the transistors in multiple layout groups to form a complete layout corresponding to the circuit. The layout design method provided by the present disclosure can improve the efficiency of circuit layout design, avoid redundant metal routing design as much as possible, and save circuit layout space.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a layout design method, system and device, circuit layout and storage medium. Background Art

[0002] With the development of the semiconductor industry, the density of transistors in integrated circuits has gradually increased. For advanced process integrated circuits, the demand for higher gate density has become very urgent. Complementary Field Effect Transistor (CFET) with buried power rail (BPR) can achieve higher gate density and smaller unit height. Summary of the invention

[0003] Embodiments of the present disclosure provide a layout design method, system and device, circuit layout and storage medium.

[0004] An embodiment of the present disclosure provides a layout design method, which includes: recording characteristic parameters of multiple transistors in a circuit, wherein each transistor includes at least two poles, and the characteristic parameters include at least the type of the multiple transistors, a signal configured to be transmitted to each pole of each transistor, and a unit device width of each transistor; grouping the multiple transistors according to the unit device width of the multiple transistors, each group including at least two transistors; matching the transistors in each group according to the type of the transistors in each group and the signal transmitted to each pole of each transistor to form a plurality of layout groups; stacking at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups according to the electrical connection relationship between the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal line, and connecting the transistors in the plurality of layout groups to form a complete layout corresponding to the circuit.

[0005] An embodiment of the present disclosure provides a circuit layout, which includes a circuit layout designed using any of the above-mentioned layout design methods.

[0006] An embodiment of the present disclosure provides a layout design system, which includes: a recording unit, configured to record characteristic parameters of multiple transistors in a circuit, wherein each transistor includes at least two poles, and the characteristic parameters include at least the type of the multiple transistors, a signal configured to be transmitted to each pole of each transistor, and a unit device width of each transistor; a division unit, configured to group the multiple transistors according to the unit device width of the multiple transistors, each group including at least two transistors; a matching unit, configured to match the transistors in each group according to the type of the transistors in each group and the signal transmitted to each pole of each transistor to form a plurality of layout groups; a connection unit, configured to stack at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups according to the electrical connection relationship between the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal line, and connect the transistors in the plurality of layout groups to form a complete layout corresponding to the circuit.

[0007] The present disclosure provides a layout design device, which includes: a processor; and a memory. The memory stores a computer executable code, and when the computer executable code is run by the processor, any of the above layout design methods is executed.

[0008] An embodiment of the present disclosure provides a storage medium having executable code stored thereon. When the executable code is executed by a processor, the processor executes any of the above-mentioned layout design methods.

[0009] The layout design method provided by the embodiment of the present disclosure can improve the efficiency of complementary field effect transistor (CFET) integrated circuit layout design and effectively reduce the CFET layout area; at the same time, the circuit layout designed by the layout design method fully utilizes the structural characteristics of at least one of the shared gate, source and drain in the CFET, which can avoid redundant metal routing design as much as possible and save circuit layout space.

[0010] The circuit layout provided by the embodiment of the present disclosure has the characteristics of compact arrangement and avoidance of redundant metal routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0012] Figure 1 A step diagram of a layout design method provided according to at least one embodiment of the present disclosure;

[0013] Figure 2 for Figure 1 A diagram showing steps of a layout design method as an example of the layout design method;

[0014] Figure 3 for Figure 1 Flowchart of step S102 and step S103 of the layout design method shown;

[0015] Figure 4A A layout of a first type transistor provided for at least one embodiment of the present disclosure;

[0016] Figure 4B A layout of a second type transistor provided for at least one embodiment of the present disclosure;

[0017] Figure 4C For the general Figure 4A The first type transistor is shown with Figure 4B A layout of a complementary field effect transistor formed by stacking the second type transistors shown;

[0018] Figure 5 A layout of another complementary field effect transistor provided according to at least one embodiment of the present disclosure;

[0019] FIG. 6A to FIG. 6C Schematic diagrams of three different layout groups are shown respectively;

[0020] Fig. 7A A schematic diagram of a layout group provided for an example according to at least one embodiment of the present disclosure;

[0021] Figure 7B A schematic diagram of another layout group provided for an example according to at least one embodiment of the present disclosure;

[0022] Figure 7C for Fig. 7A and Figure 7B The schematic diagram of the layout after the layout group is stacked;

[0023] Figure 8 An XOR gate (XOR2) circuit provided according to at least one disclosed embodiment;

[0024] Fig. 9 and Fig.10 for Figure 8 The circuit shown is a schematic diagram of a pairing of a first type transistor and a second type transistor;

[0025] Fig.11 for Figure 8 Schematic diagrams of multiple layout groups in the circuit shown;

[0026] Fig.12 Based on Figure 8 The circuit shown is Fig.11 A schematic diagram of the arrangement of the plurality of layout groups shown;

[0027] Fig.13 for Figure 8 Complementary Field Effect Transistor (CFET) layout of the circuit shown;

[0028] Fig.14 A Radix 8Booth Multiplexer circuit provided according to at least one embodiment of the present disclosure;

[0029] Fig.15 The circuit shown is a schematic diagram of a pairing of a first type transistor and a second type transistor;

[0030] Fig.16 for Fig.14 Schematic diagrams of multiple layout groups in the circuit shown;

[0031] Fig.17 Based on Fig.14 The circuit shown is Fig.16 A schematic diagram of the arrangement of the plurality of layout groups shown;

[0032] Fig.18 for Fig.14 Complementary Field Effect Transistor (CFET) layout of the circuit shown;

[0033] Fig.19 is a schematic block diagram of a layout design system according to at least one embodiment of the present disclosure;

[0034] Fig. 20 is a schematic block diagram of a layout design device according to at least one embodiment of the present disclosure;

[0035] Fig.21 is a schematic block diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0038] During the research, the inventors of this application found that the vertical stacking (also called vertical stacking) of P-type transistors and N-type transistors in a complementary field effect transistor (CFET) makes the integrated circuit layout per unit area complicated. It will take more time to design a complementary metal oxide semiconductor (CMOS) integrated circuit layout based on CFET using conventional planar layout design methods. At the same time, redundant dummy gates may be difficult to detect, resulting in additional area waste in layout design.

[0039] Different from traditional transistors, complementary field effect transistors, as a cutting-edge transistor, have the characteristics of vertical (up and down) stacking of P-type transistors and N-type transistors and sharing at least one of a gate, a source and a drain.

[0040] The embodiments of the present disclosure provide a layout design method, system and device, circuit layout and storage medium. The layout design method provided by the embodiments of the present disclosure includes: recording characteristic parameters of multiple transistors in a circuit, wherein each transistor includes at least two poles, and the characteristic parameters include at least the types of multiple transistors, the signals configured to be transmitted to each pole of each transistor, and the unit device width of each transistor; grouping multiple transistors according to the unit device width of multiple transistors, each group including at least two transistors; matching the transistors in each group according to the types of transistors in each group and the signals configured to be transmitted to each pole of each transistor to form multiple layout groups; and stacking at least part of the structures of at least part of the transistors in the multiple layout groups according to the electrical connection relationship of the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal line, and connecting the transistors in the multiple layout groups to form a complete layout corresponding to the circuit. The layout design method provided by the embodiment of the present disclosure can improve the efficiency of complementary field effect transistor (CFET) integrated circuit layout design and effectively reduce the CFET layout area; at the same time, the circuit layout designed by the layout design method fully utilizes the structural characteristics of at least one of the shared gate, source and drain in the CFET, which can avoid redundant metal routing design as much as possible and save circuit layout space.

[0041] The following describes the layout design method, system and device, circuit layout and storage medium provided by the embodiments of the present disclosure in conjunction with the accompanying drawings.

[0042] Figure 1 A step diagram of a layout design method provided according to at least one embodiment of the present disclosure, Figure 2 for Figure 1 A diagram showing a step of a layout design method as an example of a layout design method shown in FIG. Figure 3 for Figure 1 Flowchart of step S102 and step S103 of the layout design method shown.

[0043] like Figure 1 As shown, the layout design method provided by the embodiment of the present disclosure includes:

[0044] S101: Record characteristic parameters of multiple transistors in a circuit, wherein each transistor includes at least two poles, and the characteristic parameters include at least types of the multiple transistors, signals configured to be transmitted to each pole of each transistor, and a unit device width of each transistor.

[0045] For example, Figure 2 As shown, step 1 includes: recording characteristic information of all transistors in the circuit and connection information of their sources, drains and gates.

[0046] For example, the characteristic information may include the type of transistor. For example, the characteristic parameters of the transistor may include the characteristic information of the transistor, such as the type of transistor, the signal configured to be transmitted to each electrode of each transistor, and the unit device width of each transistor.

[0047] For example, the types of the plurality of transistors include a first type transistor and a second type transistor. For example, one of the first type transistor and the second type transistor is a P-type transistor, and the other is an N-type transistor. For example, the transistor may be a field effect transistor.

[0048] For example, each transistor includes three electrodes, such as a gate, a first electrode, and a second electrode. For example, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; the first electrode is schematically used as a drain electrode and the second electrode is used as a source electrode in the embodiment of the present disclosure, but it is not limited thereto, and the first electrode and the second electrode of the transistor can be interchangeable.

[0049] For example, the signals configured to be transmitted to each electrode of each transistor may include a gate signal transmitted to the gate of the transistor, a source signal transmitted to the source of the transistor, and a drain signal transmitted to the drain of the transistor.

[0050] Figure 4A A layout of a first type transistor provided for at least one embodiment of the present disclosure, Figure 4B A layout of a second type transistor provided for at least one embodiment of the present disclosure, Figure 4C For the general Figure 4A The first type transistor is shown with Figure 4B A layout of a complementary field effect transistor formed by stacking the second type transistors shown; Figure 5 A layout of another complementary field effect transistor provided according to at least one embodiment of the present disclosure.

[0051] For example, Figures 1 to 5 As shown, the transistor may be a multi-finger transistor, and the number of fingers of the transistor represents the multiple of the unit device width of each transistor, and the unit device width is generally the active area width of a single transistor. For example, the number of fingers of the transistor may refer to the total active area width of the transistor as a multiple of the unit width. For example, Figure 4C The transistor shown is a transistor with a unit device width of 1. If the active area of ​​the transistor is one unit width, one unit width can be regarded as one transistor in layout design. For example, Figure 5The transistor shown is a transistor with a unit device width of 2, including index F1 and index F2. For example, a transistor with a unit device width of 2 can be composed of two separate and identical transistors with a unit device width of 1 connected in parallel; for example, the active area of ​​a transistor with a unit device width of 2 is twice the unit width. The embodiment of the present disclosure schematically shows transistors with a unit device width of 1 and a unit device width of 2, but is not limited thereto. The embodiment of the present disclosure may also include transistors with a unit device width of 3 or more.

[0052] like Figure 1 As shown, the layout design method provided by the embodiment of the present disclosure also includes:

[0053] S102: Grouping the plurality of transistors according to unit device widths of the plurality of transistors, wherein each group includes at least two transistors.

[0054] For example, transistors with the same unit device width may be grouped together, for example, transistors with a unit device width of 1 may be grouped together as a first group, transistors with a unit device width of 2 may be grouped together as a second group, and so on.

[0055] For example, each group includes a plurality of transistors. For example, each group includes at least one first type transistor and at least one second type transistor. For example, each group includes a plurality of first type transistors and a plurality of second type transistors. For example, the number of first type transistors and the number of second type transistors included in each group may be the same or different.

[0056] like Figure 1 As shown, the layout design method provided by the embodiment of the present disclosure also includes:

[0057] S103: Matching transistors in each group according to the type of transistors in each group and the signals configured to be transmitted to each electrode of each transistor to form a plurality of layout groups.

[0058] For example, Figure 2 and Figure 3 As shown, step 2 includes: grouping the transistors according to the finger number, and pairing the P-type and N-type transistors with the same finger number one by one.

[0059] For example, the first type transistor and the second type transistor in the same group can be matched. The above-mentioned "matching the first type transistor and the second type transistor in the same group" includes pairing a first type transistor with a second type transistor to stack the gates of the two, stacking the first pole of the first type transistor with one of the first pole and the second pole of the second type transistor, and stacking the second pole of the first type transistor with the other of the first pole and the second pole of the second type transistor. The first pole and the second pole of each transistor in the embodiment of the present disclosure can be interchangeable, that is, the first pole of the first type transistor can be stacked with the second pole of the second type transistor, or with the first pole of the second type transistor, the second pole of the first type transistor can be stacked with the second pole of the second type transistor, or with the first pole of the second type transistor, and the transistor stacking relationship can be set according to the actual layout requirements.

[0060] For example, FIG. 4A to FIG. 4C As shown, the first type transistor 100 with a unit device width of 1 includes a gate 110, a channel region 101, a first electrode 120 and a second electrode 130, and the second type transistor 200 with a unit device width of 1 includes a gate 210, a channel region 201, a first electrode 220 and a second electrode 230. A group of transistors with a unit device width of 1 includes a first type transistor 100 and a second type transistor 200, the gate 110 of the first type transistor 100 and the gate 210 of the second type transistor 200 are stacked, the first electrode 120 of the first type transistor 100 and the first electrode 220 of the second type transistor 200 are stacked, and the second electrode 130 of the first type transistor 100 and the second electrode 230 of the second type transistor 200 are stacked, thereby achieving matching between the first type transistor and the second type transistor.

[0061] For example, Figure 5 As shown, a group of transistors with a unit device width of 2 includes a first type transistor 100 and a second type transistor 200, a gate 110 of the first type transistor 100 and a gate 210 of the second type transistor 200 are stacked, a first electrode 120 of the first type transistor 100 and a first electrode 220 of the second type transistor 200 are stacked, and a second electrode 130 of the first type transistor 100 and a second electrode 230 of the second type transistor 200 are stacked, thereby achieving matching between the first type transistor and the second type transistor.

[0062] For example, the signal configured to be input to the first electrode of the first type transistor is the first signal, and the signal configured to be input to the first electrode of the second type transistor is the second signal. For example, the first signal and the second signal may both be drain signals.

[0063] For example, matching the transistors in each group according to the type of transistors in each group and the signals of each pole configured as the input transistor includes comparing whether the first signal and the second signal are the same: when the first signal and the second signal are the same, performing the first stage pairing on the transistors of the first type and the second type that meet the matching conditions, wherein after completing the first stage pairing of the first type transistors and the second type transistors, multiple first layout groups in multiple layout groups are formed; after completing the first stage pairing, performing the second stage pairing on at least part of the first type transistors and the second type transistors whose first signals and the second signals are different.

[0064] For example, Figure 3 As shown, the same group includes multiple first-type transistors and multiple second-type transistors, and compares whether the drain signal (such as the first signal) configured to be input to the drain of each first-type transistor is the same as the drain signal (such as the second signal) configured to be input to the drain of each second-type transistor.

[0065] For example, Figure 3 As shown, in the same group, if the drain signal input to the drain of a first type transistor is the same as the drain signal input to the drain of a second type transistor, then the first type transistor and the second type transistor may be paired, that is, it is also necessary to determine whether the first type transistor and the second type transistor meet the matching conditions. If the matching conditions are met, the first type transistor and the second type transistor are paired.

[0066] For example, the signal configured to be input to the second pole of the first type transistor is the third signal, the signal configured to be input to the second pole of the second type transistor is the fourth signal, the signal configured to be input to the gate of the first type transistor is the fifth signal, and the signal configured to be input to the gate of the second type transistor is the sixth signal. For example, the third signal and the fourth signal may both be source signals. For example, the fifth signal and the sixth signal may both be gate signals.

[0067] For example, the first-stage pairing of transistors that meet the matching conditions in the first-type transistor and the second-type transistor includes comparing whether the third signal is the same as the fourth signal: if the third signal is the same as the fourth signal, the first-type transistor and the second-type transistor are paired one-to-one; if the third signal is different from the fourth signal, comparing the fifth signal with the sixth signal: if the fifth signal is the same as the sixth signal, the first-type transistor and the second-type transistor are paired one-to-one; if the fifth signal is different from the sixth signal, determining whether the potentials of the fifth signal and the sixth signal are opposite: if the potentials of the fifth signal and the sixth signal are opposite, the first-type transistor and the second-type transistor are paired one-to-one; if the potentials of the fifth signal and the sixth signal are not opposite, the first-type transistor and the second-type transistor wait for the second-stage pairing.

[0068] For example, Figure 3 As shown, in the same group, if the drain signal input to the drain of a first type transistor is the same as the drain signal input to the drain of a second type transistor, the subsequent matching condition may include comparing whether the source signal input to the source of the first type transistor is the same as the source signal input to the source of the second type transistor. If the two source signals are the same, the first type transistor and the second type transistor may be paired one-to-one to form Figure 4C or Figure 5 The first layout group is shown.

[0069] For example, Figure 3 As shown, in the same group, if the drain signal input to the drain of a first type transistor is the same as the drain signal input to the drain of a second type transistor, and the source signal input to the source of the first type transistor is different from the source signal input to the source of the second type transistor, the subsequent matching condition may include comparing whether the gate signal input to the gate of the first type transistor is the same as the gate signal input to the gate of the second type transistor. If the two gate signals are the same, the first type transistor and the second type transistor may be paired one-to-one to form Figure 4C or Figure 5 The first layout group is shown.

[0070] For example, Figure 3 As shown, in the case of comparing whether the gate signal input to the gate of the first type transistor is the same as the gate signal input to the gate of the second type transistor, if the two gate signals are the same, and the source of the first type transistor and the source of the second type transistor are both connected to the power signal line, then the first type transistor and the second type transistor can be paired one-to-one to form Figure 4C or Figure 5 The first layout group is shown.

[0071] For example, Figure 3 As shown, in the case of comparing whether the gate signal input to the gate of the first type transistor is the same as the gate signal input to the gate of the second type transistor, if the two gate signals are the same, but the source of at least one of the first type transistor and the second type transistor is not connected to the power signal line, then the first type transistor and the second type transistor can also be paired one-to-one to form Figure 4C or Figure 5 The first layout group is shown.

[0072] For example, Figure 4C and Figure 5 As shown, the power signal line 400 to which the source of the transistor is connected may be the first power signal line 410 or the second power signal line 420. For example, the source 230 of the first type transistor 100 may be electrically connected to one of the first power signal line 410 and the second power signal line 420, and the source 230 of the second type transistor 200 may be electrically connected to the other of the first power signal line 410 and the second power signal line 420.

[0073] For example, one of the first power signal line 410 and the second power signal line 420 outputs a high voltage, and the other outputs a low voltage. For example, the signal output by one of the first power signal line 410 and the second power signal line 420 may be a VDD signal, and the signal output by the other may be a VSS signal. For example, one of the first power signal line 410 and the second power signal line 420 outputs a constant positive voltage, and the other outputs a constant negative voltage. For example, one of the first power signal line 410 and the second power signal line 420 may be grounded. For example, a high potential voltage is input to the source of a P-type transistor, and a low potential voltage is input to the source of an N-type transistor.

[0074] For example, Figure 3 As shown, in the same group, if the drain signal input to the drain of a first type transistor is the same as the drain signal input to the drain of a second type transistor, and the source signal input to the source of the first type transistor is different from the source signal input to the source of the second type transistor, the subsequent matching condition may include comparing whether the gate signal input to the gate of the first type transistor is the same as the gate signal input to the gate of the second type transistor, and if the two gate signals are different, determining whether the potentials of the two gate signals are opposite: if the potentials of the two gate signals are opposite, the first type transistor and the second type transistor may be paired one-to-one to form Figure 4C or Figure 5 The first layout group is shown.

[0075] For example, Figure 3As shown, when the gate signal input to the gate of the first type transistor is different from the gate signal input to the gate of the second type transistor and the potential is not opposite, the first type transistor and the second type transistor need to wait for the second stage pairing, that is, the next stage pairing.

[0076] For example, performing second-stage pairing of at least a portion of the remaining first-type transistors and second-type transistors except the first layout group includes comparing a fifth signal and a sixth signal configured as input to at least a portion of the remaining first-type transistors and second-type transistors except the first layout group: if the fifth signal is the same as the sixth signal, and at least one of the first signal, the second signal, the third signal, and the fourth signal configured as input to the transistors in the first layout group is the same as the corresponding signal configured as input to at least a portion of the remaining first-type transistors and second-type transistors except the first layout group, matching at least a portion of the remaining first-type transistors and second-type transistors except the first layout group to form multiple second layout groups in the multiple layout groups; determining whether the second electrode of at least one of the first-type transistor and the second-type transistor in the second layout group is electrically connected to the signal line: if the second electrodes of all transistors in the second layout group are not electrically connected to the signal line, the second-stage pairing ends.

[0077] For example, Figure 3 As shown, the matched combination (such as the combination formed by stacking the first type transistor and the second type transistor forming the first layout group as mentioned above) is chain-matched with the remaining P / N transistors (such as the first type transistor and the second type transistor).

[0078] For example, the above-mentioned "chain matching" may include the remaining first-type transistors and second-type transistors that can be matched being connected to the first and second electrodes of the first-type transistors or the second-type transistors forming the first layout group in the circuit, respectively, or the remaining first-type transistors and second-type transistors that can be matched being input with the same signals as the first and second electrodes of the first-type transistors or the second-type transistors forming the first layout group in the circuit.

[0079] For example, Figure 3 As shown, the new P / N transistor combination (a combination formed by stacking the first type transistor and the second type transistor of the second layout group) needs to have the same gate signal, and the source or drain signal (such as the source signal or the drain signal) of the P / N transistor is respectively the same as the source or drain signal of the generated transistor combination (such as the source signal or the drain signal). The matching of this step is cyclic, and when the sources of the new P / N transistors are matched and connected to the power signal line signal, the cycle is terminated.

[0080] For example, Figure 3As shown, the second stage pairing of at least part of the remaining first type transistors and second type transistors except the first layout group includes: comparing the gate signals configured to be input to the remaining first type transistors and second type transistors: if the gate signal of a first type transistor is the same as the gate signal of a second type transistor, and the source signal of the transistor configured to be input to the first layout group is the same as the drain signal of one of the first type transistor and the second type transistor, and the drain signal of the transistor configured to be input to the first layout group is the same as the other drain signal of the first type transistor and the second type transistor, then the first type transistor and the second type transistor are matched to form a second layout group.

[0081] For example, the second layout group can be Figure 4C or Figure 5 The layout groups shown have the same features. For example, the first type transistor and the second type transistor in the second layout group have the same unit device width, such as the finger number is 1, 2 or more; in the second layout group, the gate of the first type transistor is stacked with the gate of the second type transistor, one of the first pole and the second pole of the first type transistor is stacked with the first pole of the second type transistor, and the other of the first pole and the second pole of the first type transistor is stacked with the second pole of the second type transistor.

[0082] For example, performing second-stage pairing on at least part of the remaining first-type transistors and second-type transistors except the first layout group also includes: if the fifth signal is the same as the sixth signal, performing second-stage pairing on the first-type transistors and the second-type transistors; if the fifth signal is different from the sixth signal, determining whether to perform second-stage pairing based on whether the second pole of the transistor is electrically connected to the signal line: if the second pole of the transistor is electrically connected to the signal line, performing second-stage pairing on the first-type transistors and the second-type transistors; if the second pole of the transistor is not electrically connected to the signal line, the second-stage pairing ends.

[0083] For example, Figures 3 to 5 As shown, in the process of determining the gate signals of the remaining plurality of first-type transistors and the gate signals of the plurality of second-type transistors, if the gate signal of a first-type transistor is the same as the gate signal of a second-type transistor, and the sources of both are connected to the power signal line 400, then the first-type transistor and the second-type transistor can also be paired one-to-one to form Figure 4C or Figure 5 For example, the above “both sources are connected to the power signal line 400 ” may include that the source of one of the first type transistor and the second type transistor is connected to the first power signal line 410 , and the source of the other is connected to the second power signal line 420 .

[0084] For example, Figures 3 to 5 As shown, in the process of determining the gate signals of the remaining plurality of first-type transistors and the gate signals of the plurality of second-type transistors, if the gate signal of a first-type transistor is the same as the gate signal of a second-type transistor, and the source of at least one of the two is not connected to the power signal line 400, such as the source of at least one of the first-type transistor and the second-type transistor is connected to the first power signal line 410 or the second power signal line 420, or the source of the first-type transistor and the second-type transistor is not connected to the power signal line, the first-type transistor and the second-type transistor can also be paired one-to-one to form Figure 4C or Figure 5 The second set of illustrations shown.

[0085] For example, Figure 3 As shown, in the process of determining the gate signals of the remaining plurality of first-type transistors and the gate signals of the plurality of second-type transistors, if the gate signal of a first-type transistor is different from the gate signal of a second-type transistor, but the source of the first-type transistor and the source of the second-type transistor are both connected to the power signal line, such as the source of one of the first-type transistor and the second-type transistor is connected to the first power signal line 410, and the source of the other is connected to the second power signal line 420, then the first-type transistor and the second-type transistor can also be paired one-to-one to form Figure 4C or Figure 5 The second set of illustrations shown.

[0086] For example, Figure 3 As shown, in the process of determining the gate signals of the remaining multiple first-type transistors and the gate signals of the multiple second-type transistors, if the gate signal of a first-type transistor is different from the gate signal of a second-type transistor, and the sources of the first-type transistor and the second-type transistor are not both connected to the power signal line, the second stage pairing ends.

[0087] For example, matching the transistors in each group according to the types of transistors in each group and the signals configured as input to each pole of the transistor also includes: after the second stage pairing is completed, the first signal that is only configured to input the first type of transistor and the second signal that is configured to input the second type of transistor are the same, or the fifth signal that is only configured to input the first type of transistor and the sixth signal that is configured to input the second type of transistor are the same, are paired in the third stage to form multiple third layout groups in the multiple layout groups.

[0088] For example, Figure 3 As shown, P / N transistors having only the same drain or only the same gate signal are paired.

[0089] For example, Figure 3 As shown, after the second stage pairing is completed, the same situation of the drain signals or gate signals in the remaining first type transistors and second type transistors is judged. If only the drain signal among the drain signal, gate signal and source signal input to a first type transistor is the same as the drain signal input to a second type transistor, the first type transistor and the second type transistor are paired one-to-one to form a third layout group.

[0090] For example, Figure 3 As shown, after the second stage pairing is completed, the same situation of the drain signals or gate signals in the remaining first type transistors and second type transistors is judged. If only the gate signal among the drain signal, gate signal and source signal input to a first type transistor is the same as the gate signal input to a second type transistor, the first type transistor and the second type transistor are paired one-to-one to form a third layout group.

[0091] For example, the third layout group can be combined with Figure 4C or Figure 5 The layout groups shown have the same features. For example, in the third layout group, the first type transistor and the second type transistor have the same unit device width, such as the number of fingers is 1, 2 or more; in the third layout group, the gate of the first type transistor is stacked with the gate of the second type transistor, one of the first pole and the second pole of the first type transistor is stacked with the first pole of the second type transistor, and the other of the first pole and the second pole of the first type transistor is stacked with the second pole of the second type transistor.

[0092] For example, matching transistors in each group according to the types and signals of the transistors in each group also includes: after completing the third stage pairing, performing a fourth stage pairing on the remaining first type transistors and second type transistors that have not been paired in the first stage pairing, the second stage pairing, and the third stage pairing to form multiple fourth layout groups in the multiple layout groups; if after completing the fourth stage pairing, the multiple transistors still include a remaining unpaired transistor, the transistor is recorded.

[0093] For example, Figure 3 As shown, the remaining P / N transistors are paired, and the remaining unpaired individual P or N transistors are recorded.

[0094] For example, the fourth layout group can be combined with Figure 4C or Figure 5The layout groups shown have the same features. For example, in the fourth layout group, the first type transistor and the second type transistor have the same unit device width, such as the number of fingers is 1, 2 or more; in the fourth layout group, the gate of the first type transistor is stacked with the gate of the second type transistor, one of the first pole and the second pole of the first type transistor is stacked with the first pole of the second type transistor, and the other of the first pole and the second pole of the first type transistor is stacked with the second pole of the second type transistor.

[0095] For example, Figure 3 As shown, the remaining first type transistors and second type transistors that have not been paired in the first stage pairing, the second stage pairing and the third stage pairing are paired one by one. If there is a remaining first type transistor or a second type transistor, the transistor is recorded.

[0096] For example, Figure 3 As shown, the fourth stage pairing of the remaining first type transistors and second type transistors that have not been paired in the first stage pairing, the second stage pairing, and the third stage pairing may include that the gate signal, the source signal, and the drain signal input to a first type transistor are different from the corresponding signals input to a second type transistor, but the sources of the first type transistor and the second type transistor are both connected to the power signal line, then the first type transistor and the second type transistor can also be paired one-to-one to form Figure 4C or Figure 5 The fourth set of plates shown.

[0097] For example, Figure 3 As shown, the fourth stage pairing of the remaining first-type transistors and second-type transistors that have not been paired in the first-stage pairing, the second-stage pairing, and the third-stage pairing may include that the gate signal, the source signal, and the drain signal input to a first-type transistor are different from the corresponding signals input to a second-type transistor, and the sources of the first-type transistor and the second-type transistor are not connected to the power signal line, and the first-type transistor and the second-type transistor may also be paired one-to-one to form Figure 4C or Figure 5 The fourth set of plates shown.

[0098] For example, after each group of transistors is paired in the above-mentioned several stages, if there are unpaired transistors in different groups of transistors, the first type transistors and the second type transistors in different groups can be adaptively paired, and in the adaptive pairing process, the first type transistors and the second type transistors with closer finger numbers are preferentially paired. For example, if a group of transistors with a finger number of 1 has one first type transistor remaining, a group of transistors with a finger number of 2 has one second type transistor remaining, and a group of transistors with a finger number of 3 has one second type transistor remaining, then the first type transistors in the group of transistors with a finger number of 1 can be paired one-to-one with the second type transistors in the group of transistors with a finger number of 2, and the remaining second type transistor in the group of transistors with a finger number of 3 is recorded.

[0099] For example, Figure 2 As shown, step 3 includes: designing the layout of P / N transistor combination units and single P or N transistors with different finger numbers. For example, after completing the above pairing, the first type transistor and the second type transistor are combined in the layout.

[0100] For example, Figure 4C As shown, each transistor also includes a channel region, the channel region is located between the first pole and the second pole, and the gate is stacked with the channel region. For example, a polysilicon layer is provided at the position of the channel region of each transistor. For example, the first pole and the second pole of each transistor both include a metal layer. For example, the gate of each transistor includes a gate metal layer, and the gate metal layer is overlapped with the polysilicon layer of the channel region. For example, the first pole, the channel region and the second pole can be arranged along the U direction.

[0101] For example, Figure 4C As shown, the first and second electrodes of the transistor extend along a first direction, such as extending along a V direction. For example, the polysilicon layer disposed between the first and second electrodes of the transistor may extend along the V direction. For example, the gate disposed between the first and second electrodes of the transistor may extend along the V direction.

[0102] For example, Figure 4C As shown, the first type transistor 100 includes a channel region 101, along the U direction, the channel region 101 is located between the first pole 120 and the second pole 130, and along the direction perpendicular to the UV plane, the gate 110 is stacked with the channel region 101. For example, the second type transistor 200 includes a channel region 201, along the U direction, the channel region 201 is located between the first pole 220 and the second pole 230, and along the direction perpendicular to the UV plane, the gate 210 is stacked with the channel region 201.

[0103] For example, Figure 4CAs shown, in any one of the first layout group, the second layout group, the third layout group and the fourth layout group, the channel region 101 of the first type transistor 100 overlaps with the channel region 201 of the second type transistor 200, the polysilicon layer at the channel region 101 of the first type transistor 100 is stacked with the polysilicon layer at the channel region 201 of the second type transistor 200, the metal layer included in the first electrode 120 of the first type transistor 100 is stacked with the metal layer included in the first electrode 220 of the second type transistor 200, the metal layer included in the second electrode 130 of the first type transistor 100 is stacked with the metal layer included in the second electrode 230 of the second type transistor 200, and the metal layer included in the gate 110 of the first type transistor 100 is stacked with the metal layer included in the gate 210 of the second type transistor 200.

[0104] For example, Figure 4C As shown, at least part of the transistors further include a dummy gate, which is located on a side of at least one of the first pole and the second pole away from the channel region. For example, the dummy gate may include a metal layer, the dummy gate may overlap with the polysilicon layer, and the dummy gate and the polysilicon overlap position may include a dummy channel region. For example, the dummy gate is located at the edge of the transistor. For example, the polysilicon layer at the dummy gate position may extend along the V direction.

[0105] The "virtual gate" here may include a gate that does not function as a gate in the transistor but functions as a gate after a subsequent layout combination, as well as a virtual structure that does not function as a gate in the transistor and does not function as a gate in a subsequent layout combination.

[0106] For example, Figure 4C As shown, the first type transistor 100 includes a dummy gate 310, and the dummy gate 310 is located on a side of at least one of the first electrode 120 and the second electrode 130 away from the channel region 101. For example, the second type transistor 200 includes a dummy gate 320, and the dummy gate 320 is located on a side of at least one of the first electrode 220 and the second electrode 230 away from the channel region 201. For example, the metal layer included in the dummy gate 310 of the first type transistor 100 is stacked with the metal layer included in the dummy gate 320 of the second type transistor 200.

[0107] For example, Figure 4C As shown, the dummy gate includes a first dummy gate and a second dummy gate, and the first dummy gate and the second dummy gate are respectively located on a side of the first pole away from the channel region and a side of the second pole away from the channel region. For example, the first dummy gate and the second dummy gate are respectively located on two side edges of the transistor. For example, the first dummy gate, the first pole, the channel region, the second pole and the second dummy gate can be arranged in sequence along the U direction.

[0108] For example, Figure 4C As shown, the dummy gate 310 of the first type transistor 100 includes a first dummy gate 311 and a second dummy gate 312, and the first dummy gate 311 and the second dummy gate 312 are respectively located on a side of the first pole 120 away from the channel region 101 and a side of the second pole 130 away from the channel region 101. For example, the dummy gate 320 of the second type transistor 200 includes a first dummy gate 321 and a second dummy gate 322, and the first dummy gate 321 and the second dummy gate 322 are respectively located on a side of the first pole 220 away from the channel region 201 and a side of the second pole 230 away from the channel region 201. For example, the first dummy gate.

[0109] For example, Figure 4C As shown, the first power signal line 410 can also be called a first power rail 410, and the second power signal line 420 can also be called a second power rail 420. The first power rail 410 and the second power rail 420 both extend along a second direction, such as along a U direction, and the first direction intersects the second direction.

[0110] For example, Figure 4C As shown, the first power rail 410 and the second power rail 420 are located at both sides of the first pole in the first direction.

[0111] For example, Figure 4C As shown, the first stage pairing of transistors includes: stacking the channel region of the first type transistor with the channel region of the second type transistor, and stacking the first electrode of the first type transistor with one of the first electrode and the second electrode of the second type transistor to form a first electrode group, and stacking the second electrode of the first type transistor with the other of the first electrode and the second electrode of the second type transistor to form a second electrode group.

[0112] For example, Figure 4C As shown, the method of pairing transistors in any of the second stage pairing, the third stage pairing and the fourth stage pairing can be the same as the method of pairing in the first stage, and will not be repeated here.

[0113] For example, in at least one first layout group, the dummy gate of the first type transistor is stacked with the dummy gate of the second type transistor to form a dummy gate group, and the dummy gate group includes a first dummy gate group and a second dummy gate group, and the first dummy gate group and the second dummy gate group are respectively located on the side of the first pole group away from the channel region and the side of the second pole group away from the channel region. For example, the dummy gate group of at least one second layout group includes a first dummy gate group and a second dummy gate group, and the first dummy gate group and the second dummy gate group are respectively located on the side of the first pole group away from the channel region and the side of the second pole group away from the channel region. For example, the dummy gate group of at least one third layout group includes a first dummy gate group and a second dummy gate group, and the first dummy gate group and the second dummy gate group are respectively located on the side of the first pole group away from the channel region and the side of the second pole group away from the channel region. For example, the dummy gate group of at least one fourth layout group includes a first dummy gate group and a second dummy gate group, and the first dummy gate group and the second dummy gate group are respectively located on the side of the first pole group away from the channel region and the side of the second pole group away from the channel region.

[0114] like Figure 1 As shown, the layout design method provided by the embodiment of the present disclosure includes:

[0115] S104: According to the electrical connection relationship between the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal lines, at least a portion of the structures of at least a portion of the transistors in the multiple layout groups are stacked, and the transistors in the multiple layout groups are connected to form a complete layout corresponding to the circuit.

[0116] For example, Figure 2 As shown, step 4 includes: according to circuit rules, inserting a corresponding metal layer in a combined unit layout where a source of a P / N transistor is connected to a power signal line and a common drain.

[0117] FIG. 6A to FIG. 6C Schematic diagrams of three different layout groups are shown respectively.

[0118] For example, Fig. 6A As shown, the source 230 of the second type transistor 200 (such as a P-type transistor) can be connected to the power signal line 410 to receive a VDD signal, and the source 130 of the first type transistor 100 (such as an N-type transistor) is not electrically connected to the power signal line 400. The process of pairing the above-mentioned first type transistor 100 with the second type transistor 200 includes stacking the source, drain and channel regions of the two respectively. Then, in the paired first type transistor and second type transistor, only the source 230 of the second type transistor 200 is connected to the power signal line 410.

[0119] For example, Figure 6BAs shown, the source 130 of the first type transistor 100 (such as an N-type transistor) can be connected to the power signal line 420 to receive a VSS signal, and the source 230 of the second type transistor 200 (such as a P-type transistor) is not electrically connected to the power signal line 400. The process of pairing the above-mentioned first type transistor 100 with the second type transistor 200 includes stacking the source, drain and channel regions of the two respectively. Then, in the paired first type transistor and second type transistor, only the source 130 of the first type transistor 100 is connected to the power signal line 420.

[0120] For example, Figure 6C As shown, the source 230 of the second type transistor 200 (such as a P-type transistor) can be connected to the power signal line 410 to receive a VDD signal, and the source 130 of the first type transistor 100 (such as an N-type transistor) can be connected to the power signal line 420 to receive a VSS signal. The process of pairing the above-mentioned first type transistor 100 with the second type transistor 200 includes stacking the source, drain and channel regions of the two respectively. In the paired first type transistor and second type transistor, the source 130 of the first type transistor 100 is connected to the power signal line 420, and the source 230 of the second type transistor 200 is connected to the power signal line 410 at the same time.

[0121] Of course, the embodiments of the present disclosure are not limited to stacking the source of the first type transistor and the source of the second type transistor, and stacking the drain of the first type transistor and the drain of the second type transistor. The source of the first type transistor and the drain of the second type transistor can also be stacked, and the drain of the first type transistor and the source of the second type transistor can be stacked.

[0122] For example, Figure 2 As shown, step 5 includes: performing layout design of the overall circuit, first inserting a corresponding number of combined unit layouts (such as at least one of the first layout group, the second layout group, the third layout group and the fourth layout group) and a separate P transistor unit layout or an N transistor unit layout according to circuit characteristics, and maintaining the existing metal layer connection relationship in step 4. The above-mentioned "insertion" can refer to the stacking combination of the first type transistor and the second type transistor, and stacking the layout of the transistor that has not been paired before on the corresponding layout.

[0123] For example, according to the pairing result of the first type transistor and the second type transistor, the corresponding first type transistor and the second type transistor are stacked to form at least one of the first layout, the second layout, the third layout and the fourth layout.

[0124] For example, before stacking at least a portion of the structures of at least a portion of the transistors in a plurality of layout groups, the layout design method further includes arranging the plurality of layout groups according to the electrical connection relationship between the plurality of transistors in the circuit and the electrical connection relationship between the plurality of transistors and the signal lines.

[0125] For example, Figure 2 As shown, step 6 includes: arranging the inserted unit layouts in the order of the path from the circuit input end to the output end. For example, the first layout group, the second layout group, the third layout group, the fourth layout group and the layout of the individual transistor (if any) are arranged in the order of the path from the circuit input end to the output end.

[0126] For example, Figure 2 As shown, step 7 includes: starting layout merging. First, two groups of cells with the same source or drain signals of the P transistor and the same source or drain signals of the N transistor are merged. The metal layer areas of the two groups of cell layouts are aligned and stacked. The combined cells generated in step 6 that are arranged closer are preferentially merged. In addition, this step is also applicable to the combined cells.

[0127] For example, stacking at least part of the structure of at least part of the transistors in multiple layout groups includes: stacking one of the first electrode group and the second electrode group in one layout group with one of the first electrode group and the second electrode group in another layout group, stacking a dummy gate group in one layout group with a channel region in another layout group, and stacking a dummy gate group in another layout group with a channel region in one layout group.

[0128] Fig. 7A A schematic diagram of a layout group provided according to an example of at least one embodiment of the present disclosure, Figure 7B A schematic diagram of another layout group provided according to an example of an embodiment of the present disclosure, Figure 7C for Fig. 7A and Figure 7B Schematic diagram of the layout after the layout group is stacked.

[0129] For example, Fig. 7A As shown, the layout group CMOSA is a paired combination layout including a first type transistor and a second type transistor, and the layout group CMOSA includes a channel region group 10 formed by stacking a channel region of the first type transistor and a channel region of the second type transistor, a gate group 11 formed by stacking a gate of the first type transistor and a gate of the second type transistor, a first electrode group 12 formed by stacking a first electrode of the first type transistor and one of the first and second electrodes of the second type transistor, and a second electrode group 13 formed by stacking a second electrode of the first type transistor and another of the first and second electrodes of the second type transistor. Fig. 7AIn the figure, X represents one electrode of the first type transistor, and Y represents one electrode of the second type transistor), a first dummy gate of the first type transistor and a first dummy gate of the second type transistor are stacked to form a first dummy gate group 31, and a second dummy gate of the first type transistor and a second dummy gate of the second type transistor are stacked to form a second dummy gate group 32.

[0130] For example, Fig. 7A As shown, the layout group CMOSB is a paired combination layout including a first type transistor and a second type transistor, and the layout group CMOSB includes a channel region group 20 formed by stacking a channel region of the first type transistor and a channel region of the second type transistor, a gate group 21 formed by stacking a gate of the first type transistor and a gate of the second type transistor, a first electrode group 22 formed by stacking a first electrode of the first type transistor and one of the first electrode and the second electrode of the second type transistor, and a second electrode group 23 formed by stacking a second electrode of the first type transistor and the other of the first electrode and the second electrode of the second type transistor. Figure 7B In the figure, X represents one electrode of the first type transistor, and Y represents one electrode of the second type transistor), a first dummy gate of the first type transistor and a first dummy gate of the second type transistor are stacked to form a first dummy gate group 33, and a second dummy gate of the first type transistor and a second dummy gate of the second type transistor are stacked to form a second dummy gate group 34.

[0131] For example, Figures 7A to 7C As shown, stacking layout group CMOSA and layout group CMOSB includes: stacking the gate group 11 of layout group CMOSA and the second dummy gate group 34 of CMOSB, stacking the second electrode group 13 of layout group CMOSA and the second electrode group 23 of layout group CMOSB, and stacking the second dummy gate group 32 of layout group CMOSA and the gate group 21 of layout group CMOSB, thereby saving the space occupied by two separate layout groups CMOSA and CMOSB.

[0132] For example, connecting transistors in a plurality of layout groups to form a complete layout corresponding to a circuit includes: electrically connecting a first power rail to a second electrode of a first type transistor, and electrically connecting a second power rail to a second electrode of a second type transistor.

[0133] For example, Figure 2 As shown, step 8 includes: combining the cells that have been combined and the cells that have not participated in the combination according to the arrangement order generated in step 6. Since there is no simultaneous source or drain signal between all cells, when the cells are merged, a dummy gate (such as a virtual gate) needs to be left between the two cells, and the polysilicon regions are aligned and stacked.

[0134] For example, by 7A to 7C The combination of the layout group stacking method shown in the figure and the layout group without stacking can be arranged in the order according to the circuit rules in a similar way. Figure 7C The stackup shown.

[0135] For example, two layout groups have two drain groups to which the same drain signal is input, but do not have two source groups to which the same source signal is input. Therefore, in the process of stacking the two layout groups, a dummy gate group of one layout group is stacked with a gate group of another layout group, and another dummy gate group of the one layout group is not stacked with the structure of the other layout group, but there is no situation where two dummy gate groups of a layout group are stacked with the structure of the same layout group.

[0136] For example, Figure 2 As shown, step 9 includes: electrically connecting multiple layout groups according to circuit rules.

[0137] For example, a complete layout corresponding to a circuit is formed by connecting transistors of multiple layout groups.

[0138] The layout design method provided by the embodiment of the present disclosure can improve the efficiency of CFET integrated circuit layout design and effectively reduce the layout area of ​​a CFET standard unit with double height. At the same time, the structural characteristics of the shared metal layer (such as at least one of the source metal layer and the drain metal layer) and the shared polysilicon (such as the shared gate) in the CFET are fully utilized to avoid redundant metal routing. The above-mentioned "double height" can refer to the presence of only one set of the first power rail 410 and the second power rail 420.

[0139] The layout design method provided in the embodiment of the present disclosure can effectively utilize the structural characteristics of the shared metal layer (metal layer in the source and drain regions) and the shared polysilicon corresponding gate in the CFET to achieve the pairing and layout combination of P-type transistors and N-type transistors in a specific circuit.

[0140] Figure 8 An exclusive OR gate (XOR2) circuit provided according to at least one embodiment of the present disclosure, Fig. 9 and Fig.10 for Figure 8 The circuit shown is a schematic diagram of a pairing of a first type transistor and a second type transistor. Fig.11 for Figure 8 Schematic diagram of multiple layout groups in the circuit shown, Fig.12 Based on Figure 8 The circuit shown is Fig.11 The schematic diagram of the arrangement of multiple layout groups is shown. Fig.13 for Figure 8 Complementary field-effect transistor (CFET) layout for the circuit shown.

[0141] For example, Figures 8 to 10 As shown, the characteristic parameters of multiple transistors in the circuit are recorded.

[0142] For example, Figures 8 to 11 As shown, the circuit includes P-type transistors and N-type transistors. The "P" in the figure represents a P-type transistor, and the "N" in the figure represents an N-type transistor. The transistor includes a source and a drain. The "S" in the figure represents a source and the "P" represents a drain. For example, the circuit includes four transistors with a unit device width of 1 and six transistors with a unit device width of 2. Figures 8 to 10 The "1" in the figure indicates that the unit device width is 1. Figures 8 to 10 The "2" in the figure indicates that the unit device width is 2. For example, Figure 8 In the circuit shown, P1, P2, N1 and N2 are in stage 1. st , P3, P4, P5, N3, N4 and N5 are in stage 2 nd . The above stage 1 st and stage 2 nd It may refer to the first level and the second level in a circuit, with an intermediate node being present between the first level and the second level.

[0143] For example, Figure 8 As shown, the connection relationship between the source, drain and gate of each transistor and the signal input to each electrode of each transistor are recorded, such as the signal input to the gate of transistor P1, transistor N1, transistor P4 and transistor N5 is signal A, the signal input to the gate of transistor P2, transistor N2, transistor P5 and transistor N4 is signal B, and the gate of transistor P3 and transistor N3 is connected to the drain of transistor P2. For example, the source of transistor P1 is configured to input a VDD signal, the drain of transistor P1 is connected to the source of transistor P2, the drain of transistor P2 is connected to the drain of transistor N1, and the source of transistor N1 is input with a VSS signal. For example, the source of transistor P4 is input with a VDD signal, the drain of transistor P4 is connected to the source of transistor P3, the drain of transistor P3 is connected to the drain of transistor N3, and the source of transistor N3 is input with a VSS signal. For example, a VDD signal is input to the source of the transistor P5 , a drain of the transistor P5 is connected to the source of the transistor P3 , a source of the transistor N4 is connected to the drain of the transistor N5 , and a VSS signal is input to the source of the transistor N5 .

[0144] For example, Figures 8 to 10 As shown, after the circuit is divided into a plurality of transistors, these transistors are paired and combined into a layout group according to the matching method of the first type transistor and the second type transistor.

[0145] For example, Figures 8 to 11As shown, both transistor P2 and transistor N2 are transistors with a unit device width of 1, the drains of transistor P2 and transistor N2 are input with the same signal, and the gates of transistor P2 and transistor N2 are input with the same signal B, then transistor P2 and transistor N2 are paired and stacked to form a layout group L1. For example, the source of transistor P2 is stacked with the drain of transistor N2 to form a second electrode group G2, the drain of transistor P2 is stacked with the source of transistor N2 to form a first electrode group G1, the channel region of transistor P2 is stacked with the channel region of transistor N2, and the two dummy gates of the two transistors are stacked to form a first dummy gate group D1 and a second dummy gate group D2.

[0146] For example, Figures 8 to 11 As shown, transistor P3 and transistor N3 are both transistors with a unit device width of 2. If F1 and F2 are included, the drains of transistor P3 and transistor N3 are input with the same signal, and the gates of transistor P3 and transistor N3 are input with the same signal, then transistor P3 and transistor N3 are paired and stacked to form layout group L2. For example, in F1, the source of transistor P3 is stacked with the source of transistor N3 to form a second electrode group G2, the drain of transistor P3 is stacked with the drain of transistor N3 to form a first electrode group G1, the channel region of transistor P3 is stacked with the channel region of transistor N3, and the two dummy gates of the two transistors are stacked respectively to form a first dummy gate group D5 and a second dummy gate group D6; in F2, the source of transistor P3 is stacked with the drain of transistor N3 to form a first electrode group G1, the drain of transistor P3 is stacked with the source of transistor N3 to form a second electrode group G2, the channel region of transistor P3 is stacked with the channel region of transistor N3, and the two dummy gates of the two transistors are stacked respectively to form a first dummy gate group D7 and a second dummy gate group D8.

[0147] For example, Figures 8 to 11 As shown, transistor P1 and transistor N1 are connected to the source of transistor P2 and the drain of transistor N2 respectively (such as the combination produced by chain matching), transistor P1 and transistor N1 are both transistors with a unit device width of 1, and the gates of transistor P1 and transistor N1 are input with the same signal A, then transistor P1 and transistor N1 are paired and stacked to form a layout group L3. For example, the source of transistor P1 is stacked with the source of transistor N1 to form a second electrode group G2, the drain of transistor P1 is stacked with the drain of transistor N1 to form a first electrode group G1, the channel region of transistor P1 is stacked with the channel region of transistor N1, and the two dummy gates of the two transistors are stacked to form a first dummy gate group D3 and a second dummy gate group D4.

[0148] For example, Figures 8 to 11As shown, transistor P4 and transistor N5 are located on both sides of transistor P3 and transistor N4, and both transistor P4 and transistor N5 are transistors with a unit device width of 2. If F1 and F2 are included, the gates of transistor P4 and transistor N5 are input with the same signal A, and transistor P4 and transistor N5 are paired and stacked to form a layout group L4. For example, in F1 and F2, the source of transistor P4 is stacked with the source of transistor N5 to form a second electrode group G2, the drain of transistor P4 is stacked with the drain of transistor N5 to form a first electrode group G1, the channel region of transistor P4 is stacked with the channel region of transistor N5, and the two dummy gates of the two transistors are stacked to form a first dummy gate group D9, a second dummy gate group D10, a first dummy gate group D11, and a second dummy gate group D12.

[0149] For example, Figures 8 to 11 As shown, transistor P5 and transistor N4 are respectively connected to the two electrodes of transistor P3, and both transistor P5 and transistor N4 are transistors with a unit device width of 2. If F1 and F2 are included, the gates of transistor P5 and transistor N4 are input with the same signal B, and transistor P5 and transistor N4 are paired and stacked to form layout group L5. For example, in F1, the source of transistor P4 is stacked with the source of transistor N5 to form a first electrode group G1, the drain of transistor P4 is stacked with the drain of transistor N5 to form a second electrode group G2, the channel region of transistor P5 is stacked with the channel region of transistor N4, and the two dummy gates of the two transistors are stacked respectively to form a first dummy gate group D13 and a second dummy gate group D14; in F2, the source of transistor P5 is stacked with the drain of transistor N4 to form a first electrode group G1, the drain of transistor P5 is stacked with the source of transistor N4 to form a second electrode group G2, the channel region of transistor P5 is stacked with the channel region of transistor N4, and the two dummy gates of the two transistors are stacked respectively to form a first dummy gate group D15 and a second dummy gate group D16.

[0150] It should be noted that the embodiments of the present disclosure are not limited to Fig.11 The stacking relationship of the source and drain in the P-type transistor and the N-type transistor in the same layout group is shown. The stacking relationship of the source and drain can be set according to the electrical connection relationship of the transistors in the circuit.

[0151] For example, Fig.12 As shown, layout groups L1 to L5 are sorted and stacked according to the path sequence from the circuit input end to the output end. The stacking method of layout group L1 to layout group L5 can adopt the above 7A to 7C The stacking method shown.

[0152] For example, Fig.11 and Fig.12As shown, the gate group of layout group L1 is stacked with the first dummy gate group D3 of layout group L3, the second electrode group G2 of layout group L1 is stacked with the first electrode group G1 of layout group L3, the gate group of layout group L3 is stacked with the second dummy gate group D2 of layout group L1 and the second dummy gate group D10 of layout group L4, the second electrode group G2 of layout group L3 is stacked with the second electrode group G2 in F1 of layout group L4, the gate group in F1 of layout group L4 is stacked with the second dummy gate group D2 of layout group L3 The first electrode group G1 in F1 of the layout group L4 and the second electrode group G2 in F1 of the layout group L5 are stacked, the gate group in F1 of the layout group L5 and the first dummy gate group D9 of the layout group L4 and the first dummy gate group D15 of the layout group L5 are stacked, the first electrode group G1 in F1 of the layout group L5 and the first electrode group G1 in F2 of the layout group L5 are stacked, the gate group in F2 of the layout group L5 and the layout group The first dummy gate group D11 of L4 and the first dummy gate group D13 of layout group L5 are stacked, the second electrode group G2 in F2 of layout group L5 is stacked with the first electrode group G1 in F2 of layout group L4, the gate group in F2 of layout group L4 is stacked with the second dummy gate group D16 of layout group L5, the second electrode group G2 in F2 of layout group L4 is not stacked with the electrode groups of other layout groups, the second dummy gate group D12 of layout group L4 is stacked with the first dummy gate group D16 of layout group L2 5 stacking arrangement, the first pole group G1 in F1 of layout group L2 is not stacked with the pole groups of other layout groups, the gate group in F1 of layout group L2 is stacked with the second dummy gate group D8 of layout group L2, the second pole group G2 in F1 of layout group L2 is stacked with the second pole group G2 in F2 of layout group L2, the gate group in F2 of layout group L2 is stacked with the second dummy gate group D6 of layout group L2, and the first pole group G1 in F2 of layout group L2 is not stacked with the pole groups of other layout groups.

[0153] For example, Fig.12 As shown, after multiple layout groups are stacked, the number of virtual gates (i.e., virtual gate group D5 and virtual gate group D12) that are not stacked with any gate is small, for example, 1. The disclosed embodiment is for a certain circuit, and through the above layout design method, multiple layout groups can be arranged more compactly, the number of remaining virtual gates can be reduced, and the complete layout area can be saved. The disclosed embodiment can reduce the time spent on designing a COMS integrated circuit layout based on CFET through the above layout design method, reduce the number of redundant virtual gates to reduce additional area waste in layout design.

[0154] For example, Fig.12As shown, during the transistor pairing and stacking process, the connection positions of the transistors and the signal lines 410 and 420 have been fixed.

[0155] For example, Fig.12 and Fig.13 As shown, according to Figure 8 The connection relationship of the transistors in the circuit shown connects the transistors in the stacked layout group to form a complete layout corresponding to the circuit.

[0156] For example, Fig.12 and Fig.13 As shown, the signal line 410 is configured to transmit a VDD signal, and the signal line 420 is configured to transmit a VSS signal.

[0157] For example, Figures 11 to 13 As shown, the drain of transistor P2 is connected to the drain of transistor N2 through a connecting portion 501, and the drain of transistor P2 and the drain of transistor N2 are located at different layers, such as the layout groups are all arranged on the substrate, the drain of transistor P2 is located on the side of the drain of transistor N2 away from the substrate, the connecting portion 501 is located on the side of the drains of the two transistors away from the substrate, at least one insulating layer is arranged between the drain of transistor P2 and the drain of transistor N2, and at least one insulating layer is arranged between the drain of transistor P2 and the connecting portion 501, one end of the connecting portion 501 is connected to the drain of transistor P2 through a via 601 in the insulating layer between the connecting portion 501 and the drain of transistor P2, and the other end of the connecting portion 502 is connected to the drain of transistor N2 through a via 602 in the insulating layer between the connecting portion 502 and the drain of transistor N2.

[0158] For example, Figures 11 to 13 As shown, the gate group of layout group L1 (including transistor P2 and transistor N2) is connected to the signal input terminal B through the connection part 502. For example, the connection part 502 is located on the side of the gate group of layout group L1 away from the substrate, the signal input terminal B is located on the side of the connection part 502 away from the substrate, at least one insulating layer is provided between the gate group of layout group L1 and the connection part 502, at least one insulating layer is provided between the signal input terminal B and the connection part 502, one end of the connection part 502 is connected to the connection part 503 through a via 603 in the insulating layer between the connection part 502 and the connection part 503, the connection part 503 is connected to the gate group of layout group L1 through a via (the via overlaps with the via 603 and is not shown) in the insulating layer between it and the gate group of layout group L1, and the other end of the connection part 502 is connected to the signal input terminal B through a via 604 in the insulating layer between the connection part 502 and the signal input terminal B.

[0159] For example, Figures 11 to 13As shown, the gate group of layout group L3 (including transistor P1 and transistor N1) is connected to the signal input terminal A through the connection part 505. For example, the connection part 505 is located on the side of the gate group of layout group L3 away from the substrate, the signal input terminal A is located on the side of the connection part 505 away from the substrate, at least one insulating layer is provided between the gate group of layout group L3 and the connection part 505, at least one insulating layer is provided between the signal input terminal A and the connection part 505, one end of the connection part 505 is connected to the connection part 506 through a via 606 in the insulating layer between the connection part 505 and the connection part 506, the connection part 506 is connected to the gate group of layout group L3 through a via (overlapping with the via 606 and not shown) in the insulating layer between it and the gate group, and the other end of the connection part 505 is connected to the signal input terminal A through a via 607 in the insulating layer between the connection part 505 and the signal input terminal A.

[0160] For example, Figures 11 to 13 As shown, the gate group of layout group L4 (including transistor P4 and transistor N5) is connected to the signal input terminal A through connecting portion 505 and connecting portion 506. For example, connecting portion 505 and connecting portion 506 are located in different layers, such as connecting portion 506 can be located between connecting portion 505 and the substrate, connecting portion 505 is connected to connecting portion 506 through via 606 located in the insulating layer between connecting portion 505 and connecting portion 506, and connecting portion 506 is respectively connected to the two gate groups of layout group L4 through via 608 and via 614 in the insulating layer between connecting portion 506 and the gate group.

[0161] For example, Figures 11 to 13 As shown, the gate of layout group L5 (including transistor P5 and transistor N4) is connected to signal input terminal B through connection part 502 and connection part 503. For example, connection part 502 and connection part 503 are located in different layers, such as connection part 503 can be located between connection part 502 and substrate, connection part 502 is connected to connection part 503 through via 603 in the insulating layer between connection part 502 and connection part 503, and connection part 503 is respectively connected to two gate groups of layout group L5 through via 610 and via 612 in the insulating layer between connection part 503 and the gate group.

[0162] For example, Figures 11 to 13As shown, the drain of transistor N2 is connected to the gate group of F1 of layout group L2 through connection portion 504 and connection portion 507, and the drain of transistor N2 is connected to the gate group of F2 of layout group L2 through connection portion 504, connection portion 507, connection portion 512, and connection portion 514. For example, connection portion 507 and connection portion 504 are located at different layers, such as connection portion 507 is located on the side of connection portion 504 away from the substrate, and connection portion 507 is connected through via 605 in the insulating layer between connection portion 507 and connection portion 504; connection portion 507 and connection portion 512 are different layers, such as connection portion 507 is located on the side of connection portion 512 away from the substrate, and connection portion 507 is connected through via 620 in the insulating layer between connection portion 507 and connection portion 512; connection portion 512 and connection portion 514 are different layers, such as connection portion 514 can be located between connection portion 512 and the substrate The connecting portion 512 is connected through a via 622 in the insulating layer between the connecting portion 512 and the connecting portion 514. The connecting portion 514 and the gate group of the layout group L2 are located in different layers. For example, the connecting portion 514 is located on the side of the gate group away from the substrate. One end of the connecting portion 514 can be connected to the gate group through a via 623 in the insulating layer between the connecting portion 514 and the gate group, and the other end of the connecting portion 514 can be connected to the gate group through the via 622, the connecting portion 514, and a via (overlapping with the via 622 but not shown) in the insulating layer between the connecting portion 514 and the gate group.

[0163] For example, Figures 11 to 13 As shown, the drain of transistor P5 and the drain of transistor P4 can share the same metal layer, and the drain in F2 of transistor P5 is connected to the drain in F1 of transistor P5 through a connecting portion 515. The connecting portion 515 and the drain of transistor P5 are located in different layers. For example, the connecting portion 515 is located on the side of the drain away from the substrate, and the connecting portion 515 is respectively connected to the two drains through a via 609 and a via 613 in the insulating layer between the connecting portion 515 and the drain. For example, the connection portion 515 is connected to the source of the transistor P3 through the connection portion 510 and the connection portion 511. The connection portion 515 and the connection portion 510 are located at different layers. For example, the connection portion 510 can be located on the side of the connection portion 515 away from the substrate. The connection portion 515 is connected to the connection portion 510 through a via 615 in the insulating layer between the connection portion 515 and the connection portion 510; the connection portion 510 and the connection portion 511 are on different layers. The connection portion 510 can be located on the side of the connection portion 511 facing the substrate. The connection portion 510 is connected to the connection portion 511 through a via 616 in the insulating layer between the connection portion 510 and the connection portion 511; the connection portion 511 and the source of the transistor P3 are on different layers. For example, the connection portion 511 is located on the side of the source away from the substrate. The connection portion 511 is connected to the source of the transistor P3 through a via 621 in the insulating layer between the connection portion 511 and the source.

[0164] For example, Figures 11 to 13 As shown, the two drains of the transistor P3 and the drain of the transistor N4 are connected to the signal output terminal Z through the connection portion 508 and the connection portion 509 . For example, the connection portion 508 and the two drains of the transistor and the source of the transistor N4 are all located in different layers. For example, the connection portion 508 is located on the side of the drain away from the substrate, and the connection portion 508 is connected to the drain of the transistor N4 through a via 611 located in the insulating layer between the connection portion 508 and the drain. The connection portion 508 is respectively connected to the two drains of the transistor P3 through vias 619 and vias 624 in the insulating layer between the connection portion 508 and the drain; the connection portion 508 and the connection portion 509 are on different layers. For example, the connection portion 509 is located on the side of the connection portion 508 away from the substrate, and the connection portion 508 is connected to the connection portion 509 through a via 618 in the insulating layer between the connection portion 508 and the connection portion 509; the connection portion 509 and the signal output terminal Z are located in different layers. For example, the signal output terminal A is located on the side of the connection portion 509 away from the substrate, and the connection portion 509 is connected to the signal output terminal Z through a via 617 in the insulating layer between the connection portion 509 and the signal output terminal A.

[0165] For example, the above-mentioned connecting parts are all metal layers. For example, the substrate may include a silicon substrate, and the channel of the P transistor, the channel of the N transistor, the gate, the drain and the source of the transistor are all generated by epitaxial growth upward from the silicon substrate.

[0166] For example, the signal input terminals A and B in the figure may be vias in the insulating layer for exposing the connection part, and the signal line for transmitting the signal is connected to the connection part through the via. The signal line may be a metal layer farther away from the substrate side than the connection part.

[0167] Figures 8 to 13 The example shown takes a P-on-N FET structure (such as a structure where a P transistor is located above an N transistor) as an example. The unit height of the circuit layout is 4.5T, that is, the circuit layout includes at most four metal tracks arranged in parallel, such as connection portion 501, connection portion 503, connection portion 506 and connection portion 507, which can respectively represent the above four metal tracks.

[0168] For example, the extension line of connection part 508 coincides with the extension line of connection part 501, and the two can be regarded as two mutually insulated connection parts on the same track; the extension line of connection part 503 coincides with the extension of connection part 514, and the two can be regarded as two mutually insulated connection parts on the same track; the extension line of connection part 506 coincides with the extension of connection part 511, and the two can be regarded as two mutually insulated connection parts on the same track; connection part 507 overlaps with connection part 515 in a direction perpendicular to the substrate, and the two can be regarded as two mutually insulated connection parts on the same track.

[0169] Fig.14A Radix 8Booth Multiplexer (8-base Booth selector) circuit is provided according to at least one embodiment of the present disclosure. Fig.15 The circuit shown is a schematic diagram of a pairing of a first type transistor and a second type transistor. Fig.16 for Fig.14 Schematic diagram of multiple layout groups in the circuit shown, Fig.17 Based on Fig.14 The circuit shown is Fig.16 The schematic diagram of the arrangement of multiple layout groups is shown. Fig.18 for Fig.14 Complementary field-effect transistor (CFET) layout for the circuit shown.

[0170] For example, Figure 14 to Figure 15 As shown, the characteristic parameters of multiple transistors in the circuit are recorded.

[0171] For example, Figures 14 to 16 As shown, the circuit includes a P-type transistor and an N-type transistor, where "P" in the figure represents a P-type transistor and "N" in the figure represents an N-type transistor. The transistor includes a source and a drain, where "S" in the figure represents a source and "P" represents a drain. For example, the circuit only includes transistors with a unit device width of 1.

[0172] For example, Fig.14 As shown, the connection relationship between the source, drain and gate of each transistor and the signal input to each electrode of each transistor are recorded, such as the signal input to the gate of transistor N1 and transistor P7 is signal A1, the signal input to the gate of transistor P9, transistor N9, transistor P13 and transistor N12 is signal AOI, the signal input to the gate of transistor P8 and transistor N2 is signal A2, the signal input to the gate of transistor P5 and transistor N3 is signal B1, the signal input to the gate of transistor P10, transistor N10, transistor P11 and transistor N11 is signal S, the signal input to the gate of transistor P6 and transistor N4 is signal B2, the signal input to the gate of transistor P3 and transistor N5 is signal C1, the signal input to the gate of transistor P4 and transistor N6 is signal C2, the signal input to the gate of transistor P12 and transistor N13 is signal AOIS, the signal input to the gate of transistor P2 and transistor N8 is signal D2, and the signal input to the gate of transistor P1 and transistor N7 is signal D1.

[0173] For example, Figures 14 to 16 As shown, after the circuit is divided into a plurality of transistors, these transistors are paired and combined into a layout group according to the matching method of the first type transistor and the second type transistor.

[0174] For example, Fig.15As shown, the first type transistor and the second type transistor are paired according to the signal input to the drain of the first type transistor being the same as the signal input to the drain of the second type transistor, and the signal input to the gate of the first type transistor being the same as the signal input to the gate of the second type transistor. For example, the first type transistor and the second type transistor are transistor P7 and transistor N1, or transistor P9 and transistor N9, or transistor P13 and transistor N12, respectively.

[0175] For example, Figures 14 to 16 As shown, the drain of transistor P7 and the drain of transistor N1 are input with the same signal. For example, the drain of transistor P7 and the drain of transistor N1 are connected, and the gates of transistor P7 and transistor N1 are input with the same signal A1. Then, transistor P7 and transistor N1 are paired and stacked to form layout group L1.

[0176] For example, Figures 14 to 16 As shown, the drain of transistor P9 and the drain of transistor N9 are input with the same signal, such as the drain of transistor P9 and the drain of transistor N9 are connected, and the gates of transistor P9 and transistor N9 are input with the same signal AOI, then transistor P9 and transistor N9 are paired and stacked to form layout group L2.

[0177] For example, Figures 14 to 16 As shown, the drain of transistor P13 and the drain of transistor N12 are input with the same signal. For example, the drain of transistor P13 and the drain of transistor N12 are connected, and the gates of transistor P13 and transistor N12 are input with the same signal AOI. Then, transistor P13 and transistor N12 are paired and stacked to form layout group L3.

[0178] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method, transistor P8 and transistor N2 are connected to the two electrodes of transistor N1 respectively, and the gate of transistor P8 and the gate of transistor N2 are input with the same signal A2, then transistor P8 and transistor N2 are paired and stacked to form layout group L4.

[0179] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method, transistor P5 and transistor N3 are connected to the two electrodes of transistor P8 respectively, and the gate of transistor P5 and the gate of transistor N3 are input with the same signal B1, then transistor P5 and transistor N3 are paired and stacked to form layout group L5.

[0180] For example, Figures 14 to 16As shown, according to the above-mentioned chain matching method, transistor P10 and transistor N10 are connected to the two electrodes of transistor N9 respectively, and the gate of transistor P10 and the gate of transistor N10 are input with the same signal S, then the gate of transistor P10 and transistor N10 are paired and stacked to form layout group L6.

[0181] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method, the transistor P11 and the transistor N11 are connected to the two electrodes of the transistor N13 respectively, and the gate of the transistor P11 and the gate of the transistor N11 are input with the same signal S, then the transistor P11 and the transistor N11 are paired and stacked to form the layout group L7.

[0182] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method of the generated combination: transistor P6 and transistor N4 are chain-connected with transistor P8 and transistor, and the gate of transistor P6 and the gate of transistor N4 are input with the same signal B2, then transistor P6 and transistor N4 are paired and stacked to form layout group L8.

[0183] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method, transistor P3 and transistor N5 are chain-connected with transistor P6 and transistor P8, and the gate of transistor P3 and the gate of transistor N5 are input with the same signal C1, then transistor P3 and transistor N5 are paired and stacked to form layout group L9.

[0184] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method with the generated combination: transistor P4 and transistor N6 are chain-connected with transistor P6, transistor P8 and transistor N5, and the gates of transistor P4 and transistor N6 are input with the same signal C2, then transistor P4 and transistor N6 are paired and stacked to form layout group L10.

[0185] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method, transistor P12 and transistor N13 are connected to the two electrodes of transistor N11 respectively, and the gate of transistor P12 and the gate of transistor N13 are input with the same signal AOIS, then transistor P12 and transistor N13 are paired and stacked to form layout group L11.

[0186] For example, Figures 14 to 16As shown, according to the above-mentioned chain matching method of the generated combination: transistor P2 and transistor N8 are chain-connected with transistor P4, transistor P6, transistor P8 and transistor N7, and the gate of transistor P2 and the gate of transistor N8 are input with the same signal D2, then transistor P2 and transistor N8 are paired and stacked to form layout group L12.

[0187] For example, Figures 14 to 16 As shown, according to the above-mentioned chain matching method of the generated combination: transistor P1 and transistor N7 are chain-connected with transistor P3, transistor P5 and transistor P7, and the gate of transistor P1 and the gate of transistor N7 are input with the same signal D1, then transistor P1 and transistor N7 are paired and stacked to form layout group L13.

[0188] For example, Fig.16 As shown, the drain of transistor P1 is stacked with the drain of transistor N7, the source of transistor P1 is stacked with the source of transistor N7, the gate of transistor P1 is stacked with the gate of transistor N7, and the dummy gates of both are stacked to form layout group L13.

[0189] For example, Fig.16 As shown, the source of transistor P2 and the drain of transistor N8 are stacked, the drain of transistor P2 and the source of transistor N8 are stacked, the gate of transistor P1 and the gate of transistor N7 are stacked, and the dummy gates of the two are stacked to form layout group L12.

[0190] For example, Fig.16 As shown, the source of transistor P4 is stacked with the source of transistor N6, the drain of transistor P4 is stacked with the drain of transistor N6, the gate of transistor P4 is stacked with the gate of transistor N6, and the dummy gates of both are stacked to form layout group L10.

[0191] For example, Fig.16 As shown, the source of transistor P3 and the drain of transistor N5 are stacked, the drain of transistor P3 and the source of transistor N5 are stacked, the gate of transistor P3 and the gate of transistor N5 are stacked, and the dummy gates of both are stacked to form layout group L9.

[0192] For example, Fig.16 As shown, the source of transistor P7 is stacked with the source of transistor N1, the drain of transistor P7 is stacked with the drain of transistor N1, the gate of transistor P7 is stacked with the gate of transistor N1, and the dummy gates of both are stacked to form layout group L1.

[0193] For example, Fig.16As shown, the source of transistor P8 is stacked with the source of transistor N2, the drain of transistor P8 is stacked with the drain of transistor N2, the gate of transistor P8 is stacked with the gate of transistor N2, and the dummy gates of both are stacked to form layout group L4.

[0194] For example, Fig.16 As shown, the source of transistor P6 and the drain of transistor N4 are stacked, the drain of transistor P6 and the source of transistor N4 are stacked, the gate of transistor P6 and the gate of transistor N4 are stacked, and the dummy gates of both are stacked to form layout group L8.

[0195] For example, Fig.16 As shown, the source of transistor P5 is stacked with the source of transistor N3, the drain of transistor P5 is stacked with the drain of transistor N3, the gate of transistor P5 is stacked with the gate of transistor N3, and the dummy gates of both are stacked to form layout group L5.

[0196] For example, Fig.16 As shown, the source of transistor P9 and the drain of transistor N9 are stacked, the drain of transistor P9 and the source of transistor N9 are stacked, the gate of transistor P9 and the gate of transistor N9 are stacked, and the dummy gates of the two are stacked to form layout group L2.

[0197] For example, Fig.16 As shown, the source of transistor P10 is stacked with the source of transistor N10, the drain of transistor P10 is stacked with the drain of transistor N10, the gate of transistor P10 is stacked with the gate of transistor N10, and the dummy gates of both are stacked to form layout group L6.

[0198] For example, Fig.16 As shown, the source of transistor P12 is stacked with the source of transistor N13, the drain of transistor P12 is stacked with the drain of transistor N13, the gate of transistor P12 is stacked with the gate of transistor N13, and the dummy gates of both are stacked to form layout group L11.

[0199] For example, Fig.16 As shown, the source of transistor P13 and the drain of transistor N12 are stacked, the drain of transistor P13 and the source of transistor N12 are stacked, the gate of transistor P13 and the gate of transistor N12 are stacked, and the dummy gates of both are stacked to form layout group L3.

[0200] For example, Fig.16As shown, the source of transistor P11 is stacked with the source of transistor N11, the drain of transistor P11 is stacked with the drain of transistor N11, the gate of transistor P11 is stacked with the gate of transistor N11, and the dummy gates of both are stacked to form layout group L7.

[0201] It should be noted that the embodiments of the present disclosure are not limited to Fig.16 The stacking relationship of the source and drain in the P-type transistor and the N-type transistor in the same layout group is shown. The stacking relationship of the source and drain can be set according to the electrical connection relationship of the transistors in the circuit.

[0202] For example, Fig.17 As shown, layout groups L1 to L13 are sorted and stacked according to the path sequence from the circuit input end to the output end. The stacking method of layout groups L1 to L13 can adopt the above-mentioned 7A to 7C as well as Fig.12 The stacking method shown is the same and will not be repeated here.

[0203] For example, Fig.17 As shown, after the multiple layout groups are stacked, the number of virtual gates that are not stacked with any gate is small, for example, 4. For a certain circuit, the embodiment of the present disclosure can arrange multiple layout groups more compactly through the above layout design method, reduce the number of remaining virtual gates, and save the complete layout area. The embodiment of the present disclosure can reduce the time spent on designing a COMS integrated circuit layout based on CFET through the above layout design method, reduce the number of redundant virtual gates to reduce additional area waste in layout design.

[0204] For example, Fig.17 As shown, during the process of pairing and stacking the transistors, the connection positions of the transistors and the signal lines 410 and 420 have been fixed.

[0205] For example, according to Fig.14 The connection relationship of the transistors in the circuit shown will be as follows Fig.17 and Fig.18 The transistors in the stacked layout group are connected to form a complete layout corresponding to the circuit. Fig.18 The method of connecting the transistors in the layout group shown and the method of forming a complete layout corresponding to the circuit can be referred to Fig.12 and Fig.13 A method of forming a complete layout corresponding to a circuit is shown.

[0206] Figures 14 to 18 The example shown takes a P-on-N FET structure as an example, and the unit height of the circuit layout is 4.5T, that is, the circuit layout includes a maximum of 4 metal tracks.

[0207] Another embodiment of the present disclosure provides a circuit layout, which can be designed and formed by the above-mentioned layout design method. The circuit layout provided by the embodiment of the present disclosure has the characteristics of compact arrangement and avoiding redundant metal routing. The embodiment of the present disclosure is for a certain circuit, and in the circuit layout designed by the above-mentioned layout design method, the number of redundant dummy gates is reduced to save the complete layout area.

[0208] Fig.19 FIG. 1 is a schematic block diagram of a layout design system according to at least one embodiment of the present disclosure. Fig.19 As shown, the layout design system 1000 includes a recording unit 010 , a dividing unit 020 , a matching unit 030 and a connecting unit 040 .

[0209] The recording unit 010 is configured to record characteristic parameters of multiple transistors in the circuit. Each transistor includes at least two poles, and the characteristic parameters include at least the types of multiple transistors, the signals configured to be transmitted to each pole of each transistor, and the unit device width of each transistor. The recording unit 010 can implement step S101, and its specific implementation method can refer to the relevant description of step S101, which will not be repeated here.

[0210] The division unit 020 is configured to group the multiple transistors according to the unit device width of the multiple transistors, each group includes at least two transistors. The division unit 020 can implement step S102, and its specific implementation method can refer to the relevant description of step S102, which will not be repeated here.

[0211] The matching unit 030 is configured to match the transistors in each group according to the type of transistors in each group and the signal transmitted to each pole of each transistor to form a plurality of layout groups. The matching unit 030 can implement step S103, and its specific implementation method can refer to the relevant description of step S103, which will not be repeated here.

[0212] For example, the matching unit 030 can form a first layout group, a second layout group, a third layout group, and a fourth layout group in the plurality of layout groups by matching the first type transistor and the second type transistor. For example, the matching unit 030 can implement the first stage pairing, the second stage pairing, the third stage pairing, and the fourth stage pairing. For example, the matching unit 030 can implement Figure 3 The matching process is shown.

[0213] The connection unit 040 is configured to stack at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups according to the electrical connection relationship between the plurality of transistors in the circuit and the electrical connection relationship between the plurality of transistors and the signal line, and connect the transistors in the plurality of layout groups to form a complete layout corresponding to the circuit. The connection unit 040 can implement step S104, and its specific implementation method can refer to the relevant description of step S104, which will not be repeated here.

[0214] For example, the connection unit 040 can implement the stacking method of the first type transistor and the second type transistor in each layout group. For example, the connection unit 040 can implement the stacking method of different layout groups.

[0215] It should be noted that the recording unit 010, the division unit 020, the matching unit 030 and the connection unit 040 can be implemented by software, hardware, firmware or any combination thereof. For example, they can be implemented as an acquisition circuit and a control circuit respectively. The embodiments of the present disclosure do not limit their specific implementation methods.

[0216] It should be noted that in the embodiments of the present disclosure, the layout design system may include more or fewer circuits or units, and the connection relationship between the various circuits or units is not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and can be composed of analog devices according to circuit principles, or can be composed of digital chips, or in other applicable ways.

[0217] An embodiment of the present disclosure also provides a layout design device. Fig. 20 is a schematic block diagram of a layout design device according to at least one embodiment of the present disclosure. Fig. 20 As shown, the layout design device 2000 includes a processor 050 and a memory 060. The memory 060 includes one or more computer program modules 061. The one or more computer program modules 061 are stored in the memory 060 and are configured to be executed by the processor 050. The one or more computer program modules 061 include instructions for executing any step of the layout design method S101-S104 provided in at least one embodiment of the present disclosure. When the one or more computer program modules 061 are executed by the processor 050, one or more steps of the layout design method S101-S104 provided in at least one embodiment of the present disclosure can be executed. The memory 060 and the processor 050 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0218] For example, the processor 050 may be a central processing unit (CPU), a digital signal processor (DSP), or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 050 may be a general-purpose processor or a special-purpose processor, and may layout other components in the device 2000 to perform desired functions.

[0219] For example, the memory 060 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 061 may be stored on the computer-readable storage medium, and the processor 050 may run one or more computer program modules 061 to implement various functions of the layout design device 2000. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium. The specific functions and technical effects of the layout design device 2000 can refer to the description of the layout design method above, which will not be repeated here.

[0220] An embodiment of the present disclosure also provides a computer-readable storage medium. Fig.21 is a schematic block diagram of a computer-readable storage medium according to at least one embodiment of the present disclosure. Fig.21 As shown, the computer-readable storage medium 3000 stores computer program instructions 070, and when the computer program instructions 070 are executed by the processor, one or more steps in the layout design method described above are performed.

[0221] For example, the computer-readable storage medium 3000 may be any combination of one or more computer-readable storage media, such as a computer-readable storage medium comprising a computer-readable program code for recording characteristic parameters of a plurality of transistors in a circuit, another computer-readable storage medium comprising a computer-readable program code for grouping the plurality of transistors according to the unit device widths of the plurality of transistors, yet another computer-readable storage medium comprising a computer-readable program code for matching the transistors in each group according to the types of the transistors in each group and the signals, and yet another computer-readable storage medium comprising a computer-readable program code for stacking at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups and connecting the transistors in the plurality of layout groups according to the electrical connection relationship between the plurality of transistors in the circuit and the electrical connection relationship between the plurality of transistors and the signal lines.

[0222] Of course, the above-mentioned various program codes can also be stored in the same computer-readable medium, and the embodiments of the present disclosure are not limited to this. For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium to execute, for example, the layout design method provided in any embodiment of the present disclosure.

[0223] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the readable storage medium may also be Fig. 20 For the memory 060 in the example, the related description can be referred to the aforementioned content and will not be repeated here.

[0224] There are a few points to note:

[0225] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0226] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0227] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A layout design method, comprising: Recording characteristic parameters of a plurality of transistors in a circuit, wherein each transistor includes at least two electrodes, and the characteristic parameters include at least types of the plurality of transistors, signals configured to be transmitted to each electrode of each transistor, and a unit device width of each transistor; Grouping the plurality of transistors according to the unit device widths of the plurality of transistors, each group including at least two transistors; Matching the transistors in each group according to the type of the transistors in each group and the signal transmitted to each electrode of each transistor to form a plurality of layout groups; According to the electrical connection relationship between the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal line, at least a portion of the structure of at least some of the transistors in the multiple layout groups is stacked, and the transistors in the multiple layout groups are connected to form a complete layout corresponding to the circuit.

2. The layout design method according to claim 1, wherein: The types of the plurality of transistors include first-type transistors and second-type transistors, each transistor includes a gate, a first electrode and a second electrode, a signal configured to be input to the first electrode of the first-type transistor is a first signal, and a signal configured to be input to the first electrode of the second-type transistor is a second signal; Matching the transistors in each group according to the types of the transistors in each group and the signals transmitted to each electrode of each transistor includes comparing whether the first signal and the second signal are the same: when the first signal and the second signal are the same, performing first-stage pairing on the transistors of the first type and the transistors of the second type that meet the matching condition, wherein after completing the first-stage pairing on the first type transistors and the second type transistors, a plurality of first layout groups in the plurality of layout groups are formed; After the first stage pairing is completed, a second stage pairing is performed on at least a portion of the first type transistors and the second type transistors whose first signals and second signals are different.

3. The layout design method according to claim 2, wherein: The signal configured to be input into the second electrode of the first type transistor is a third signal, the signal configured to be input into the second electrode of the second type transistor is a fourth signal, the signal configured to be input into the gate of the first type transistor is a fifth signal, and the signal configured to be input into the gate of the second type transistor is a sixth signal; Performing first-stage pairing of transistors that meet matching conditions among the first-type transistors and the second-type transistors includes: Compare whether the third signal is the same as the fourth signal: If the third signal is the same as the fourth signal, pairing the first type transistors with the second type transistors one-to-one; If the third signal is different from the fourth signal, comparing the fifth signal to the sixth signal: If the fifth signal is the same as the sixth signal, pairing the first type transistors with the second type transistors one-to-one; If the fifth signal is different from the sixth signal, determine whether the potentials of the fifth signal and the sixth signal are opposite: if the potentials of the fifth signal and the sixth signal are opposite, perform one-to-one pairing of the first type transistor and the second type transistor; if the potentials of the fifth signal and the sixth signal are not opposite, the first type transistor and the second type transistor wait for the second stage pairing.

4. The layout design method according to claim 3, wherein: Performing a second-stage pairing on at least a portion of the remaining first-type transistors and the second-type transistors except the first layout group includes: comparing the fifth signal and the sixth signal configured as input to at least a portion of the first type transistors and the second type transistors remaining except the first layout group: If the fifth signal is the same as the sixth signal, and at least one of the first signal, the second signal, the third signal, and the fourth signal configured to be input to the transistors in the first layout group is the same as a corresponding signal configured to be input to at least a portion of the remaining first-type transistors and the second-type transistors except the first layout group, matching is performed on the remaining first-type transistors and the at least a portion of the second-type transistors except the first layout group to form a plurality of second layout groups among the plurality of layout groups; Determine whether the second electrode of at least one of the first type transistor and the second type transistor in the second layout group is electrically connected to the signal line: If the second electrodes of the transistors in the second layout group are not electrically connected to the signal line, the second stage pairing ends.

5. The layout design method according to claim 4, wherein: Performing second-stage pairing on at least part of the remaining first-type transistors and second-type transistors except the first layout group further includes: If the fifth signal is the same as the sixth signal, performing the second-stage pairing of the first-type transistor and the second-type transistor; If the fifth signal and the sixth signal are different, determining whether to perform the second-stage pairing according to whether the second electrode of the transistor is electrically connected to the signal line: If the second electrode of the transistor is electrically connected to the signal line, the first type transistor and the second type transistor are paired in the second stage; if the second electrode of the transistor is not electrically connected to the signal line, the second stage pairing ends.

6. The layout design method according to claim 4, wherein: Matching the transistors in each group according to the type of the transistors in each group and the signal transmitted to each electrode of each transistor also includes: After the second-stage pairing is completed, the transistors that are only configured to input the first type of transistor and the second signal that are configured to input the second type of transistor are the same are paired in the third stage to form multiple third layout groups among the multiple layout groups; or the transistors that are only configured to input the fifth signal of the first type of transistor and the sixth signal that are configured to input the second type of transistor are the same are paired in the third stage to form multiple third layout groups among the multiple layout groups.

7. The layout design method according to claim 6, wherein: Matching the transistors in each group according to the type of the transistors in each group and the signal transmitted to each electrode of each transistor also includes: After the third-stage pairing is completed, the remaining first-type transistors and second-type transistors that have not completed pairing in the first-stage pairing, the second-stage pairing, and the third-stage pairing are paired in the fourth stage to form a plurality of fourth layout groups in the plurality of layout groups; If after completing the fourth stage pairing, the plurality of transistors includes a remaining unpaired transistor, the transistor is recorded.

8. The layout design method according to any one of claims 1 to 3, wherein: Before stacking at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups, the layout design method further comprises arranging the plurality of layout groups according to the electrical connection relationship between the plurality of transistors in the circuit and the electrical connection relationship between the plurality of transistors and the signal line.

9. The layout design method according to claim 2 or 3, wherein: Each transistor further includes a channel region, the channel region is located between the first electrode and the second electrode, and the gate is stacked with the channel region; At least part of the transistors further include a dummy gate, wherein the dummy gate is located on a side of at least one of the first electrode and the second electrode away from the channel region; The first stage pairing of the transistors includes: stacking the channel region of the first type transistor with the channel region of the second type transistor, and stacking one of the first pole and the second pole of the first type transistor with one of the first pole and the second pole of the second type transistor to form a first pole group, and stacking the other of the first pole and the second pole of the first type transistor with the other of the first pole and the second pole of the second type transistor to form a second pole group.

10. The layout design method according to claim 9, wherein: In at least one first layout group, the dummy gate of the first type transistor is stacked with the dummy gate of the second type transistor to form a dummy gate group, and the dummy gate group includes a first dummy gate group and a second dummy gate group, and the first dummy gate group and the second dummy gate group are respectively located on a side of the first electrode group away from the channel region and a side of the second electrode group away from the channel region.

11. The layout design method according to claim 9, wherein: Stacking at least a portion of the structures of at least a portion of the transistors in the plurality of layout groups comprises: One of the first pole group and the second pole group in one layout group is stacked with one of the first pole group and the second pole group in another layout group, a dummy gate in one layout group is stacked with the channel region in another layout group, and a dummy gate in another layout group is stacked with the channel region in one layout group.

12. The layout design method according to claim 9, wherein: The first pole and the second pole both extend along a first direction, the signal line comprises a first power rail and a second power rail, the first power rail and the second power rail both extend along a second direction, and the first direction intersects the second direction; Connecting the transistors in the multiple layout groups to form a complete layout corresponding to the circuit includes: electrically connecting the first power rail to the second pole of the first type transistor in at least one layout group, and electrically connecting the second power rail to the second pole of the second type transistor in at least one layout group, wherein the first power rail and the second power rail are located on both sides of the first pole in the first direction.

13. A circuit layout, comprising a circuit layout designed by the layout design method according to any one of claims 1 to 12.

14. A layout design system, comprising: A recording unit configured to record characteristic parameters of a plurality of transistors in a circuit, wherein each transistor includes at least two electrodes, and the characteristic parameters at least include types of the plurality of transistors, a signal configured to be transmitted to each electrode of each transistor, and a unit device width of each transistor; a dividing unit configured to group the plurality of transistors according to the unit device widths of the plurality of transistors, each group including at least two transistors; A matching unit, configured to match the transistors in each group according to the type of the transistors in each group and the signal transmitted to each electrode of each transistor to form a plurality of layout groups; The connection unit is configured to stack at least a portion of the structures of at least a portion of the transistors in the multiple layout groups according to the electrical connection relationship between the multiple transistors in the circuit and the electrical connection relationship between the multiple transistors and the signal line, and connect the transistors in the multiple layout groups to form a complete layout corresponding to the circuit.

15. A layout design device, comprising: processor; and A memory, wherein the memory stores computer executable codes, and when the computer executable codes are run by the processor, the layout design method according to any one of claims 1 to 12 is executed.

16. A storage medium having executable codes stored thereon, wherein when the executable codes are executed by a processor, the processor executes the layout design method according to any one of claims 1 to 12.

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