A process for radiation hardening of silicon PNP transistors against total ionizing dose

Abstract

A total ionizing dose radiation hardening process for a silicon PNP transistor includes: selecting a silicon epitaxial wafer with a suitable doping concentration, and manufacturing a silicon-based PNP transistor through a four-time oxidation process, photolithography and impurity implantation of a base region and an emitter region, heavy metal doping, alloying, passivation, etching and other process flows. The present invention can significantly reduce the oxide-captured positive charge and interface state effects induced by ionizing radiation, can greatly enhance the total ionizing dose radiation resistance of a bipolar device, and can effectively improve the total ionizing dose radiation resistance of a silicon PNP transistor.

Description

Technical Field

[0001] The present invention belongs to the field of power electronics technology, in particular to a total ionizing dose radiation hardening process for silicon PNP transistors. The present invention relates to bipolar transistors and circuits, and the radiation resistance of bipolar devices is regulated by the manufacturing process of the devices. Background Art

[0002] During the spacecraft's in-orbit service, it will be affected by a large number of charged particles in the space radiation environment, mainly high-energy charged particles such as electrons, protons and heavy ions. These high-energy charged particles will produce ionizing radiation damage effects, displacement damage effects, ionization / displacement synergistic effects, etc. in the spacecraft's internal working systems, integrated circuits, and electronic components, posing a serious threat to the spacecraft's working systems. Integrated circuits and electronic components are the core of the spacecraft's normal operation, and their reliability and stability have become important indicators for the detection and evaluation of various types of spacecraft.

[0003] The experimental results show that different process transistors 60 Under Co-γ-ray irradiation, interface state traps and oxide charges are mainly generated. Interface state traps will lead to an increase in the recombination rate on the transistor surface, which will in turn lead to an increase in base current and degradation of current gain, while oxide charges have a certain inhibitory effect on the effect of interface states.

[0004] Since the birth of bipolar transistors, domestic and foreign scholars have conducted a lot of research on the characterization, mechanism, defect evolution model and radiation hardening of traditional bipolar transistors, and have achieved rich research results. However, there are few studies on the radiation hardening measures of bipolar transistors and the performance of the devices after hardening. Therefore, the research on the radiation damage mechanism of bipolar transistors has very important academic and application value. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a total ionizing dose radiation hardening process for a silicon PNP transistor. On the basis of the existing bipolar transistor and circuit manufacturing process, by controlling dry oxygen and wet oxygen processes and adopting a heavy metal doping method, a pre-recombination center is introduced. Under the same irradiation dose condition, the composite leakage current of the bipolar device is greatly reduced, the gain degradation is reduced, and the purpose of improving the radiation resistance of the bipolar device is achieved.

[0006] The technical solution of the present invention is:

[0007] A total ionizing dose radiation hardening process for a silicon PNP transistor comprises the following steps:

[0008] 1) Growing an epitaxial layer on a substrate;

[0009] 2) performing an oxidation treatment on the epitaxial layer to obtain an oxide layer;

[0010] 3) etching the first base region on the surface of the oxide layer obtained in step 2) by photolithography;

[0011] 4) N-type impurity implantation is performed at the first base region to form the first base region; secondary oxidation treatment is performed to grow an oxide layer;

[0012] 5) etching the emitter region on the upper surface of the oxide layer using a photolithography process;

[0013] 6) P-type impurity injection is used at the emitter region to form an emitter region; three oxidation processes are performed to grow an oxide layer;

[0014] 7) etching a second base region on the upper surface of the oxide layer by photolithography;

[0015] 8) Performing heavy metal doping treatment on the substrate surface;

[0016] 9) The silicon epitaxial wafer after heavy metal production is formed into a second base region by N-type impurity implantation, and subjected to four oxidation treatments to grow an oxide layer to obtain an oxidized silicon epitaxial wafer;

[0017] 10) etching the oxidized silicon epitaxial wafer into emitter region lead holes and base region lead holes by photolithography to lead out electrodes;

[0018] 11) The base and emitter are prepared on the oxide layer by metallization and photolithography;

[0019] 12) depositing a passivation layer to obtain a passivation layer serving as a protective layer;

[0020] 13) The substrate surface is thinned and polished to obtain a silicon PNP transistor.

[0021] Optionally, the oxidation treatment steps in step 2), step 4), step 6) and step 9) all adopt dry oxygen oxidation and wet oxygen oxidation to grow the oxide layer alternately in sequence, and the oxidation temperature is 950°C to 1100°C.

[0022] Optionally, the substrate in step 1) has a doping concentration greater than 8*10 18 cm -3 P-type semiconductor material.

[0023] Optionally, the epitaxial layer in step 1) has a doping concentration in the range of 2.2*10 15 ~3.4*10 15 cm -3 P-type semiconductor material.

[0024] Optionally, the N-type impurity particles are any one of nitrogen, phosphorus, arsenic and antimony, and the P-type impurity particles are any one of boron, aluminum, gallium and indium.

[0025] Optionally: In step 4), the N-type impurity injection dose is not less than 1*10 14 cm -2 .

[0026] Optionally: in the step 8), high temperature diffusion and sputtering of platinum is used for heavy metal doping, and the temperature range is 900° C. to 1000° C.

[0027] Optionally: in step 12), the material of the passivation layer is silicon dioxide, and the thickness of the silicon dioxide is greater than 0.2 μm.

[0028] Optionally, the etching in the photolithography process is dry etching or wet etching.

[0029] Optionally: the metallization is carried out by physical vapor deposition or chemical vapor deposition, and the metal material selected for metallization is any one or more of aluminum, copper, gold, titanium aluminum, aluminum copper, aluminum silicon copper, titanium nickel silver and titanium nickel gold.

[0030] The advantages of the present invention compared with the prior art are:

[0031] The total dose radiation resistant process technology of the present invention retains the traditional bipolar process technology, and the manufacturing process steps are very simple. The present invention can greatly reduce the oxide capture positive charge and interface state influence induced by ionizing radiation, and can greatly enhance the total dose radiation resistant performance of bipolar devices, which is of great significance for reducing the performance degradation of bipolar devices under total dose radiation, and has obvious advantages and broad application prospects in the application of bipolar device total dose radiation resistant reinforcement technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The relationship between the base current and the emitter junction voltage of bipolar devices with different processes before irradiation;

[0033] Figure 2 The relationship between the base current and the emitter junction voltage of bipolar devices with different processes after irradiation;

[0034] Figure 3 The deep level transient spectra of PNP low-power bipolar transistors with different processes before irradiation;

[0035] Figure 4 The deep level transient spectra of PNP low-power bipolar transistors with different processes after irradiation;

[0036] Figure 5 is a cross-sectional view of the silicon PNP transistor structure of the present invention;

[0037] Figure 6 It is a process flow chart of the present invention. DETAILED DESCRIPTION

[0038] The silicon PNP transistor is a vertically structured transistor with P+-PN-P+ silicon material as the main structure, and additional structures such as an oxide layer, a metal layer, and a passivation layer added to the main structure. An N+ type region is set in the N-type base region as the ohmic contact between the metal layer and the base region, and a P+ type guard ring is set on the periphery of the N-type base region, and a passivation layer is covered on the surface of the transistor except for the bonding point as a protective layer. The P+ type silicon substrate material on the back of the transistor is used as the collector lead-out terminal, and the base metal layer bonding point and the emitter metal layer bonding point on the front of the transistor are used as the base lead-out terminal and the emitter lead-out terminal, such as Figure 5 shown.

[0039] The present invention conducts irradiation tests on transistors that introduce the pre-recombination center process, analyzes the radiation damage mechanism of the transistor based on the test results, and provides a certain reference for the design of the radiation resistance reinforcement process. The bipolar device is a low-power PNP transistor. Without affecting the electrical performance parameters of the device, the original process is changed to introduce the pre-recombination center process. The relationship between the base current and the emitter junction voltage of the bipolar device with different processes is as follows: Figure 1 shown.

[0040] The specific process of the present invention is as follows:

[0041] 1) growing an epitaxial layer 2 on a substrate 1;

[0042] A high-doping concentration P-type semiconductor material is selected as the substrate 1. The thickness of the substrate 1 is about 450 μm, and the doping concentration of the substrate 1 is greater than 8*10 18 cm -3 The epitaxial layer 2 is a P-type semiconductor material with a low doping concentration. The doping concentration of the epitaxial layer 2 ranges from 2.2*10 15 ~3.4*10 15 cm -3 .

[0043] 2) performing an oxidation treatment on the epitaxial layer 2 to obtain an oxide layer; through the oxidation treatment, a high temperature oxidation process is used to grow the oxide layer 3 in a dry / wet oxygen mixed manner, with the purpose of using the grown oxide layer as a masking layer and a protective layer to achieve the diffusion of impurities in the first base region on the epitaxial layer 2 after photolithography;

[0044] 3) etching the first base region on the surface of the oxide layer obtained in step 2) by photolithography;

[0045] 4) N-type impurity injection is performed at the first base region to form the first base region 4; a high temperature oxidation process is performed to perform secondary oxidation in a dry / wet oxygen mixed manner to grow an oxide layer with a thickness of 0.6 μm; the N-type impurity particles are any one of nitrogen, phosphorus, arsenic and antimony. The N-type impurity injection dose is not less than 1*10 14 cm -2 The present invention improves the doping concentration of the base region on the basis of the prior art, and the N-type impurity injection dose is increased from 5*10 13 cm -2 Increased to 1*10 14 cm -2 .

[0046] 5) etching the emitter region on the upper surface of the oxide layer using a photolithography process;

[0047] 6) P-type impurity injection is used at the emitter region to form an emitter region 5; and a high-temperature oxidation process is used to perform three oxidation treatments in a dry / wet oxygen mixture to grow an oxide layer with a thickness of 0.2 μm; the P-type impurity particles are any one of boron, aluminum, gallium and indium.

[0048] 7) etching a second base region on the upper surface of the oxide layer by photolithography;

[0049] 8) Performing heavy metal doping treatment on the surface of substrate 1; specifically, high temperature diffusion sputtering of platinum is used for heavy metal doping at a temperature of 900° C. to 1000° C.

[0050] 9) The silicon epitaxial wafer after heavy metal production is formed into a high-concentration second base region 6 by N-type impurity implantation, and four oxidation treatments are performed by dry / wet oxygen mixed method using a high-temperature oxidation process to grow an oxide layer to obtain an oxidized silicon epitaxial wafer, the oxide layer thickness of which is 0.1 μm;

[0051] 10) etching the oxidized silicon epitaxial wafer into emitter region lead holes and base region lead holes by photolithography to lead out electrodes;

[0052] 11) The base 7 electrode and the emitter 8 electrode are prepared on the oxide layer by metallization and photolithography process; the metallization adopts physical vapor deposition or chemical vapor deposition such as evaporation and sputtering, and the metal layer can be any one or more of aluminum, copper, gold, titanium aluminum, aluminum copper, aluminum silicon copper, titanium nickel silver and titanium nickel gold.

[0053] 12) A passivation layer is deposited on the front side of the silicon epitaxial wafer with the electrode by PECVD to obtain a passivation layer 9 as a protective layer; the material of the passivation layer 9 is silicon dioxide, and the present invention removes the common silicon nitride layer, and the thickness of the silicon dioxide is greater than 0.2 μm.

[0054] 13) Thinning and polishing are performed on the surface of substrate 1, and die testing is completed to obtain a radiation-resistant silicon-based PNP transistor.

[0055] Each oxidation treatment step adopts a dry oxygen-wet oxygen-dry oxygen-wet oxygen-dry oxygen-wet oxygen-dry oxygen multilayer method to grow an oxide layer, and the oxidation temperature is 950° C. to 1100° C. The etching in the above-mentioned photolithography process adopts dry etching or wet etching.

[0056] The process optimized by the present invention 60 Co-γ-ray, the relationship between the base current and the emitter junction voltage of bipolar transistors of different processes is as follows Figure 2 As shown in the figure, it can be seen that under the same radiation absorption dose conditions, the radiation damage degree of the bipolar transistor is smaller and the radiation resistance is stronger when the pre-recombination center process is introduced. In order to further illustrate the influence of different processes on the radiation resistance of bipolar devices, Figure 4 The relationship between the change of deep energy level defects and the bipolar transistor manufacturing process under the same absorbed dose conditions is given. It can be seen from the figure that when the pre-recombination center is introduced, the transistor produces fewer deep energy level defects and the bipolar device has stronger radiation resistance.

[0057] 1. Based on the existing bipolar device process conditions, the specific process flow is as follows:

[0058] like Figure 6 As shown, select silicon wafer → primary oxidation → base region lithography → base region impurity injection → secondary oxidation → emitter region lithography → base region impurity injection → tertiary oxidation → base region lithography → heavy metal doping → base region impurity injection → fourth oxidation → lead hole lithography → alloying → electrode preparation → passivation → passivation layer etching → thinning → die testing.

[0059] Each oxidation process is improved by changing the oxidation process to a high-temperature oxidation process, adjusting the growth of the oxide layer by a dry / wet oxygen mixture, and reducing the introduction of H2 during the oxidation process; heavy metal doping is performed on the substrate surface, and heavy metal doping is controlled by high-temperature diffusion and sputtering of platinum to introduce pre-recombination centers.

[0060] 2. Carry out irradiation experiments to compare and analyze whether the radiation resistance performance of bipolar devices before and after process improvement meets the requirements;

[0061] 3. If the result obtained in step 2 does not meet the requirements, repeat the results of steps 1 and 2, and re-design the radiation-hardened device to finally obtain a new radiation-hardened device, such as Figure 5 shown.

[0062] Figure 1 The I of PNP low-power bipolar transistors of different processes before irradiation B With the emitter junction voltage VEB The changes in I of PNP low-power bipolar transistors of different processes can be seen. B All with V EB Increase with increase, and between different processes I B No significant changes.

[0063] Figure 2 is 60 I of PNP low-power bipolar transistors with different processes after Co-γ irradiation B With the emitter junction voltage V EB The changes in I of PNP low-power bipolar transistors of different processes can be seen. B All with V EB increases, and the I B The radiation dose increases significantly, so overall, the ionization effects are more sensitive to the original process transistors.

[0064] Figure 3 The deep energy level transient spectra of PNP type low-power bipolar transistors with different processes before irradiation are shown. It can be seen from the figure that there is no obvious change in the position and height of the characteristic peak of the deep energy level transient spectra of PNP type low-power bipolar transistors with different processes, which indicates that there are no deep energy level defects in PNP type low-power bipolar transistors with different processes before irradiation.

[0065] Figure 4 The deep level transient spectra of PNP-type low-power bipolar transistors under different processes after irradiation are shown. It can be seen from the figure that the defect peak position and height of PNP-type low-power bipolar transistors under different processes have changed. The DLTS defect peak intensity generated under the pre-recombination center process condition is smaller, and the DLTS defect peak concentration generated under the original process condition is significantly higher, and the defect energy level is closer to the center of the bandgap, causing the greatest impact. Both transistors of the two processes have interface state ionization defects after irradiation, but the introduction of the pre-recombination center process condition has few defects and stronger radiation resistance.

[0066] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0067] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A process for total ionizing dose radiation hardening of a silicon PNP transistor, characterized in that: include: Growing an epitaxial layer (2) on a substrate (1); Performing an oxidation treatment on the epitaxial layer (2) to obtain an oxide layer; A first base region is etched on the surface of the obtained oxide layer by using a photolithography process; Injecting N-type impurities into the first base region to form a first base region (4); performing secondary oxidation to grow an oxide layer; The position of the emission region is etched on the upper surface of the oxide layer by using a photolithography process; A P-type impurity injection method is used at the emitter region to form an emitter region (5); a three-step oxidation treatment is performed to grow an oxide layer; A second base region is etched on the upper surface of the oxide layer by using a photolithography process; Performing a heavy metal doping treatment on the surface of the substrate (1); The silicon epitaxial wafer after heavy metal production is formed into a second base region (6) by N-type impurity implantation, and subjected to four oxidation treatments to grow an oxide layer to obtain an oxidized silicon epitaxial wafer; The oxidized silicon epitaxial wafer is etched by photolithography to form an emitter region lead hole and a base region lead hole for leading out electrodes; A base electrode (7) and an emitter electrode (8) are prepared on the oxide layer by metallization and photolithography processes; Depositing a passivation layer to obtain a passivation layer (9) serving as a protective layer; Polishing the surface of the substrate (1) to obtain a silicon PNP transistor; The oxidation treatment adopts dry oxygen oxidation and wet oxygen oxidation to grow the oxide layer alternately, and the oxidation temperature is 950° C. to 1100° C.; The substrate (1) has a doping concentration greater than 8*10 18 cm -3 P-type semiconductor material; The doping concentration of the epitaxial layer (2) is in the range of 2.2*10 15 ~3.4*10 15 cm -3 P-type semiconductor material; The particles of the N-type impurities are any one of nitrogen, phosphorus, arsenic and antimony, and the particles of the P-type impurities are any one of boron, aluminum, gallium and indium; The N-type impurity injection dose is not less than 1*10 14 cm -2 .

2. The process for total ionizing dose radiation hardening of a silicon PNP transistor according to claim 1, characterized in that: The heavy metal doping is carried out by high temperature diffusion sputtering of platinum, and the temperature range is 900℃~1000℃.

3. The process for total ionizing dose radiation hardening of a silicon PNP transistor according to claim 1, characterized in that: The material of the passivation layer (9) is silicon dioxide, and the thickness of the silicon dioxide is greater than 0.2 μm.

4. The process for total ionizing dose radiation hardening of a silicon PNP transistor according to claim 1, characterized in that: The etching in the photolithography process adopts dry etching or wet etching.

5. The process for total ionizing dose radiation hardening of a silicon PNP transistor according to claim 1, characterized in that: The metallization is carried out by physical vapor deposition or chemical vapor deposition, and the metal material selected for metallization is any one or more of aluminum, copper, gold, titanium aluminum, aluminum copper, aluminum silicon copper, titanium nickel silver and titanium nickel gold.

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