Nonlinear Compensation Circuit for Input Buffer of Analog-to-Digital Converter

Abstract

The invention discloses a nonlinear compensation circuit of an analog-to-digital converter input buffer. In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the input buffer buffers the input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from a sampling switch; the common-mode buffer buffers the common-mode voltage of the analog-to-digital converter; the input end of a current replication circuit is connected to the gate end and the drain end of a top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common-mode buffer, so that the top transistor of the input buffer and the top transistor of the common-mode buffer form a current mirror; the sampling circuit is composed of a sampling switch and a sampling capacitor, the upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, the lower plate of the sampling capacitor is connected to the output of the common-mode buffer, and after the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to a reference voltage, the sampling capacitor maintains the voltage difference between the input signal and the common-mode signal, and sends it to a comparator.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, in particular to a nonlinear compensation circuit for an analog-to-digital converter input buffer. Background Art

[0002] Analog to Digital Converter (ADC) is one of the most important modules in System on Chip (SoC). It converts analog signals in nature into digital signals for easy processing by digital systems. Application fields such as 5G, millimeter wave communication and phased array radar urgently need high-speed and high-precision ADC. At present, the mainstream ADC structures are mainly the following: full parallel (Flash) ADC, pipeline (Pipelined) ADC, successive approximation register (SAR) ADC and Sigma-Delta ADC. Among these structures, SAR ADC has a relatively simple structure, low power consumption and good compatibility with advanced processes, while pipelined ADC can achieve high speed and high precision due to its pipeline advantages. In recent years, with the advancement of integrated circuit technology, the advantages of SAR ADC have gradually come into play. Therefore, the implementation structure of high-speed and high-precision ADC has evolved from traditional pipelined ADC to pipelined SAR ADC that combines pipelined ADC with SAR ADC. It can achieve high speed, high precision and low power consumption. The structural block diagrams of Pipelined ADC, SAR ADC, and Pipelined SAR ADC are shown below. Figure 1 , 2 , as shown in Figure 3.

[0003] Whether it is the traditional pipelined ADC or the newly emerged pipelined SAR ADC in recent years, when the sampling rate of the ADC continues to increase, especially when it reaches more than 500MSPS, the signal source driving the ADC chip will face huge challenges. Due to the parasitic inductance of the ADC package bonding wire and the parasitic capacitance related to the input, the kickback phenomenon caused by the continuous switching of the large signal of the sampling switch inside the ADC will seriously damage the input signal of the ADC, thereby significantly deteriorating the performance of the entire ADC. In order to solve the kickback problem of high-speed and high-precision ADCs, it is usually necessary to insert an on-chip input buffer before the sampling switch of the ADC, which can not only isolate the kickback of the sampling switch, but also reduce the driving requirements for the input signal source. In order to achieve high speed, the current implementation scheme of the input buffer is mainly a source follower structure. When it drives the sampling capacitor behind it, the instantaneous current flowing into the capacitor is completely related to the input signal, which makes the output signal of the buffer seriously nonlinearly distorted, thereby greatly reducing the linearity index of the entire ADC. One existing solution is to significantly increase the DC current of the source follower to reduce the proportion of nonlinear current, which will inevitably cause great power consumption. Another solution is to use a source follower structure based on compensation capacitors (such as Figure 4 The nonlinearity of the buffer can be suppressed to a certain extent, but its compensation capacitor is directly connected to the input, which will reduce the signal bandwidth of the ADC. At the same time, in order to ensure the flow of the compensation current, the DC power consumption of the source follower also needs to be increased.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0005] In view of the above shortcomings or defects of the prior art, a nonlinear compensation circuit for an analog-to-digital converter input buffer is provided, which compensates for the nonlinearity of part of the input buffer through the output of the common mode buffer in the ADC. The purpose of the present invention is achieved through the following technical solutions.

[0006] The nonlinear compensation circuit of the analog-to-digital converter input buffer includes,

[0007] An input buffer, which buffers an input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from the sampling switch, and the input buffer is a source follower structure, and the gate terminal and the drain terminal of the top transistor of the input buffer are short-circuited to generate a current that fluctuates with the input signal as an input current of the current replication circuit;

[0008] A common mode buffer, which buffers the common mode voltage of the analog-to-digital converter, and the common mode buffer is a source follower structure;

[0009] A current replicating circuit, wherein the input end is connected to the gate end and the drain end of the top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common mode buffer, so that the top transistor of the input buffer and the top transistor of the common mode buffer form a current mirror;

[0010] The sampling circuit is composed of a sampling switch and a sampling capacitor. The upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, and the lower plate of the sampling capacitor is connected to the output of the common-mode buffer. After the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to the reference voltage. The sampling capacitor maintains the voltage difference between the input signal and the common-mode signal and sends it to the comparator.

[0011] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the input buffer is connected to the sampling capacitor C through sampling switches S1, S2, S6, and S7 respectively. 1N , C 1P , C 2N , C 2P The upper plate samples the input signal.

[0012] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the common-mode buffer is connected to the lower plate of the sampling capacitor through sampling switches S3 and S8 to sample the common-mode voltage.

[0013] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the current replication circuit is a group of current mirrors.

[0014] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the sampling switch is a gate voltage bootstrap switch, the sampling capacitor is a split capacitor structure, and the two original sampling capacitors are split into four sampling capacitors C with equal capacitance. 1N , C 1P , C 2N , C 2P , its capacitance is half of the original sampling capacitor capacitance, and the total capacitance remains the same.

[0015] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the sampling circuit is divided into a sampling phase and a conversion phase. When in the sampling phase, the clock signal Φ s With Φ p is high level, the clock signal Φ c is low level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the output of the input buffer through switches S1, S2, S6, and S7, and the lower plate is connected to the output of the common-mode buffer through sampling switches S3 and S8.

[0016] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, when the sampling circuit is in the comparison stage, the clock signal Φ s With Φ p is low level, the clock signal Φ c is high level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the positive and negative reference levels REFP and REFN, and the lower plate of the sampling capacitor is connected to the comparator of the analog-to-digital converter to quantize the input signal on the sampling capacitor to obtain the corresponding digital code.

[0017] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the analog-to-digital converter is a pipeline successive approximation analog-to-digital converter. After the analog-to-digital converter completes input quantization, the pipeline successive approximation analog-to-digital converter causes the upper plate of the sampling capacitor to switch continuously, and the input of the comparator is the lower plate of the sampling capacitor, which returns to the common mode level, and then enters the sampling stage of the next cycle to repeat the operation.

[0018] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the input of the comparator of the pipeline successive approximation analog-to-digital converter is the voltage difference between the upper and lower plates of the sampling capacitor, which is the difference between the output of the input buffer and the output of the common mode buffer.

[0019] In the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the input buffer includes the input signal and the nonlinear component of the input signal, the output of the common-mode buffer includes the common-mode signal and the nonlinear component of the input signal, the input signal is obtained by taking the difference between the upper and lower plate voltages of the sampling capacitor, and the nonlinear calibration of the input buffer is completed.

[0020] Beneficial Effects

[0021] The present invention transfers the nonlinear component of the input signal generated in the input buffer to the common-mode buffer through the current replication circuit, and connects the two to the upper and lower plates of the sampling capacitor respectively, thereby eliminating the nonlinearity of part of the input signal; the present invention does not connect the compensation capacitor to the input signal path, thereby avoiding the attenuation of the input bandwidth caused by the compensation capacitor; the present invention does not use the compensation capacitor, thereby avoiding the circuit area overhead caused by the current compensation path. The common-mode buffer used in the invention is required by the circuit, and the circuit area overhead is much smaller than the area overhead caused by the current compensation path.

[0022] The above description is only an overview of the technical solution of the present invention. In order to make the technical means of the present invention clearer and to enable those skilled in the art to implement it according to the contents of the specification, and to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described below by way of example. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] By reading the detailed description of the preferred specific embodiments below, various other advantages and benefits of the present invention will become clear to those of ordinary skill in the art. The drawings in the specification are only for the purpose of illustrating the preferred embodiments and are not considered to be limitations of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work. Moreover, the same reference numerals are used to represent the same components throughout the drawings.

[0024] In the attached picture:

[0025] Figure 1 It is a structural block diagram of Pipelined ADC in the prior art;

[0026] Figure 2 It is a block diagram of the SAR ADC structure of the prior art;

[0027] Figure 3 It is a structural block diagram of the Pipelined SAR ADC of the prior art;

[0028] Figure 4 The structure diagram of the input buffer based on compensation capacitor;

[0029] Figure 5 It is a structural schematic diagram of a nonlinear compensation circuit of an analog-to-digital converter input buffer of the present invention;

[0030] Figure 6 A timing diagram of a nonlinear compensation circuit of an analog-to-digital converter input buffer of the present invention;

[0031] Figure 7 A schematic diagram of the FFT result output by the nonlinear compensation circuit using the analog-to-digital converter input buffer of the present invention;

[0032] Figure 8 The schematic diagram of the FFT result outputted by the common input buffer for comparison;

[0033] Fig. 9 The figure is a schematic diagram comparing the SFDR output of the input buffer of the present invention and that of a common input buffer under different input frequencies.

[0034] The present invention is further explained below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0035] The following will refer to the attached Figures 1 to 9 Specific embodiments of the present invention are described in more detail. Although specific embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0036] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present invention, but the description is based on the general principles of the specification and is not intended to limit the scope of the present invention. The scope of protection of the present invention shall be determined by the attached claims.

[0037] To facilitate understanding of the embodiments of the present invention, several specific embodiments will be further explained below with reference to the accompanying drawings, and each of the accompanying drawings does not constitute a limitation on the embodiments of the present invention.

[0038] like Figure 5 to Figure 6 As shown, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes:

[0039] An input buffer, which buffers an input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from the sampling switch, and the input buffer is a source follower structure, and the gate terminal and the drain terminal of the top transistor of the input buffer are short-circuited to generate a current that fluctuates with the input signal as an input current of the current replication circuit;

[0040] A common mode buffer, which buffers the common mode voltage of the analog-to-digital converter, and the common mode buffer is a source follower structure;

[0041] A current replicating circuit, wherein the input end is connected to the gate end and the drain end of the top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common mode buffer, so that the top transistor of the input buffer and the top transistor of the common mode buffer form a current mirror;

[0042] The sampling circuit is composed of a sampling switch and a sampling capacitor. The upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, and the lower plate of the sampling capacitor is connected to the output of the common-mode buffer. After the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to the reference voltage. The sampling capacitor maintains the voltage difference between the input signal and the common-mode signal and sends it to the comparator.

[0043] The present invention utilizes a common-mode buffer in a high-speed and high-precision ADC as a compensation circuit to copy the current of an input buffer to the common-mode buffer, wherein the output of the input buffer is connected to an upper plate of a sampling capacitor of the ADC, and the output of the common-mode buffer is connected to a lower plate of the sampling capacitor; a current source of the input buffer and a current source of the common-mode buffer form a current mirror structure to ensure that consistent nonlinear fluctuations are generated on the upper and lower plates of the sampling capacitor when a sampling switch is switched, thereby compensating for the nonlinearity of the input buffer to a large extent and significantly improving the linearity of the input buffer of the high-speed and high-precision ADC.

[0044] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the input buffer is connected to the sampling capacitor C through sampling switches S1, S2, S6, and S7 respectively. 1N , C 1P , C 2N , C 2P The upper plate samples the input signal.

[0045] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the common-mode buffer is connected to the lower plate of the sampling capacitor through sampling switches S3 and S8 to sample the common-mode voltage.

[0046] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the current replication circuit is a group of current mirrors.

[0047] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the sampling switch is a gate voltage bootstrap switch, the sampling capacitor is a split capacitor structure, and the two original sampling capacitors are split into four sampling capacitors C with equal capacitance. 1N , C 1P , C 2N , C 2P , its capacitance is half of the original sampling capacitor capacitance, and the total capacitance remains the same.

[0048] In the preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the sampling circuit is divided into a sampling phase and a conversion phase. When in the sampling phase, the clock signal Φ s With Φ p is high level, the clock signal Φ c is low level, the sampling capacitor C1N , C 1P , C 2N , C 2P The upper plate is connected to the output of the input buffer through switches S1, S2, S6, and S7, and the lower plate is connected to the output of the common-mode buffer through sampling switches S3 and S8.

[0049] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, when the sampling circuit is in the comparison stage, the clock signal Φ s With Φ p is low level, the clock signal Φ c is high level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the positive and negative reference levels REFP and REFN, and the lower plate of the sampling capacitor is connected to the comparator of the analog-to-digital converter to quantize the input signal on the sampling capacitor to obtain the corresponding digital code.

[0050] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the analog-to-digital converter is a pipeline successive approximation analog-to-digital converter. After the analog-to-digital converter completes input quantization, the pipeline successive approximation analog-to-digital converter causes the upper plate of the sampling capacitor to continuously switch, and the input of the comparator is the lower plate of the sampling capacitor, which returns to the common mode level, and then enters the sampling phase of the next cycle to repeat the operation.

[0051] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the input of the comparator of the pipeline successive approximation analog-to-digital converter is the voltage difference between the upper and lower plates of the sampling capacitor, which is the difference between the output of the input buffer and the output of the common-mode buffer.

[0052] In a preferred embodiment of the nonlinear compensation circuit of the analog-to-digital converter input buffer, the output of the input buffer includes the input signal and the nonlinear component of the input signal, the output of the common-mode buffer includes the common-mode signal and the nonlinear component of the input signal, the input signal is obtained by subtracting the upper and lower plate voltages of the sampling capacitor, and the nonlinear calibration of the input buffer is completed.

[0053] For a better understanding, Figure 5 to Figure 6 As shown, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes:

[0054] Input buffer (differential), which buffers the input outside the ADC chip (output of the signal source), isolates the input signal source from the sampling switch, and improves the driving capability of the input signal. Its structure is a source follower structure, and the gate terminal and the drain terminal of the top transistor are short-circuited to generate a current that fluctuates with the input signal;

[0055] The common-mode buffer buffers the common-mode voltage (reference output) of the ADC to improve the ability of the common-mode voltage to drive a larger sampling capacitor. The structure is also a source-follower structure, and the gate terminal of the top transistor is connected to the output of the current replica circuit.

[0056] A current replicating circuit, wherein the input end is connected to the gate end and the drain end of the top current source of the input buffer, and the output end is connected to the gate end of the top current source of the common mode buffer, so that the top current source of the input buffer and the top current source of the common mode buffer form a current mirror, thereby forming a current replicating circuit;

[0057] The sampling circuit consists of a sampling switch and a sampling capacitor. The upper plate of the capacitor is connected to the output of the input buffer through the switch, and the lower plate of the capacitor is connected to the output of the common-mode buffer. After the switch is disconnected, the upper plate of the capacitor is connected to the reference voltage. The sampling capacitor will maintain the voltage difference between the input signal and the common-mode signal and send it to the comparator. The output of the input buffer (differential) is connected to the sampling capacitor C through sampling switches S1, S2, S6, and S7 respectively. 1N , C 1P , C 2N , C 2P The upper plate of the input buffer is used to sample the input signal. The output of the common-mode buffer is connected to the lower plate of the sampling capacitor through switches S3 and S8 to sample the common mode. The current replication circuit is a set of current mirrors, the input of which comes from the top current source of the input buffer (differential), and the output is connected to the top current source of the common-mode buffer.

[0058] In one embodiment, the sampling circuit includes a sampling capacitor and a sampling switch, wherein the sampling switch is mostly a gate voltage bootstrap switch. The sampling capacitor adopts a split capacitor structure, that is, the original two sampling capacitors (differential) are split into four C with equal capacitance. 1N , C 1P , C 2N , C 2P , the capacitance is half of the original sampling capacitor capacitance, and the total capacitance remains the same. The sampling circuit is divided into the sampling stage and the conversion stage. When in the sampling stage, the clock signal Φ s With Φ p is high level, the clock signal Φ c is low level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the output of the input buffer (differential) through switches S1, S2, S6, and S7, and the lower plate is connected to the output of the common-mode buffer through switches S3 and S8. When in the comparison phase, the clock signal Φ s With Φ p is low level, the clock signal Φc is high level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the positive and negative reference levels REFP and REFN, and at the same time, the lower plate of the sampling capacitor can be connected to the comparator of the ADC to quantize the input signal on the sampling capacitor and obtain the corresponding digital code. Here, the pipeline successive approximation ADC is taken as an example. After the ADC completes the input quantization, the upper plate of the sampling capacitor is continuously switched due to the pipeline successive approximation ADC, so that the input of the comparator, that is, the lower plate of the sampling capacitor, returns to the common mode level. Then enter the sampling stage of the next cycle, repeat the above operation, and the input of the pipeline successive approximation ADC quantization is the voltage difference between the upper and lower plates of the sampling capacitor, that is, the difference between the output of the input buffer and the output of the common mode buffer. The output of the input buffer includes the input signal and the nonlinear component of the input signal, and the output of the common mode buffer includes the common mode signal and part of the nonlinear component of the input signal. When the difference between the upper and lower plate voltages of the sampling capacitor is calculated, a relatively pure input signal can be obtained, and the nonlinear compensation of the input buffer is completed.

[0059] To further understand the present invention, in one embodiment, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes an input buffer (differential), a common-mode buffer, a current replication circuit and a sampling circuit, wherein the current replication circuit is composed of a top current source of the input buffer (differential) and a top current source of the common-mode buffer.

[0060] In one embodiment, the sampling capacitor C 1N , C 1P , C 2N , C 2P The plates are connected to the output of the input buffer and the output of the common-mode buffer respectively. At the same time, the top current source of the common-mode buffer and the top current source of the input buffer form a current mirror structure. The current flowing through the common-mode buffer will contain the nonlinear current component of the input buffer that fluctuates with the input signal. Then, it is connected to the sampling capacitor through the main input tube of the common-mode buffer to convert the current information into voltage information and store it in the sampling capacitor C. 1N , C 1P , C 2N , C 2P At this time, the voltage information of the upper plate of the sampling capacitor also contains the nonlinear component brought by the input buffer. Since the nonlinear component of the input buffer exists on both the upper and lower plates of the sampling capacitor, the two can offset each other, thereby obtaining a relatively pure input signal and realizing compensation for the nonlinearity of the input buffer.

[0061] In one embodiment, Figure 5As shown, the nonlinear compensation circuit of the analog-to-digital converter input buffer includes an input buffer (differential), a common-mode buffer, a current mirror and a sampling circuit. The current mirror is composed of the top current source of the input buffer (differential) and the top current source of the common-mode buffer.

[0062] In one embodiment, Figure 5 As shown, transistors M1, M7, M9, M4, M8, M 13 It forms an input buffer (differential), in which M7 and M8 are the main input pair, and transistors M2, M5, M 10 , M3, M6, M 12 A common-mode buffer is formed, and M5 and M6 are the main input tubes. Among them, M1 (M4) and M3 (M2) of the input buffer form a current mirror. The current flowing through the input buffer is copied through the current mirror structure, thereby generating the same nonlinear component to offset the nonlinearity of the input buffer. The sampling circuit consists of switches S1, S2, S3, S6, S7, S8 and capacitor C 1N , C 1P , C 2N , C 2P composition.

[0063] In one embodiment, the working sequence of the high-speed and high-precision ADC input buffer using the current copy structure for nonlinear compensation of the present invention is as follows: Figure 6 As shown. Each cycle is divided into a sampling phase φ s and the conversion phase φ c .

[0064] In one embodiment, it is assumed that the input buffer operates in the sampling phase, that is, the clock signal φ s ,φ p is high level, the clock signal φ c When it is low level, switches S1, S2, S3, S6, S7, and S8 are turned on, and C 1N , C 1P , C 2N , C 2P The upper plate of the is connected to the output of the input buffer, and the lower plate is connected to the output of the common-mode buffer. Assume that the input signal is V IN 、V IP , the output signal is V TOPN , V TOPP , the current flowing through the input buffer (differential) is I IP ,I IN , then the relationship is:

[0065]

[0066] Where: V th , μ n, C ox and W / L are the threshold voltage, electron mobility, gate oxide capacitance and width-to-length ratio of the transistor, respectively.

[0067] The current flowing through the input buffer mainly consists of two parts. One part is the buffer’s own bias current I b , part of which is the current I flowing through the sampling capacitor when the circuit is in the sampling stage cp ,I cn , which is also the main source of nonlinearity. Its relationship is:

[0068]

[0069] The input of the common-mode buffer is V CM , the outputs are V CMOUTP 、V CMOUTN , the current flowing through the common-mode buffer is I CMP ,I CMN , the relationship is:

[0070]

[0071] Since the current flowing through the common-mode buffer in the circuit comes from the top current mirror structure, the frequency of the current is consistent with the frequency of the input signal and is at a higher frequency, and the area of ​​the transistor in the current replication path is large, resulting in a large parasitic capacitance, which will cause the common-mode buffer current to have a certain phase lag compared to the input current. In order to overcome the deviation caused by the current phase shift, we can perform differential crossover on the current of the common-mode buffer, so the common-mode buffer current I CMP ,I CMN The input buffer current I IP ,I IN The relationship is as follows:

[0072]

[0073] In addition, during the sampling phase, the current I flowing through the sampling capacitor cp ,I cn , ideally its value is:

[0074]

[0075] When the input signal is a sinusoidal signal, assuming the amplitude is A, the relationship between current and voltage is:

[0076]

[0077] At this time, the current relationship of the input buffer is:

[0078]

[0079] At the end of the sampling phase, the voltage difference stored on the capacitor is the output V of the input buffer. TOPN (V TOPP ) and the common-mode buffer output V CMOUTN (V CMOUTP ), the voltage value is:

[0080]

[0081] Substituting into equations (4) and (7), we can obtain that when the phase shift in the current mirror satisfies the following conditions:

[0082]

[0083] The voltage difference across the capacitor is:

[0084]

[0085] At this point, it can be seen that the voltage difference between the upper and lower plates of the capacitor is the difference between the input signal and the common mode. At this point, the nonlinearity of the input buffer can be completely eliminated. However, in actual circuit implementation, since the phase shift of the current mirror replica circuit changes with frequency, the nonlinearity of the input signal cannot be completely eliminated, but it can still greatly improve the nonlinearity of the input signal.

[0086] After sampling, the conversion phase begins, that is, the clock signal φ s ,φ p is low level, the clock signal φ c When the level is high, switches S4, S5, S9, S 10 On, C 1N , C 1P , C 2N , C 2P The upper plate of the capacitor is connected to the positive and negative reference voltages REFP and REFN. At this time, the upper plate of the capacitor can be connected to the comparator for comparison to quantize the input signal. After the pipeline successfully approximates the ADC conversion, it enters the sampling stage of the next cycle and repeats the above operations.

[0087] When the replica circuit structure of the present invention is used to perform nonlinear compensation on the high-speed and high-precision ADC input buffer, assuming that the parasitic inductance of the package bondwire is 2nH, the power supply voltage is 1.8V, the input signal frequency is 748Mhz, the input swing is 1.6Vpp, the total sampling capacitance (single-ended) is 280FF, the sampling frequency is 2Ghz, that is, the sampling time is 250ps, at this time, the total current of the input buffer and the common-mode buffer is 9.7mA, and the difference between the output of the input buffer and the output of the common-mode buffer is subjected to fast Fourier transform (FFT) to obtain a power spectrum density diagram, as shown in FIG. Figure 7As shown in the figure, it can be seen that the linearity index of the output signal, namely the spurious-free dynamic range (SFDR), is 82.38dB.

[0088] In order to compare the performance of the present invention with that of a common input buffer, a common input buffer circuit is designed as a comparison circuit under the same input conditions and with the same circuit area, and its structure is a source follower structure. At this time, the power supply current of the common input buffer is about 14 mA. When the output of the input buffer is subjected to a fast Fourier transform (FFT) to obtain a power spectrum density diagram, as shown in FIG. Figure 8 As shown. It can be seen that the linearity index of the output signal, namely the spurious-free dynamic range (SFDR), is 61.37dB. In order to further illustrate the universality of the calibration method of the present invention, at a sampling frequency of 2Ghz, at different input frequencies, the difference between the output of the input buffer and the output of the common mode buffer is subjected to a fast Fourier transform, and the output SFDR is compared with that of the ordinary input buffer, as shown in FIG. Fig. 9 As shown in the figure, it can be seen that the calibration method can still improve the linearity of the input buffer at different input frequencies.

[0089] In summary, the nonlinear compensation circuit of the analog-to-digital converter input buffer proposed in the present invention effectively improves the nonlinearity of the input buffer without increasing the power consumption and area overhead of the input buffer, thereby improving the performance of the ADC.

[0090] Although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments and application fields, and the above specific embodiments are only illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present invention, all of which belong to the protection of the present invention.

Claims

1. A nonlinear compensation circuit for an analog-to-digital converter input buffer, characterized in that: These include, An input buffer, which buffers an input signal of an input signal source outside the analog-to-digital converter to isolate the input signal source from the sampling switch, and the input buffer is a source follower structure, and the gate terminal and the drain terminal of the top transistor of the input buffer are short-circuited to generate a current that fluctuates with the input signal as an input current of the current replication circuit; A common mode buffer, which buffers the common mode voltage of the analog-to-digital converter, and the common mode buffer is a source follower structure; A current replicating circuit, wherein the input end is connected to the gate end and the drain end of the top transistor of the input buffer, and the output end is connected to the gate end of the top transistor of the common mode buffer, so that the top transistor of the input buffer and the top transistor of the common mode buffer form a current mirror; The sampling circuit is composed of a sampling switch and a sampling capacitor. The upper plate of the sampling capacitor is connected to the output of the input buffer through the sampling switch, and the lower plate of the sampling capacitor is connected to the output of the common-mode buffer. After the sampling switch is disconnected, the upper plate of the sampling capacitor is connected to the reference voltage. The sampling capacitor maintains the voltage difference between the input signal and the common-mode signal and sends it to the comparator. The sampling switch is a gate voltage bootstrap switch, and the sampling capacitor is a split capacitor structure. Two original sampling capacitors are split into four sampling capacitors C with equal capacitance. 1N , C 1P , C 2N , C 2P , its capacitance is half of the original sampling capacitor capacitance, the total capacitance remains the same, the sampling circuit is divided into the sampling stage and the conversion stage, Φ s , Φ p , Φ c are clock signals. When in the sampling stage, Φ s With Φ p is high level, Φ c is low level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the output of the input buffer through switches S1, S2, S6, and S7, and the lower plate is connected to the output of the common-mode buffer through sampling switches S3 and S8. When the sampling circuit is in the comparison stage, the clock signal Φ s With Φ p is low level, the clock signal Φ c is high level, the sampling capacitor C 1N , C 1P , C 2N , C 2P The upper plate is connected to the positive and negative reference levels REFP and REFN, and the lower plate of the sampling capacitor is connected to the comparator of the analog-to-digital converter to quantize the input signal on the sampling capacitor to obtain the corresponding digital code.

2. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that: The output of the input buffer is connected to the sampling capacitor C through sampling switches S1, S2, S6, and S7 respectively. 1N , C 1P , C 2N , C 2P The upper plate samples the input signal.

3. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that: The output of the common-mode buffer is connected to the lower plate of the sampling capacitor through sampling switches S3 and S8 to sample the common-mode voltage.

4. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that: The current replication circuit is a group of current mirrors.

5. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 1, characterized in that: The analog-to-digital converter is a pipelined successive approximation analog-to-digital converter. After the analog-to-digital converter completes quantization of the input, the pipelined successive approximation analog-to-digital converter causes the upper plate of the sampling capacitor to switch continuously, and the input of the comparator is the lower plate of the sampling capacitor, which returns to the common mode level, and then enters the sampling phase of the next cycle to repeat the operation.

6. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 5, characterized in that: The input of the comparator of the pipelined successive approximation analog-to-digital converter is the voltage difference between the upper and lower plates of the sampling capacitor, which is the difference between the output of the input buffer and the output of the common-mode buffer.

7. The nonlinear compensation circuit of the analog-to-digital converter input buffer according to claim 6, characterized in that: The output of the input buffer includes the input signal and the nonlinear component of the input signal. The output of the common-mode buffer includes the common-mode signal and the nonlinear component of the input signal. The input signal is obtained by taking the difference between the upper and lower plate voltages of the sampling capacitor to complete the nonlinear calibration of the input buffer.

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