A configurable fast Fourier transform circuit with sequential architecture

Abstract

The present invention belongs to the field of digital signal processing, and specifically provides a configurable fast Fourier transform circuit with a sequential architecture, which is used to solve the problems of high resource consumption and high power consumption of the existing fast Fourier transform circuit structure with configurable points. The present invention is based on a sequential single-stage feedback FFT operation structure with registers as storage units, including: a butterfly operation unit module, a register storage unit with a depth dimension of 2N points, a configurable address generation module and a reverse module; the configurable address generation module performs mode configuration according to the number of points N of the fast Fourier transform, and then generates a corresponding address value to realize the FFT operation with configurable points; the present invention greatly reduces the use of operation unit resources, and reduces the power consumption and resource consumption of the FFT system; at the same time, the present invention optimizes the multiplier structure in the butterfly operation unit module, adopts booth coding to improve the delay of the multiplier path, and improves the clock operating frequency and operation speed.

Description

Technical Field

[0001] The invention belongs to the field of digital signal processing, and specifically provides a configurable fast Fourier transform circuit with a sequential architecture. Background Art

[0002] Fast Fourier transform is widely used in digital imaging, wireless communication, speech recognition, radar signal processing and other fields. Currently, in radar imaging technology, image recognition and other technologies, it is necessary to study specialized fast Fourier transform circuits to meet the requirements of high data throughput, high precision, and real-time operation.

[0003] Common circuit architectures of fast Fourier transform circuits include sequential iterative architecture, pipeline architecture, and parallel architecture. To implement configurable FFT operation functions, parallel architecture or pipeline architecture is used. Figure 1 As shown, the configurable radix-4 frequency extraction FFT adopts a parallel pipeline architecture and realizes variable-length FFT operations by controlling the selector; the traditional configurable FFT circuit works according to the following principles: the control unit configures the parameters of the selector to determine the working configuration mode and the data flow direction; when a "start" signal is given externally, the entire system starts to work. If each selector is not selected, each butterfly operation unit performs operations to achieve the maximum N-point operation; each level operates independently of each other, and after completing the first-level operation, the data is output to the second-level butterfly operation unit for operation; recursion is performed in sequence, and the operation is finally completed and output at the last level; if a small-point FFT operation is performed, it is only necessary to change the state of the selector by changing the control unit. If an N / 4-point operation is performed, it is only necessary to disable the selector of the first butterfly operation and send the input data to the second selector. Therefore, the operation methods of N / 16-point FFT and N / 64-point FFT are similar to this. It can be seen that the biggest feature of the parallel pipeline architecture is that the entire system control architecture is simple and uses multiple butterfly operation units to improve the operating speed; however, it consumes a lot of resources. For FFT with a large number of points N, the number of butterfly operation units required at each level for base R extraction is logRN; at the same time, if a small number of points is calculated, the resource utilization of the entire system is not high; in addition, since the butterfly operation unit contains a large number of multipliers, the parallel architecture ignores the influence of the layout and wiring of the butterfly operation module, which will cause its critical path to become longer under the deep submicron process, affecting the physical implementation of the back-end chip.

[0004] In the traditional sequential architecture, the N-point FFT transform circuit is as follows Figure 2As shown, the entire FFT uses only one butterfly operation unit for calculation. After the input data is completed, it is stored in a storage unit. According to the FFT operation instruction, the value of the corresponding address is taken out in the signal flow graph and sent to the butterfly operation for calculation. Due to the characteristics of in-situ calculation, it can be stored back to the original storage unit; thus, only one storage unit and one butterfly operation can be used to complete the FFT operation. However, with the sequential architecture, the configuration method of different points has changed, and the addressing method has also changed. Therefore, multiple sets of addressing methods are generally required to realize configurable functions, resulting in a more complex addressing scheduling structure; and because the traditional SRAM stores the intermediate results of the butterfly operation, the intermediate results need to be delayed and registered, resulting in a slow FFT operation speed. Therefore, it is traditionally difficult for the sequential architecture to accurately realize configurable functions. Summary of the invention

[0005] The purpose of the present invention is to provide a configurable fast Fourier transform circuit with a sequential architecture to solve the problems that the current fast Fourier transform circuit structure with configurable points consumes a lot of resources and consumes a lot of power. The present invention implements a configurable fast Fourier transform circuit under a radix-sequential architecture based on a register group storage method, performs mode signal configuration on a configurable address generation module according to the number of points N of the fast Fourier transform, the configurable address generation module selects a working mode according to the mode signal, and then performs address encoding to generate an address value according to an FFT in-situ calculation method, thereby achieving configurable requirements with fewer resources. At the same time, the multiplier structure in a butterfly operation unit module is optimized, booth coding is used to improve the delay of the multiplier path, and the clock operating frequency and operation speed are improved.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A configurable fast Fourier transform circuit with a sequential architecture comprises: a butterfly operation unit module, a register storage unit with a depth dimension of 2N points, a configurable address generation module and a reverse module; the characteristic is that the configurable fast Fourier transform circuit configures the number of points N of the fast Fourier transform according to a mode signal, writes the sampled time domain signal into the register storage unit with a depth dimension of 2N points under clock control, sends a write end signal to the configurable address generation module after the writing is completed, the configurable address generation module generates a corresponding address value, the butterfly operation unit module reads the corresponding data in the register storage unit with a depth dimension of 2N points according to the address value, completes the operation, and writes the calculation result into the original address, the butterfly operation unit module completes all discrete Fourier transform operations according to the time sequence to obtain a frequency domain result, and the frequency domain result is reversely output through the reverse module to store the data in the register storage unit with a depth dimension of 2N points to obtain a fast Fourier transform operation result.

[0008] Furthermore, the configurable address generation module includes: a counter, a mode selection control module, a diff-D flip-flop group, a weight-D flip-flop group, an iD flip-flop group and a combinational logic operation circuit, wherein the iD flip-flop is used to store the operation level i, and the diff-D flip-flop group is used to store the intermediate operation result diff: The weight-D flip-flop group is used to store the intermediate calculation result weight: The counting result of the counter is the data j of the current operation level i. The mode selection control module selects the overflow flag j of the counter according to the number of FFT points N. flag :j flag =N / 4-1, to realize the address generation mode configuration according to the number of FFT points N; for each address generation mode, the address generation process is: the counter starts working under the control of the trigger signal, and the combinational logic operation circuit outputs the address according to the intermediate operation result diff, the intermediate operation result weight, the operation level i and its data j:

[0009] Add0(i,j)=data

[0010] Add1(i,j)=data+diff

[0011] Add2(i,j)=data+2·diff

[0012] Add3(i,j)=data+3·diff

[0013] Among them, data=quo_j·weight+mod_j, k=mod_j·k_pow, quo_j=(j-mod_j) / diff, mod_j=j%diff, k_pow=4 i ;

[0014] When j = j flag When , update the operation level i: i = i + 1.

[0015] Furthermore, the butterfly operation unit module includes: a booth multiplier and a radix-4 butterfly operation unit, wherein four booth multipliers constitute a complex multiplication circuit, and the calculation result of the radix-4 butterfly operation unit is complex multiplied by the complex multiplication circuit with the rotation factor to obtain an output.

[0016] The beneficial effects of the present invention are:

[0017] The present invention provides a configurable fast Fourier transform circuit with a sequential architecture, which is based on a sequential single-stage feedback FFT operation structure with registers as storage units, and realizes FFT operation with configurable points through mode selection of a configurable address generation module; compared with the traditional parallel pipeline architecture that needs to use multiple butterfly operation units, the present invention can greatly reduce the use of operation unit resources, thereby reducing the power consumption and resource consumption of the FFT system; at the same time, the present invention optimizes the multiplier structure in the butterfly operation unit module, adopts booth-coded multipliers to replace traditional multipliers, reduces the number of multiplier partial sums, improves the delay of the multiplier path, effectively reduces the difficulty of back-end layout and wiring, and greatly improves the clock operating frequency and operation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a configurable FFT transform circuit of an existing parallel pipeline architecture.

[0019] Figure 2 Schematic diagram of the N-point FFT transformation circuit structure of the traditional sequential architecture.

[0020] Figure 3 It is a schematic diagram of the structure of a configurable fast Fourier transform circuit of a sequential architecture in the present invention.

[0021] Figure 4 It is a butterfly operation data flow diagram of the butterfly operation unit module in the present invention.

[0022] Figure 5 Schematic diagram of the complex multiplication circuit structure of the butterfly operation unit module in the present invention.

[0023] Figure 6 It is an address generation sequence of a configurable address generation module in an embodiment of the present invention.

[0024] Figure 7 It is a schematic diagram of the structure of a configurable address generation module in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and technical effect of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and embodiments;

[0026] This embodiment provides a sequential architecture configurable fast Fourier transform circuit, whose structure is as follows: Figure 3As shown, it specifically includes: a butterfly operation unit module, a register storage unit with a depth dimension of 2N points (used to store real data and imaginary data), a configurable address generation module and a reverse module; wherein the configurable fast Fourier transform circuit configures the number of fast Fourier transform points N according to the mode signal, and the sampled time domain signal is written into the register storage unit with a depth dimension of 2N points under clock control, and after the writing is completed, a write end signal is sent to the configurable address generation module, and the configurable address generation module generates a corresponding address value, and the butterfly operation unit module reads the corresponding data in the register storage unit with a depth dimension of 2N points according to the address value, completes the operation, and writes the calculation result into the original address, and the butterfly operation unit module completes all DFT (discrete Fourier transform) operations according to the timing to obtain a frequency domain result, and the frequency domain result is reversed through the reverse module to output the data stored in the register storage unit with a depth dimension of 2N points, which is the FFT (fast Fourier transform) operation result.

[0027] In terms of working principle:

[0028] 1. The butterfly operation unit module includes: a booth multiplier and a radix-4 butterfly operation unit. The four booth multipliers constitute a complex multiplication circuit. The calculation result of the radix-4 butterfly operation unit and the rotation factor are complex multiplied by the complex multiplication circuit. In this embodiment, the butterfly operation data flow diagram of the butterfly operation unit module is as follows: Figure 4 As shown, the input data is sampled in 4 equal parts, and the 4 extracted data are sent to the butterfly operation unit module in parallel under clock control. After calculating a butterfly operation, the calculated data is stored in the original address; for the N-point FFT transform of the base n extraction, log n After the calculation result of the N-level butterfly operation is completed, the result of the fast Fourier transform is output in reverse order; the booth multiplier adopts a 24×10-bit booth multiplier, and the booth multiplier is used to replace the multiplier in the traditional butterfly operation unit module, thereby forming a complex multiplication circuit such as Figure 5 As shown, the number of partial items can be effectively reduced, thereby reducing path delay and improving the effect of clock frequency.

[0029] 2. The working principle of the configurable address generation module is as follows: According to the calculation characteristics of FFT, the corresponding address generation algorithm is designed. The present invention adopts a base 4 frequency extraction method, the number of calculation points is N, and the address generation algorithm is as follows:

[0030] According to the number of FFT points to be selected, set the FFT calculation level i=0,1,2,...,log4N, then there will be j groups of data in each calculation level: j=0,1,2,...,N / 4-1, and form Add0(i,j), Add1(i,j), Add2(i,j), Add3(i,j) as addresses from small to large; for the calculation level i, calculate the intermediate result value:

[0031] k_pow=4 i

[0032] Further perform remainder operation: mod_j=j%diff, quotient operation: quo_j=(j-mod_j) / diff, and set parameters data and k: data=quo_j·weight+mod_j, k=mod_j·k_pow;

[0033] The final generated address value is as follows:

[0034] Add0(i,j)=data

[0035] Add1(i,j)=data+diff

[0036] Add2(i,j)=data+2·diff

[0037] Add3(i,j)=data+3·diff

[0038] When j is calculated to N / 4-1, the operation level i=i+1 is updated and the next level of operation is performed; this embodiment takes 64 points as an example, and the address generation sequence obtained is as follows Figure 6 As shown;

[0039] Based on the above address generation algorithm, this embodiment provides a configurable address generation module such as Figure 7 As shown, it includes: a counter, a mode selection control module, a diff-D flip-flop group, a weight-D flip-flop group, an iD flip-flop group and a combinational logic operation circuit, wherein the iD flip-flop is used to store the operation level i, and the diff-D flip-flop group is used to store the intermediate operation result diff: The weight-D flip-flop group is used to store the intermediate calculation result weight: The counting result of the counter is the data j of the current operation level i. The mode selection control module selects the overflow flag j of the counter according to the number of FFT points N. flag :j flag=N / 4-1, that is, the address generation mode configuration according to the FFT point number N is realized; for each address generation mode, the address generation process is: the counter starts working under the control of the trigger signal, and the combinational logic operation circuit outputs the address according to the intermediate operation result diff, the intermediate operation result weight, the operation level i and its data j:

[0040] Add0(i,j)=data

[0041] Add1(i,j)=data+diff

[0042] Add2(i,j)=data+2·diff

[0043] Add3(i,j)=data+3·diff

[0044] Among them, data=quo_j·weight+mod_j, k=mod_j·k_pow, quo_j=(j-mod_j) / diff, mod_j=j%diff, k_pow=4 i ;

[0045] When j = j flag When , update the operation level i: i = i + 1.

[0046] In this embodiment, the configurable address generation module implements the switching of 256-point butterfly operation address generation or 64-point butterfly operation address generation according to the Mode signal. When mode=0, the address required for 256-point FFT is generated, and when Mode=1, the address required for 64-point FFT is generated; the counter starts working under the control of the trigger signal. When Mode=0, the calculator series result j counts from 0 to 63, and an overflow signal is generated to update the operation series i. Both weight and diff are shifted after the overflow signal arrives, and the updated values ​​are stored again in the corresponding trigger group. At the same time, the combinational logic circuit outputs the calculated address value in real time according to the above algorithm; similarly, when Mode=1, j counts from 0 to 15; thus, the overflow flag j of the counter is used. flag The choice of is to realize the address generation mode configuration according to the FFT point number N.

[0047] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A configurable fast Fourier transform circuit with a sequential architecture, comprising: A butterfly operation unit module, a register storage unit with a depth dimension of 2N points, a configurable address generation module and a reverse module; characterized in that the configurable fast Fourier transform circuit configures the number of fast Fourier transform points N according to the mode signal, writes the sampled time domain signal into the register storage unit with a depth dimension of 2N points under clock control, and sends a write end signal to the configurable address generation module after the writing is completed, the configurable address generation module generates a corresponding address value, the butterfly operation unit module reads the corresponding data in the register storage unit with a depth dimension of 2N points according to the address value, completes the operation, and writes the calculation result into the original address, the butterfly operation unit module completes all discrete Fourier transform operations according to the timing to obtain a frequency domain result, and the frequency domain result is reversely output through the reverse module to store the data in the register storage unit with a depth dimension of 2N points to obtain a fast Fourier transform operation result; The configurable address generation module includes: a counter, a mode selection control module, a diff-D trigger group, a weight-D trigger group, an iD trigger group and a combinational logic operation circuit, wherein the iD trigger is used to store the operation level i, and the diff-D trigger group is used to store the intermediate operation result diff: The weight-D flip-flop group is used to store the intermediate calculation result weight: The counting result of the counter is the data j of the current operation level i. The mode selection control module selects the overflow flag j of the counter according to the number of FFT points N. flag :j flag =N / 4-1, to realize the address generation mode configuration according to the number of FFT points N; for each address generation mode, the address generation process is: the counter starts working under the control of the trigger signal, and the combinational logic operation circuit outputs the address according to the intermediate operation result diff, the intermediate operation result weight, the operation level i and its data j: Add0(i,j)=data Add1(i,j)=data+diff Add2(i,j)=data+2·diff Add3(i,j)=data+3·diff where data = quo_j·weight + mod_j, k = mod_j·k_pow, quo_j = (j - mod_j) / diff, mod_j = j % diff, k_pow = 4 i ; When j = j flag When , update the operation level i: i = i + 1; The butterfly operation unit module includes: a booth multiplier and a radix-4 butterfly operation unit, wherein four booth multipliers constitute a complex multiplication circuit, and the calculation result of the radix-4 butterfly operation unit is complex multiplied by the complex multiplication circuit with the rotation factor to obtain an output.

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