NRHC-14T Radiation-Tolerant SRAM Memory Cells, Chips and Modules

Abstract

The present invention relates to a NRHC-14T radiation-resistant SRAM storage unit, a chip and a module. The NRHC-14T radiation-resistant SRAM storage unit includes PMOS transistors P1-P8 and NMOS transistors N1-N6. Transistors P1 and P2 are cross-coupled, P1, P2, P3 and P4 are used as pull-up tubes, P5 and P6 are used as pull-down tubes, and their states are controlled by storage nodes Q and QN respectively. Two main storage nodes Q and QN are connected to bit lines BL and BLB respectively through N5 and N6, and two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB respectively through P7 and P8. N5 and N6 are controlled by word lines WL, and P7 and P8 are controlled by word lines WLB. The present invention can improve the ability of the unit circuit to resist SEU, can greatly improve the speed of the unit at the expense of a smaller unit area, and reduce the power consumption of the unit.

Description

Technical Field

[0001] The invention relates to the technical field of static random access memory cells, in particular to a NRHC-14T radiation-resistant SRAM memory cell, a chip and a module. Background Art

[0002] With the continuous advancement of complementary metal oxide semiconductor (CMOS) technology. The size of electronic devices is getting smaller and smaller, its integration is getting higher and higher, and factors such as the space radiation environment in which it works affect the stability of the device. The radiation effect in space will cause single event effects (SEE) to the working static random access memory (SRAM). Single event effects can cause hard errors and soft errors in electronic devices. The occurrence of hard errors can cause physical damage to the device, leading to catastrophic consequences; while soft errors mainly affect the working state of the device, making it unable to transmit correct information. Due to the limited energy of space radiation particles, the probability of causing soft errors in the device is much greater than the probability of causing hard errors in the device. Among soft errors, the probability of single event upset (SEU) is much greater than the probability of other types of errors. In order to improve the unit's ability to resist SEU, the existing technology mainly includes the following solutions:

[0003] 1. As Figure 1 The figure shows a DICE 12T circuit that is resistant to single-event upsets. It has 4 storage nodes and 4 transmission tubes. When an SEU occurs on each single storage node, the node will eventually be recovered by the remaining nodes. However, when an SEU occurs on any two storage nodes, the storage information of the circuit node will be flipped and cannot be self-recovered, resulting in erroneous data.

[0004] 2. If Figure 2 The figure shows a Soft Error Tolerant 10T SRAM BitCell (QUATRO 10T) circuit. It has better SEU resistance than the traditional six-tube cell structure, but the write capability of the cell is poor, and its Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) are poor.

[0005] 3. Such as Figure 3The circuit shown is a SAR14T circuit, which uses four NMOS transistors to write data into the cell, but uses two NMOS transistors to read data through external nodes, resulting in a large read delay time for the cell.

[0006] 4. Such as Figure 4 The circuit shown is a RSP14T circuit, which utilizes source isolation technology. When the cell stores "1", the stacked PMOS structure connects the transistor P2 to the weak signal "1", so the amount of charge collected by the drain of the transistor P2 will be reduced, the resistance of the node QB to SEU is improved, and the cell becomes more stable.

[0007] 5. As Figure 5 The circuit shown is a Radiation Hardened By Polar Design (RHPD-12T), which can resist partial double-node flips in addition to single-node flips, but at the expense of lower HSNM and RSNM.

[0008] 6. Such as Figure 6 The figure shows a Radiation Hardened By Design SRAM bit-cell (RHBD14T) circuit. This circuit uses polarity hardening technology, which reduces the number of sensitive nodes, but leads to larger read and write delays and lower noise margin (SNM) values.

[0009] Based on the above existing solutions, there is a need for a NRHC-14T unit that improves the read and write speed of the storage unit, reduces the power consumption of the unit, and improves the unit's ability to resist single-event upsets. Summary of the invention

[0010] Based on this, it is necessary to provide a NRHC-14T radiation-resistant SRAM storage unit, chip and module to address the problems of slow storage unit read and write speed, high unit power consumption and poor unit single particle upset resistance.

[0011] NRHC-14T radiation-resistant SRAM memory cell, which includes:

[0012] PMOS transistor P1;

[0013] A PMOS transistor P2, wherein the drain of P2 is electrically connected to the gate of P1, the gate of P2 is electrically connected to the drain of P1, and the source of P2 is electrically connected to the source of P1;

[0014] A PMOS transistor P3, wherein the gate of P3 is electrically connected to the gate of P1 and the drain of P2, and the source of P3 is electrically connected to the source of P1 and the source of P2;

[0015] A PMOS transistor P4, wherein the gate of P4 is electrically connected to the gate of P2 and the drain of P1, and the source of P4 is electrically connected to the source of P1, the source of P2, and the source of P3;

[0016] A PMOS transistor P5, wherein the source of P5 is electrically connected to the drain of P1, and the gate of P5 is electrically connected to the drain of P3;

[0017] A PMOS transistor P6, wherein the source of P6 is electrically connected to the drain of P2, the gate of P6 is electrically connected to the drain of P4, and the drain of P6 is electrically connected to the drain of P5;

[0018] A PMOS transistor P7, wherein a drain of P7 is electrically connected to a drain of P1, a gate of P7 is electrically connected to a word line WLB, and a source of P7 is electrically connected to a bit line BL;

[0019] A PMOS transistor P8, wherein the drain of P8 is electrically connected to the drain of P2, the gate of P8 is electrically connected to the word line WLB, and the source of P8 is electrically connected to the bit line BLB;

[0020] NMOS transistor N1, wherein the drain of N1 is electrically connected to the drain of P3 and the gate of P5, and the gate of N1 is electrically connected to the drain of P4 and the gate of P6;

[0021] NMOS transistor N2, the drain of N2 is electrically connected to the drain of P4, the gate of P6, and the gate of N1, and the gate of N2 is electrically connected to the drain of N1, the drain of P3, and the gate of P5;

[0022] NMOS transistor N3, wherein the drain of N3 is electrically connected to the source of N1, the gate of N3 is electrically connected to the gate of P3, the gate of P1, and the drain of P2, and the source of N3 is electrically connected to the drain of P5 and the drain of P6;

[0023] NMOS transistor N4, the drain of N4 is electrically connected to the source of N2, the gate of N4 is electrically connected to the gate of P4, the gate of P2, the drain of P1, and the source of P5, and the source of N4 is electrically connected to the source of N3, the drain of P5, and the drain of P6;

[0024] NMOS transistor N5, wherein the drain of N5 is electrically connected to the drain of N1, the gate of N5 is electrically connected to the word line WL, and the source of N5 is electrically connected to the bit line BL;

[0025] NMOS transistor N6, wherein the drain of N6 is electrically connected to the drain of N2, the gate of N6 is electrically connected to the word line WL, and the source of N6 is electrically connected to the bit line BLB;

[0026] Transistors P1 and P2 are cross-coupled, P1, P2, P3 and P4 are used as pull-up transistors, P5 and P6 are used as pull-down transistors, and their states are controlled by storage nodes Q and QN respectively. P3 and N3, P4 and N4 constitute inverters respectively, N1 and N2 are inserted between two inverters respectively and cross-coupled, two main storage nodes Q and QN are connected to bit lines BL and BLB respectively through N5 and N6, two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB respectively through P7 and P8, N5 and N6 are controlled by word line WL, and P7 and P8 are controlled by word line WLB; VDD is electrically connected to the sources of transistors P1, P2, P3 and P4; the sources of transistors N3 and N4 and the drains of P5 and P6 are grounded.

[0027] Furthermore, the lengths of the transistors N1 to N6 and P1 to P8 are all 65 nm, of which P1 and P2 are 370 nm wide, P5 and P6 are 80 nm wide, and the widths of the remaining transistors are all 140 nm.

[0028] In one embodiment, when the NRHC-14T radiation-resistant SRAM memory cell is in the holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a low level, the word line WLB is a high level, and the circuit maintains an initial state.

[0029] In one embodiment, when the NRHC-14T radiation-resistant SRAM memory cell is in the data reading stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a high level, the word line WLB is a low level, and transistors N5, N6, P7 and P8 are turned on.

[0030] Further, if the data stored in the unit circuit is '0', then "Q=S0=0, QN=S1=1"; the bit line BL is discharged to the ground through discharge path 1: transistors P7, P5 and discharge path 2: transistors N5, N1 and N3, so that a voltage difference is generated on the bit line, and the data is read out through the sensitive amplifier; if the data stored in the unit circuit is '1', then "Q=S0=1, QN=S1=0"; the bit line BLB is discharged to the ground through discharge path 1: transistors P8, P6 and discharge path 2: transistors N6, N2 and N4, so that a voltage difference is generated on the bit line, and the data is read out through the sensitive amplifier.

[0031] In one of the embodiments, when the NRHC-14T radiation-resistant SRAM memory cell is in the data writing stage, the word line WL is at a high level and the word line WLB is at a low level.

[0032] Further, if BL is high and BLB is low, '1' is written to the storage nodes Q and S0 respectively through transistors N5 and P7; if BL is low and BLB is high, '1' is written to the storage nodes QN and S1 respectively through transistors N6 and P8.

[0033] The present invention also includes a NRHC-14T radiation-resistant SRAM storage chip, which is packaged using the circuit structure of the aforementioned NRHC-14T radiation-resistant SRAM storage unit.

[0034] Furthermore, the pins of the NRHC-14T radiation-resistant SRAM memory chip include:

[0035] A first pin electrically connected to the gates of transistors P7 and P8 through a word line WLB;

[0036] A second pin electrically connected to the gates of transistors N5 and N6 through a word line WL;

[0037] A third pin, which is electrically connected to the sources of transistors N5 and P7 through a bit line BL;

[0038] The fourth pin is electrically connected to the sources of the transistors N6 and P8 through the bit line BLB.

[0039] The present invention also includes a NRHC-14T radiation-resistant SRAM storage module, which uses the circuit of the aforementioned NRHC-14T radiation-resistant SRAM storage unit, and the NRHC-14T radiation-resistant SRAM storage module includes:

[0040] The gates of transistors P7 and P8 are electrically connected to a word line WLB, thereby leading to a first connection terminal;

[0041] The gates of transistors N5 and N6 are electrically connected to a word line WL, thereby leading to a second connection terminal;

[0042] The sources of transistors N5 and P7 are electrically connected to the bit line BL, thereby leading to a third connection terminal;

[0043] Sources of the transistors N6 and P8 are electrically connected to the bit line BLB, thereby leading out a fourth connection terminal.

[0044] The technical solution provided by the present invention has the following beneficial effects:

[0045] The use of RHM-14T radiation-resistant SRAM storage cells can improve the SEU resistance of the unit circuit, greatly increase the speed of the unit at the expense of a smaller unit area, and reduce the power consumption of the unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1A schematic diagram of the structure of a DICE circuit in the prior art provided as the background technology of the present invention;

[0047] Figure 2 A schematic diagram of the structure of a QUATRO 10T circuit in the prior art provided as the background technology of the present invention;

[0048] Figure 3 A schematic diagram of the structure of a SAR14T circuit in the prior art provided as the background technology of the present invention;

[0049] Figure 4 A schematic diagram of the structure of the RSP14T circuit in the prior art provided as the background technology of the present invention;

[0050] Figure 5 A schematic diagram of the structure of the RHPD-12T circuit in the prior art provided as the background technology of the present invention;

[0051] Figure 6 A schematic diagram of the structure of the RHBD14T circuit in the prior art provided as the background technology of the present invention;

[0052] Figure 7 It is a schematic diagram of the structure of the NRHC-14T radiation-resistant SRAM storage unit of the present invention;

[0053] Figure 8 for Figure 7 Timing waveform diagram of the internal NRHC-14T radiation-resistant SRAM memory cell;

[0054] Fig. 9 For Figure 7 Transient waveform simulation diagram of the NRHC-14T radiation-resistant SRAM storage cell at different times and different nodes being injected with double exponential current source pulses;

[0055] Fig.10 for Figure 7 NRHC-14T radiation-hardened SRAM memory cells with Figures 1 to 6 Comparison chart of HSNM, RSNM and WSNM comparison in existing technology;

[0056] Fig.11 for Figure 7 NRHC-14T radiation-hardened SRAM memory cells with Figures 1 to 6 A comparison chart of the number of failures of the prior art under different supply voltages and different frequencies;

[0057] Fig.12 For Figure 7 Schematic diagram of the structure of the NRHC-14T radiation-resistant SRAM memory chip based on the NRHC-14T radiation-resistant SRAM memory cell. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0059] like Figure 7 As shown, this embodiment provides a NRHC-14T radiation-resistant SRAM storage cell, which includes PMOS transistors P1-P8 and NMOS transistors N1-N6. Transistors P1 and P2 are cross-coupled, P1, P2, P3 and P4 are used as pull-up transistors, P5 and P6 are used as pull-down transistors, and their states are controlled by storage nodes Q and QN respectively, P3 and N3, P4 and N4 respectively constitute inverters, N1 and N2 are respectively inserted between two inverters and cross-coupled, two main storage nodes Q and QN are connected to bit lines BL and BLB respectively through N5 and N6, two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB respectively through P7 and P8, N5 and N6 are controlled by word line WL, and P7 and P8 are controlled by word line WLB; VDD is electrically connected to the sources of transistors P1, P2, P3 and P4; the sources of transistors N3 and N4 are grounded with the drains of P5 and P6.

[0060] The specific connection method is as follows: the bit line BL is electrically connected to the source of the transmission transistors N5 and P7; the bit line BLB is electrically connected to the source of the transistors N6 and P8; the word line WL is electrically connected to the gate of the transmission transistors N5 and N6; the word line WLB is electrically connected to the gate of the transmission transistors P7 and P8; the drain of the transmission transistor N5 is electrically connected to the drain of the NMOS transistor N1; the drain of the transmission transistor N6 is electrically connected to the drain of the NMOS transistor N2; the drain of the transmission transistor P7 is electrically connected to the drain of the PMOS transistor P1; the drain of the transmission transistor P8 is electrically connected to the drain of the PMOS transistor P2; VDD is electrically connected to the source of the PMOS transistors P1, P2, P3 and P4; the source of the NMOS transistors N3 and N4 and the drain of the PMOS transistors P5 and P6 are grounded.

[0061] The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P5, the gates of the PMOS transistors P2 and P4, and the gate of the NMOS transistor N4, and the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P2, the source of the PMOS transistor P6, the gate of the PMOS transistor P3, and the gate of the NMOS transistor N3. The drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P6, the gates of the PMOS transistors P1 and P3, and the gate of the NMOS transistor N3, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P1, the source of the PMOS transistor P5, the gate of the PMOS transistor P4, and the gate of the NMOS transistor N4. The drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, the gate of the NMOS transistor N2, and the gate of the PMOS transistor P5, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N3, the gate of the PMOS transistor P1, the drain of the PMOS transistor P2, and the source of the PMOS transistor P6. The drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N1, and the gate of the PMOS transistor P6, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N4, the gate of the PMOS transistor P2, the drain of the PMOS transistor P1, and the source of the PMOS transistor P5. The source of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P1, and the gate of the PMOS transistor P5 is electrically connected to the drain of the PMOS transistor P3 and the drain of the NMOS transistor N1. The source of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P2 , and the gate of the PMOS transistor P6 is electrically connected to the drain of the PMOS transistor P4 and the drain of the NMOS transistor N2 .

[0062] The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, the gate of the PMOS transistor P5, and the gate of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P4, and the gate of the PMOS transistor P6. The drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P6, and the gate of the NMOS transistor N1, and the gate of the NMOS transistor N2 is electrically connected to the drain of the NMOS transistor N1, the drain of the PMOS transistor P3, and the gate of the PMOS transistor P5. The drain of the NMOS transistor N3 is electrically connected to the source of the NMOS transistor N1, and the gate of the NMOS transistor N3 is electrically connected to the gates of the PMOS transistors P3 and P1, the drain of the PMOS transistor P2, and the source of the PMOS transistor P6. The drain of NMOS transistor N4 is electrically connected to the source of NMOS transistor N2, and the gate of NMOS transistor N4 is electrically connected to the gates of PMOS transistors P4 and P2, the drain of PMOS transistor P1, and the source of PMOS transistor P5. The drain of N5 is electrically connected to the drain of N1, the gate of N5 is electrically connected to the word line WL, and the source of N5 is electrically connected to the bit line BL. The drain of N6 is electrically connected to the drain of N2, the gate of N6 is electrically connected to the word line WL, and the source of N6 is electrically connected to the bit line BLB.

[0063] The length of all transistors is 65nm, among which the width of PMOS transistors P1 and P2 is 370nm, the width of P5 and P6 is 80nm, and the width of all remaining transistors is 140nm.

[0064] The principle of the above NRHC-14T radiation-resistant SRAM storage cell is as follows: in the holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a low level, the word line WLB is a high level, the circuit maintains its initial state, and the circuit does not work. When in the data reading stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a high level, the word line WLB is a low level, and the transfer transistors N5, N6, P7 and P8 are turned on; if the data stored in the unit circuit is '0', then "Q=S0=0, QN=S1=1"; then BL discharges to the ground through discharge path 1: transistors P7, P5 and discharge path 2: transistors N5, N1, and N3, so that a voltage difference is generated on the bit line, and then the data is read out through the sensitive amplifier; if the data stored in the unit circuit is '1', then "Q=S0=1, QN=S1=0" then BLB discharges to the ground through discharge path 1: transistors P8, P6 and discharge path 2: transistors N6, N2 and N4, so that a bit line voltage difference is generated, and then the data is read out through the sensitive amplifier. In the data writing phase, the word line WL is at a high level and the word line WLB is at a low level. If BL is at a high level and BLB is at a low level, then '1' is written to the storage nodes Q and S0 respectively through the transmission transistors N5 and P7; if BL is at a low level and BLB is at a high level, then '1' is written to the storage nodes QN and S1 respectively through the transmission transistors N6 and P8. During the writing process, because data is written to the internal nodes Q\S0 and QN\S1 simultaneously through the transmission transistors N5 and P7 and N6 and P8, the storage nodes are more easily written with data, so the writing speed will be greatly improved. At the same time, the power consumption of the circuit is reduced due to the greatly improved writing speed.

[0065] When only considering the improvement of the circuit structure's radiation resistance performance, if the storage node of the circuit is bombarded by particles, since the circuit nodes S0 and S1 are surrounded by PMOS transistors, according to the polarity reinforcement principle, the space particles bombard the sensitive node PMOS tube, and only a "0-1" voltage pulse is generated at the node, and this pulse cannot affect the state of other transistors due to the existence of gate capacitance, which effectively prevents the external nodes S0 and S1 from flipping. At the same time, the stability of the data of the S0 and S1 nodes ensures that the internal nodes Q and QN can be restored to the initial state after flipping, thereby improving the circuit's ability to resist SEU. If other non-critical nodes are bombarded by particles, the storage unit is less susceptible to being affected.

[0066] Under the simulation conditions of Corner: TT; Temperature: 27℃; VDD: 1.2V, the timing waveform of the NRHC-14T radiation-resistant SRAM storage cell circuit is as follows: Figure 8The transient waveform simulation of the NRHC-14T radiation-resistant SRAM storage unit circuit at different times and different nodes being injected with double exponential current source pulses is shown in Figure 2. Fig. 9 The comparison of NRHC-14T radiation-resistant SRAM storage unit circuit with the existing SRAM unit circuit is shown in the figure. Fig.10 The comparison of the number of failures of the NRHC-14T radiation-resistant SRAM storage cell circuit and the prior art SRAM cell circuit under different power supply voltages and different frequencies is shown in the figure. Fig.11 shown.

[0067] The simulation conditions are consistent with the above. The overall circuit area, read / write time and power consumption of the 14T radiation-resistant SRAM storage unit circuit provided in this embodiment are improved compared with the prior art SRAM unit circuit, as shown in the following table:

[0068] Simulation comparison table

[0069] unit <![CDATA[Area (μm 2 )]]> Read latency (ps) Write latency (ps) Power consumption (μW) DICE 8.97 56.2 27.6 15.16 Quatro 7.48 112.5 25.13 15.1 SAR14T 11.03 109.5 21 15.17 RSP14T 10.96 110 31.9 15.12 RHPD-12T 8.75 51.82 20.4 15.19 RHBD14T 9.85 99.5 39.3 15.13 NRHC-14T 10.47 91 17.5 15.12

[0070] The simulation conditions are consistent with the above. The critical charge of the NRHC-14T radiation-resistant SRAM storage unit provided in this embodiment is higher than that of the SRAM unit circuit in the prior art, as shown in the following table:

[0071] Charge comparison table

[0072] Circuit Name Critical charge (fC) Quatro 7.36 RSP14T 7.24 RHPD-12T 19.6 DICE >50 SAR14T >50 RHBD14T >50 NRHC-14T >50

[0073] It can be seen that the NRHC-14T radiation-resistant SRAM storage unit provided by the present invention can improve the SEU resistance of the unit circuit, can greatly increase the speed of the unit at the expense of a smaller unit area, and reduce the power consumption of the unit.

[0074] like Fig.12 As shown, based on the aforementioned NRHC-14T radiation-resistant SRAM storage unit, a NRHC-14T radiation-resistant SRAM storage chip is further provided, and the chip is packaged by the NRHC-14T radiation-resistant SRAM storage unit; the mode of packaging into a chip makes it easier to promote and apply the NRHC-14T radiation-resistant SRAM storage unit.

[0075] The pins of the NRHC-14T radiation-resistant SRAM memory chip include: a first pin, which is electrically connected to the gates of transistors P7 and P8 through a word line WLB. A second pin, which is electrically connected to the gates of transistors N5 and N6 through a word line WL. A third pin, which is electrically connected to the sources of transistors N5 and P7 through a bit line BL. A fourth pin, which is electrically connected to the sources of transistors N6 and P8 through a bit line BLB.

[0076] On the basis of the aforementioned NRHC-14T radiation-resistant SRAM storage unit, the present embodiment also includes a NRHC-14T radiation-resistant SRAM storage module, which adopts the circuit structure in the aforementioned NRHC-14T radiation-resistant SRAM storage unit, and the NRHC-14T radiation-resistant SRAM storage module includes: the gates of transistors P7 and P8 are electrically connected to the word line WLB, thereby leading to a first connection terminal. The gates of transistors N5 and N6 are electrically connected to the word line WL, thereby leading to a second connection terminal. The sources of transistors N5 and P7 are electrically connected to the bit line BL, thereby leading to a third connection terminal. The sources of transistors N6 and P8 are electrically connected to the bit line BLB, thereby leading to a fourth connection terminal.

[0077] Designing the NRHC-14T radiation-resistant SRAM storage unit into a NRHC-14T radiation-resistant SRAM storage module can facilitate the promotion and application of the NRHC-14T radiation-resistant SRAM storage unit in the market, and facilitate technical personnel in the field to quickly use the NRHC-14T radiation-resistant SRAM storage unit. They only need to refer to the product manual to connect the module.

[0078] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. NRHC-14T radiation-resistant SRAM storage cell, characterized in that: It includes: PMOS transistor P1; A PMOS transistor P2, wherein the drain of P2 is electrically connected to the gate of P1, the gate of P2 is electrically connected to the drain of P1, and the source of P2 is electrically connected to the source of P1; A PMOS transistor P3, wherein the gate of P3 is electrically connected to the gate of P1 and the drain of P2, and the source of P3 is electrically connected to the source of P1 and the source of P2; A PMOS transistor P4, wherein the gate of P4 is electrically connected to the gate of P2 and the drain of P1, and the source of P4 is electrically connected to the source of P1, the source of P2, and the source of P3; A PMOS transistor P5, wherein the source of P5 is electrically connected to the drain of P1, and the gate of P5 is electrically connected to the drain of P3; A PMOS transistor P6, wherein the source of P6 is electrically connected to the drain of P2, the gate of P6 is electrically connected to the drain of P4, and the drain of P6 is electrically connected to the drain of P5; A PMOS transistor P7, wherein a drain of P7 is electrically connected to a drain of P1, a gate of P7 is electrically connected to a word line WLB, and a source of P7 is electrically connected to a bit line BL; A PMOS transistor P8, wherein the drain of P8 is electrically connected to the drain of P2, the gate of P8 is electrically connected to the word line WLB, and the source of P8 is electrically connected to the bit line BLB; NMOS transistor N1, wherein the drain of N1 is electrically connected to the drain of P3 and the gate of P5, and the gate of N1 is electrically connected to the drain of P4 and the gate of P6; NMOS transistor N2, the drain of N2 is electrically connected to the drain of P4, the gate of P6, and the gate of N1, and the gate of N2 is electrically connected to the drain of N1, the drain of P3, and the gate of P5; NMOS transistor N3, wherein the drain of N3 is electrically connected to the source of N1, the gate of N3 is electrically connected to the gate of P3, the gate of P1, and the drain of P2, and the source of N3 is electrically connected to the drain of P5 and the drain of P6; NMOS transistor N4, the drain of N4 is electrically connected to the source of N2, the gate of N4 is electrically connected to the gate of P4, the gate of P2, the drain of P1, and the source of P5, and the source of N4 is electrically connected to the source of N3, the drain of P5, and the drain of P6; NMOS transistor N5, wherein the drain of N5 is electrically connected to the drain of N1, the gate of N5 is electrically connected to the word line WL, and the source of N5 is electrically connected to the bit line BL; NMOS transistor N6, wherein the drain of N6 is electrically connected to the drain of N2, the gate of N6 is electrically connected to the word line WL, and the source of N6 is electrically connected to the bit line BLB; Transistors P1 and P2 are cross-coupled, P1, P2, P3 and P4 are used as pull-up transistors, P5 and P6 are used as pull-down transistors, and their states are controlled by storage nodes Q and QN respectively. P3 and N3, P4 and N4 constitute inverters respectively, N1 and N2 are inserted between two inverters respectively and cross-coupled, two main storage nodes Q and QN are connected to bit lines BL and BLB respectively through N5 and N6, two redundant storage nodes S0 and S1 are connected to bit lines BL and BLB respectively through P7 and P8, N5 and N6 are controlled by word line WL, and P7 and P8 are controlled by word line WLB; VDD is electrically connected to the sources of transistors P1, P2, P3 and P4; the sources of transistors N3 and N4 and the drains of P5 and P6 are grounded.

2. The NRHC-14T radiation-resistant SRAM storage cell according to claim 1, characterized in that: The lengths of the transistors N1 to N6 and P1 to P8 are all 65 nm, of which P1 and P2 are 370 nm wide, P5 and P6 are 80 nm wide, and the widths of the remaining transistors are all 140 nm.

3. The NRHC-14T radiation-resistant SRAM storage cell according to claim 2, characterized in that: When the NRHC-14T radiation-resistant SRAM storage cell is in the holding stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a low level, the word line WLB is a high level, and the circuit maintains an initial state.

4. The NRHC-14T radiation-resistant SRAM storage cell according to claim 2, characterized in that: When the NRHC-14T radiation-resistant SRAM storage cell is in the data reading stage, the bit lines BL and BLB are precharged to a high level, the word line WL is a high level, the word line WLB is a low level, and transistors N5, N6, P7 and P8 are turned on.

5. The NRHC-14T radiation-resistant SRAM storage cell according to claim 4, characterized in that: If the data stored in the NRHC-14T radiation-resistant SRAM storage cell is '0', then "Q=S0=0, QN=S1=1"; the bit line BL is discharged to the ground through discharge path 1: transistors P7 and P5 and discharge path 2: transistors N5, N1 and N3, so that a voltage difference is generated in the bit line, and the data is read out through the sense amplifier; if the data stored in the NRHC-14T radiation-resistant SRAM storage cell is '1', then "Q=S0=1, QN=S1=0"; the bit line BLB is discharged to the ground through discharge path 1: transistors P8 and P6 and discharge path 2: transistors N6, N2 and N4, so that a voltage difference is generated in the bit line, and the data is read out through the sense amplifier.

6. The NRHC-14T radiation-resistant SRAM storage cell according to claim 2, characterized in that: When the NRHC-14T radiation-resistant SRAM storage unit is in the data writing stage, the word line WL is at a high level and the word line WLB is at a low level.

7. The NRHC-14T radiation-resistant SRAM storage cell according to claim 6, characterized in that: If BL is high and BLB is low, '1' is written to the storage nodes Q and S0 respectively through transistors N5 and P7; if BL is low and BLB is high, '1' is written to the storage nodes QN and S1 respectively through transistors N6 and P8.

8. NRHC-14T radiation-resistant SRAM memory chip, characterized in that: It is packaged using the circuit structure of the NRHC-14T radiation-resistant SRAM storage unit as described in any one of claims 1 to 7.

9. The NRHC-14T radiation-resistant SRAM memory chip according to claim 8, characterized in that: The pins of the NRHC-14T radiation-resistant SRAM memory chip include: A first pin electrically connected to the gates of transistors P7 and P8 through a word line WLB; A second pin electrically connected to the gates of transistors N5 and N6 through a word line WL; A third pin, which is electrically connected to the sources of transistors N5 and P7 through a bit line BL; The fourth pin is electrically connected to the sources of the transistors N6 and P8 through the bit line BLB. 10.NRHC-14T radiation-resistant SRAM storage module, characterized in that: It adopts the circuit of the NRHC-14T radiation-resistant SRAM storage unit as claimed in any one of claims 1 to 5, and the NRHC-14T radiation-resistant SRAM storage module comprises: The gates of transistors P7 and P8 are electrically connected to a word line WLB, thereby leading to a first connection terminal; The gates of transistors N5 and N6 are electrically connected to a word line WL, thereby leading to a second connection terminal; The sources of transistors N5 and P7 are electrically connected to the bit line BL, thereby leading to a third connection terminal; Sources of the transistors N6 and P8 are electrically connected to the bit line BLB, thereby leading out a fourth connection terminal.

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