Method for manufacturing active area metal zero layer
By adding the first etch stop layer to the active area metal zero-layer manufacturing method and selective etching is performed using the material difference between it and other layer films, the problem of trench morphology deformation is solved, and better metal filling effect and device performance are achieved.
Patent Information
- Application Number
- CN202210597551.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-30
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2042-05-30
AI Technical Summary
In the existing method of manufacturing metal zero-layers in active zones, the groove morphology is prone to become bowling spherical, resulting in defects during metal filling and affecting product quality.
After the gate replacement process is completed, the step of forming the first etch stop layer is added. The material of the first etch stop layer is different from the materials of the zero interlayer film and the first interlayer film, and selective etching is realized, and precise trenches are formed through grading etching.
Prevent the groove from bowling morphology, improve the ability of metal to fill the grooves, avoid filling gaps, and improve device performance.
Smart Images
Figure CN115020330B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing an active area metal zero layer (MOA). Background Art
[0002] like Figure 1 FIG. 1 is a schematic diagram of a device cross-sectional structure after a groove is formed in an existing method for manufacturing an active area metal zero layer; the existing method for manufacturing an active area metal zero layer comprises the following steps:
[0003] Step 1: providing a semiconductor substrate 101 after a gate replacement process is completed.
[0004] The gate replacement process forms a gate structure 105 in the dummy gate structure removal area. The gate structure 105 is composed of a gate dielectric layer and a metal gate. A zero-layer interlayer film 110 is formed between the gate structures 105. The top surface of the gate structure 105 is flush with the top surface of the zero-layer interlayer film 110.
[0005] Typically, the material of the zeroth interlayer film 110 includes an oxide layer or a low dielectric constant material.
[0006] The semiconductor substrate 101 includes a silicon substrate.
[0007] A field oxide 102 is formed on the semiconductor substrate 101 , and the active region is composed of the semiconductor substrate 101 in a region surrounded by the field oxide 102 .
[0008] The dummy gate structure is formed by stacking a dummy gate dielectric layer and a polysilicon dummy gate. The material of the dummy gate dielectric layer includes an oxide layer.
[0009] The gate dielectric layer includes a high dielectric constant layer; the metal gate includes a stacked structure of a metal work function layer and a metal conductive material layer.
[0010] Before step 1, it also includes:
[0011] A spacer 106 is formed on the side of the dummy gate structure. In some embodiments, the material of the spacer 106 includes an oxide layer or a nitride layer.
[0012] Source and drain regions are formed on the surfaces of the active region at both sides of the dummy gate structure.
[0013] An embedded epitaxial layer is formed in the source and drain regions.
[0014] NMOS and PMOS are integrated on the same semiconductor substrate 101 . Figure 1In FIG. 1 , the region indicated by the bracket 103 is a formation region of the NMOS, and the region indicated by the bracket 104 is a formation region of the PMOS.
[0015] In the NMOS formation region, the material of the embedded epitaxial layer 107 includes SiP;
[0016] In the PMOS formation region, the material of the embedded epitaxial layer 108 includes SiGe.
[0017] Before forming the zeroth interlayer film 110, the method further includes forming a contact etching stop layer 109;
[0018] The contact etch stop layer 109 covers the top surface of the dummy gate structure, the side surface of the dummy gate structure and the surface of the source and drain regions between the dummy gate structures;
[0019] After the zeroth interlayer film 110 is planarized, the contact etch stop layer 109 on the top surface of the dummy gate structure is removed.
[0020] Step 2: forming a first interlayer film 111.
[0021] Typically, the first interlayer film 111 is made of an oxide layer.
[0022] Typically, an intermediate mask layer is inserted into the first interlayer film 111, and the intermediate mask layer is formed by stacking a TiN layer 112 and a silicon nitride layer 113. The intermediate mask layer is arranged in the region where the gate structure 105 is spaced relatively large, and is used to make the polishing load of each region in the subsequent metal chemical mechanical polishing process uniform. After the intermediate mask layer is inserted, the first interlayer film 111 is divided into two layers, namely a bottom layer 111a and a top layer 111b.
[0023] The bottom layer 111a is formed by PECVD to form an oxide layer, that is, PEOX. The top layer 111b is formed by CVD process, such as CVD process using LAM equipment.
[0024] The thickness of the bottom layer 111a is The thickness of the TiN layer 112 is The thickness of the silicon nitride layer 113 is The thickness of the top layer 111b is approximately
[0025] Step 3: etching to form a groove 114 of the metal zero layer in the active area, including:
[0026] A formation region of the trench 114 is defined.
[0027] The first interlayer film 111 and the zeroth interlayer film 110 are etched once to form the groove 114 .
[0028] In the actual process, the process structures of the materials of the first interlayer film 111 and the zeroth interlayer film 110 are different. Even if they are both oxide layers, the different formation processes will also make the materials of the two different. During the etching process of the first interlayer film 111 and the zeroth interlayer film 110, it is impossible to ensure that the etching rate at each position is the same, which makes the defined pattern different in the downward transmission process, and it is easy to increase the width of the groove 114 when etching the zeroth interlayer film 110. The width increase area is shown by the dotted circle 115, so that the groove 114 has a bowling profile, which is not conducive to the subsequent metal filling.
[0029] Step 4: Filling metal in the trench 114 to form the active area metal zero layer.
[0030] The metal material of the active area metal zero layer includes tungsten.
[0031] Figure 2 yes Figure 1 The corresponding photo is an electron microscope photo, and it can be seen that the width of the bottom area 115 of the groove 114a increases, so that the morphology of the groove 114 is a bowling ball morphology. Filling the groove 114 with the metal zero layer in the active area easily forms a gap shown by the mark 116, which affects the product quality. Summary of the invention
[0032] The technical problem to be solved by the present invention is to provide a method for manufacturing an active area metal zero layer, which can improve the side morphology of the groove of the active area metal zero layer, prevent the groove from having a bowling ball morphology and thus prevent filling defects.
[0033] In order to solve the above technical problems, the present invention provides a method for manufacturing an active area metal zero layer, comprising the following steps:
[0034] Step 1, providing a semiconductor substrate that has completed a gate replacement process and forming a first etch stop layer; the gate replacement process forms a gate structure in the pseudo gate structure removal area, the gate structure is composed of a gate dielectric layer and a metal gate stacked together, a zeroth layer of interlayer film is formed between the gate structures, the top surface of the gate structure is flush with the top surface of the zeroth layer of interlayer film, the first etch stop layer is formed on the top surface of the gate structure and the top surface of the zeroth layer of interlayer film; the first etch stop layer and the zeroth layer of interlayer film are made of different materials so that the first etch stop layer and the zeroth layer of interlayer film have different etching rates.
[0035] Step 2: forming a first interlayer film on the top surface of the first etch stop layer; the first etch stop layer and the first interlayer film are made of different materials so that the first etch stop layer and the first interlayer film have different etching rates.
[0036] Step 3: etching to form a groove of the metal zero layer in the active area, including:
[0037] A formation area of the groove is defined.
[0038] A first etching is performed, the first etching removing the first interlayer film in the trench formation region and stopping on the surface of the first etch stop layer.
[0039] A second etching is performed to remove the first etching stop layer and stop on the surface of the zeroth interlayer film.
[0040] A third etching is performed to remove the zeroth interlayer film in the groove formation area and thereby form the groove passing through the first interlayer film, the first etch stop layer and the zeroth interlayer film; in the third etching, the first etch stop layer accurately defines the etching area of the zeroth interlayer film, thereby preventing the groove from having a bowling ball morphology.
[0041] The bottom of the trench exposes an active area formed by the semiconductor substrate.
[0042] Step 4: Filling metal in the trench to form the active area metal zero layer.
[0043] A further improvement is that the material of the zeroth interlayer film includes an oxide layer or a low dielectric constant material.
[0044] A further improvement is that the process for forming the zeroth interlayer film includes PECVD, SACVD, HDPCVD or HARP process.
[0045] A further improvement is that the material of the first interlayer film includes an oxide layer or a low dielectric constant material.
[0046] A further improvement is that the material of the first etch stop layer includes silicon nitride.
[0047] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0048] A further improvement is that field oxide is formed on the semiconductor substrate, and the active region is composed of the semiconductor substrate in the region surrounded by the field oxide.
[0049] A further improvement is that the dummy gate structure is formed by stacking a dummy gate dielectric layer and a polysilicon dummy gate.
[0050] A further improvement is that, before step 1, the following steps are further included:
[0051] forming a sidewall spacer on the side of the dummy gate structure;
[0052] Source and drain regions are formed on the surfaces of the active region at both sides of the dummy gate structure.
[0053] A further improvement is that an embedded epitaxial layer is formed in the source and drain regions.
[0054] A further improvement is that NMOS and PMOS are integrated on the same semiconductor substrate;
[0055] In the formation region of the NMOS, the material of the embedded epitaxial layer includes SiP;
[0056] In the PMOS formation region, the material of the embedded epitaxial layer includes SiGe.
[0057] A further improvement is that before forming the zeroth interlayer film, a step of forming a contact etching stop layer is also included;
[0058] The contact etch stop layer covers the top surface of the dummy gate structure, the side surface of the dummy gate structure and the surface of the source and drain regions between the dummy gate structures;
[0059] After planarizing the zeroth interlayer film, the contact etch stop layer on the top surface of the dummy gate structure is removed.
[0060] A further improvement is that, in step three, the third etching stops on the surface of the contact etch stop layer;
[0061] The method further includes removing the contact etching stop layer to expose the surface of the active area at the bottom of the trench.
[0062] A further improvement is that the metal material of the active area metal zero layer includes tungsten.
[0063] A further improvement is that the gate dielectric layer includes a high dielectric constant layer; and the metal gate includes a stacked structure of a metal work function layer and a metal conductive material layer.
[0064] The present invention further adds a step of forming a first etch stop layer after the gate replacement process is completed and before the first interlayer film is formed. The material of the first etch stop layer is different from the material of the bottom zeroth interlayer film and the top first interlayer film, so that selective etching can be achieved between the first etch stop layer and the first interlayer film and between the first etch stop layer and the zeroth interlayer film, so that the etching of the groove can be achieved in a graded manner, that is, the first interlayer film, the first etch stop layer and the zeroth interlayer film are etched in sequence. The graded etching can achieve accurate transfer of the pattern and thus prevent the bottom of the groove from being deformed, especially prevent the groove from being in a bowling ball shape, thereby improving the ability of the metal to fill the groove and preventing the appearance of filling gaps in the metal zero layer of the active area, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0065] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0066] Figure 1 It is a schematic diagram of the cross-sectional structure of a device after a groove is formed in the existing method for manufacturing the active area metal zero layer;
[0067] Figure 2 yes Figure 1 Corresponding photos;
[0068] Figure 3 is a flow chart of a method for manufacturing an active area metal zero layer according to an embodiment of the present invention;
[0069] Figure 4A-4F It is a schematic diagram of the device cross-sectional structure in each step of the method for manufacturing the active area metal zero layer in an embodiment of the present invention. DETAILED DESCRIPTION
[0070] like Figure 3 As shown, it is a flow chart of a method for manufacturing an active area metal zero layer according to an embodiment of the present invention; 4A to 4F FIG. 1 is a schematic diagram of a cross-sectional structure of a device in each step of a method for manufacturing an active area metal zero layer according to an embodiment of the present invention; the method for manufacturing an active area metal zero layer according to an embodiment of the present invention comprises the following steps:
[0071] Step 1: Figure 4A As shown, a semiconductor substrate 201 after a gate replacement process is provided.
[0072] The gate replacement process forms a gate structure 205 in the pseudo gate structure removal area. The gate structure 205 is composed of a gate dielectric layer and a metal gate. A zero-layer interlayer film 210 is formed between the gate structures 205. The top surface of the gate structure 205 is flush with the top surface of the zero-layer interlayer film 210.
[0073] In the embodiment of the present invention, the material of the zeroth interlayer film 210 includes an oxide layer or a low dielectric constant material.
[0074] The zero-th interlayer film 210 is formed by a process including PECVD, SACVD, HDPCVD or HARP.
[0075] The semiconductor substrate 201 includes a silicon substrate.
[0076] A field oxide 202 is formed on the semiconductor substrate 201, and the active region is composed of the semiconductor substrate 201 surrounded by the field oxide 202. In some embodiments, the field oxide 202 is isolated by a shallow trench 216 (STI).
[0077] The dummy gate structure is formed by stacking a dummy gate dielectric layer and a polysilicon dummy gate. The material of the dummy gate dielectric layer includes an oxide layer.
[0078] The gate dielectric layer includes a high dielectric constant layer; the metal gate includes a stacked structure of a metal work function layer and a metal conductive material layer.
[0079] Before step 1, it also includes:
[0080] A spacer 206 is formed on the side of the dummy gate structure. In some embodiments, the material of the spacer 206 includes an oxide layer or a nitride layer.
[0081] Source and drain regions are formed on the surfaces of the active region at both sides of the dummy gate structure.
[0082] An embedded epitaxial layer is formed in the source and drain regions.
[0083] NMOS and PMOS are integrated on the same semiconductor substrate 201 . Figure 4A In the figure, the region indicated by the bracket 203 is a formation region of the NMOS, and the region indicated by the bracket 204 is a formation region of the PMOS.
[0084] In the NMOS formation region, the material of the embedded epitaxial layer 207 includes SiP;
[0085] In the PMOS formation region, the material of the embedded epitaxial layer 208 includes SiGe.
[0086] Before forming the zeroth interlayer film 210, the method further includes forming a contact etching stop layer 209;
[0087] The contact etch stop layer 209 covers the top surface of the dummy gate structure, the side surface of the dummy gate structure and the surface of the source and drain regions between the dummy gate structures;
[0088] After the zeroth interlayer film 210 is planarized, the contact etch stop layer 209 on the top surface of the dummy gate structure is removed.
[0089] like Figure 4B As shown, a first etch stop layer 211 is formed. The first etch stop layer 211 is formed on the top surface of the gate structure 205 and the top surface of the zero-th interlayer film 210; the first etch stop layer 211 and the zero-th interlayer film 210 are made of different materials, so that the first etch stop layer 211 and the zero-th interlayer film 210 have different etching rates.
[0090] In the embodiment of the present invention, the material of the first etch stop layer 211 includes silicon nitride.
[0091] Step 2: Figure 4C As shown, a first interlayer film 212 is formed on the top surface of the first etch stop layer 211 ; the first etch stop layer 211 and the first interlayer film 212 are made of different materials so that the first etch stop layer 211 and the first interlayer film 212 have different etching rates.
[0092] In the embodiment of the present invention, the material of the first interlayer film 212 is an oxide layer. In other embodiments, the material of the first interlayer film 212 can also be a low dielectric constant material.
[0093] In some embodiments, an intermediate mask layer is further inserted into the first interlayer film 212. Figure 4C In the embodiment, the intermediate mask layer is formed by stacking a TiN layer 213 and a silicon nitride layer 214. The intermediate mask layer is arranged in the region where the gate structure 205 is spaced relatively large, so as to make the polishing load of each region in the subsequent metal chemical mechanical polishing process uniform. After inserting the intermediate mask layer, the first interlayer film 212 is divided into two layers, namely a bottom layer 212a and a top layer 212b.
[0094] In some embodiments, the bottom layer 212a is formed by PECVD to form an oxide layer, namely, PEOX, and the top layer 212b is formed by LAMCVD.
[0095] In some embodiments, the thickness of the bottom layer 212a is The thickness of the TiN layer 213 is The thickness of the silicon nitride layer 214 is The thickness of the top layer 212b is approximately
[0096] In some embodiments, a TiN layer 215 is formed on the surface of the first interlayer film 212 and the TiN layer 215 is patterned and etched. The TiN layer 215 covers the top of the source and drain region where the active metal zero layer will not be formed. The patterned etching of the TiN layer 215 will cause less than or equal to The loss makes the thickness of the top layer 212b approximately
[0097] Step 3: etching to form a groove 216 of the metal zero layer in the active area, including:
[0098] A formation region of the trench 216 is defined.
[0099] like Figure 4D As shown, a first etching is performed, and the first etching removes the first interlayer film 212 in the formation region of the trench 216 and stops on the surface of the first etch stop layer 211. The first etching forms the top portion 216a of the trench 216.
[0100] like Figure 4E As shown, a second etching is performed to remove the first etching stop layer 211 and stop on the surface of the zeroth interlayer film 210. After the second etching is completed, the depth of the trench 216 is deepened and is indicated by a mark 216b.
[0101] like Figure 4F As shown, a third etching is performed to remove the zeroth layer interlayer film 210 in the formation area of the groove 216 and thereby form the groove 216 passing through the first layer interlayer film 212, the first etch stop layer 211 and the zeroth layer interlayer film 210; in the third etching, the first etch stop layer 211 accurately defines the etching area of the zeroth layer interlayer film 210, thereby preventing the groove 216 from having a bowling ball morphology.
[0102] The bottom of the trench 216 exposes the active area formed by the semiconductor substrate 201 .
[0103] In the embodiment of the present invention, the third etching stops on the surface of the contact etching stop layer 209;
[0104] Then, the step of removing the contact etching stop layer 209 is further included to expose the surface of the active area at the bottom of the trench 216 .
[0105] Step 4: Filling metal in the trench 216 to form the active area metal zero layer.
[0106] In the embodiment of the present invention, the metal material of the active area metal zero layer includes tungsten.
[0107] The embodiment of the present invention further adds a step of forming a first etch stop layer 211 after the gate replacement process is completed and before the first interlayer film 212 is formed. The material of the first etch stop layer 211 is different from the material of the bottom zeroth interlayer film 210 and the top first interlayer film 212. This allows selective etching between the first etch stop layer 211 and the first interlayer film 212 and between the first etch stop layer 211 and the zeroth interlayer film 210, so that the etching of the groove 216 can be achieved by graded etching, that is, the first interlayer film 212, the first etch stop layer 211 and the zeroth interlayer film 210 are etched in turn. The graded etching can achieve accurate transfer of the pattern and prevent the bottom of the groove 216 from being deformed, especially preventing the groove 216 from having a bowling ball morphology, thereby improving the ability of the metal to fill the groove 216 and preventing the appearance of filling gaps in the metal zero layer of the active area, thereby improving the device performance.
[0108] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing an active area metal zero layer, characterized in that: The steps include: Step 1, providing a semiconductor substrate that has completed a gate replacement process and forming a first etch stop layer; the gate replacement process forms a gate structure in the pseudo gate structure removal area, the gate structure is formed by stacking a gate dielectric layer and a metal gate, a zero-th interlayer film is formed between the gate structures, the top surface of the gate structure is flush with the top surface of the zero-th interlayer film, and the first etch stop layer is formed on the top surface of the gate structure and the top surface of the zero-th interlayer film; the first etch stop layer and the zero-th interlayer film are made of different materials so that the first etch stop layer and the zero-th interlayer film have different etching rates; Step 2: forming a first interlayer film on the top surface of the first etch stop layer; The first etch stop layer and the first interlayer film are made of different materials so that the first etch stop layer and the first interlayer film have different etching rates; An intermediate mask layer is inserted into the first interlayer film, and the intermediate mask layer is formed by stacking a TiN layer and a silicon nitride layer; The intermediate mask layer divides the first interlayer film into two layers, namely a bottom layer and a top layer; The zeroth interlayer film and the first interlayer film are formed by different processes; The bottom layer and the top layer of the first interlayer film are formed by different processes; Step 3: etching to form a groove of the metal zero layer in the active area, including: defining a formation area of the groove; Performing a first etching, wherein the first etching removes the first interlayer film in the groove formation region and stops on the surface of the first etch stop layer; Performing a second etching to remove the first etching stop layer and stop on the surface of the zeroth interlayer film; Performing a third etching to remove the zeroth interlayer film in the formation area of the groove and thereby forming the groove passing through the first interlayer film, the first etch stop layer and the zeroth interlayer film; in the third etching, the first etch stop layer accurately defines the etching area of the zeroth interlayer film, thereby preventing the groove from having a bowling ball morphology; The bottom of the trench exposes an active area formed by the semiconductor substrate; Step 4: Filling metal in the trench to form the active area metal zero layer.
2. The method for manufacturing the active area metal zero layer according to claim 1, characterized in that: The material of the zeroth interlayer film includes an oxide layer or a low dielectric constant material.
3. The method for manufacturing the active area metal zero layer according to claim 2, characterized in that: The formation process of the zero-th interlayer film includes PECVD, SACVD, HDPCVD or HARP process.
4. The method for manufacturing the active area metal zero layer according to claim 2, characterized in that: The material of the first interlayer film includes an oxide layer or a low dielectric constant material.
5. The method for manufacturing the active area metal zero layer according to claim 4, characterized in that: The material of the first etch stop layer includes silicon nitride.
6. The method for manufacturing an active area metal zero layer according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.
7. The method for manufacturing the active area metal zero layer according to claim 6, characterized in that: Field oxide is formed on the semiconductor substrate, and the active region is composed of the semiconductor substrate in a region surrounded by the field oxide.
8. The method for manufacturing the active area metal zero layer according to claim 6, characterized in that: The dummy gate structure is formed by stacking a dummy gate dielectric layer and a polysilicon dummy gate.
9. The method for manufacturing the active area metal zero layer according to claim 7, characterized in that: Before step 1, it also includes: forming a sidewall spacer on the side of the dummy gate structure; Source and drain regions are formed on the surfaces of the active region at both sides of the dummy gate structure.
10. The method for manufacturing the active area metal zero layer according to claim 9, characterized in that: An embedded epitaxial layer is formed in the source and drain regions.
11. The method for manufacturing an active area metal zero layer according to claim 10, characterized in that: NMOS and PMOS are integrated on the same semiconductor substrate; In the formation region of the NMOS, the material of the embedded epitaxial layer includes SiP; In the PMOS formation region, the material of the embedded epitaxial layer includes SiGe.
12. The method for manufacturing an active area metal zero layer according to claim 9, characterized in that: Before forming the zeroth interlayer film, the method further includes forming a contact etching stop layer; The contact etch stop layer covers the top surface of the dummy gate structure, the side surface of the dummy gate structure and the surface of the source and drain regions between the dummy gate structures; After planarizing the zeroth interlayer film, the contact etch stop layer on the top surface of the dummy gate structure is removed.
13. The method for manufacturing an active area metal zero layer according to claim 12, characterized in that: In step three, the third etching stops on the surface of the contact etch stop layer; The method further includes removing the contact etching stop layer to expose the surface of the active area at the bottom of the trench.
14. The method for manufacturing an active area metal zero layer according to claim 1, characterized in that: The metal material of the active area metal zero layer includes tungsten.
15. The method for manufacturing an active area metal zero layer according to claim 1, characterized in that: The gate dielectric layer includes a high dielectric constant layer; the metal gate includes a stacked structure of a metal work function layer and a metal conductive material layer.
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