Semiconductor devices and manufacturing methods thereof

Abstract

A semiconductor device and a manufacturing method thereof, the semiconductor device comprising a substrate, a first thin film transistor and a second thin film transistor. The first and second thin film transistors are arranged on the substrate. The first thin film transistor comprises a first and a second stacked metal oxide layer. The oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, and the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer. The two-dimensional electron gas is located at the interface between the first and second metal oxide layers. The second thin film transistor is electrically connected to the first thin film transistor. The second thin film transistor comprises a third metal oxide layer. The second and third metal oxide layers belong to the same patterned layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a metal oxide layer and a manufacturing method thereof. Background Art

[0002] At present, common thin film transistors usually use amorphous silicon semiconductors as channels, wherein amorphous silicon semiconductors are widely used in various thin film transistors due to their simple process and low cost.

[0003] With the advancement of display technology, the resolution of display panels has been increasing year by year. In order to shrink the thin film transistors in the pixel circuit, many manufacturers are committed to developing new semiconductor materials, such as metal oxide semiconductor materials. Among metal oxide semiconductor materials, indium gallium zinc oxide (IGZO) has the advantages of small area and high electron mobility, so it is regarded as an important new semiconductor material. Summary of the invention

[0004] The present invention provides a semiconductor device having the advantages of high efficiency and low manufacturing cost.

[0005] The invention provides a method for manufacturing a semiconductor device, which has the advantages of low manufacturing cost and high efficiency of the manufactured semiconductor device.

[0006] At least one embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate, a first thin film transistor and a second thin film transistor. The first thin film transistor and the second thin film transistor are arranged on the substrate. The first thin film transistor includes a stacked first metal oxide layer and a second metal oxide layer. The oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, and the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer. The two-dimensional electron gas is located at the interface between the first metal oxide layer and the second metal oxide layer. The second thin film transistor is electrically connected to the first thin film transistor. The second thin film transistor includes a third metal oxide layer. The second metal oxide layer and the third metal oxide layer belong to the same patterned layer.

[0007] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first thin film transistor on a substrate, the first thin film transistor comprising a stacked first metal oxide layer and a second metal oxide layer, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer, and the two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer; forming a second thin film transistor on the substrate, wherein the second thin film transistor is electrically connected to the first thin film transistor, the second thin film transistor comprises a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0009] FIG. 2A to FIG. 2E is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 8 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0016] Description of reference numerals:

[0017] 10,20,30,40,50,60: Semiconductor devices

[0018] 100: Substrate

[0019] 102: Buffer layer

[0020] 110: Gate dielectric layer

[0021] 112: Opening

[0022] 120: Interlayer dielectric layer

[0023] 122: First contact hole

[0024] 124: Second contact hole

[0025] 126: The third contact hole

[0026] 128: Fourth contact hole

[0027] 200: The first thin film transistor

[0028] 210: First metal oxide layer

[0029] 212: Fifth doping region

[0030] 214: Sixth doping region

[0031] 220, 220a: Second metal oxide layer

[0032] 222: First doping region

[0033] 224: Second doping region

[0034] 226: First channel area

[0035] 230: First gate

[0036] 242: The First Source

[0037] 244: First drain

[0038] 300: Second thin film transistor

[0039] 320,320a: Third metal oxide layer

[0040] 322: The third doping region

[0041] 324: Second channel area

[0042] 326: Fourth doping region

[0043] 330,330A: Second grid

[0044] 342: Second Source

[0045] 344: Second drain

[0046] 2DEG: Two-dimensional electron gas

[0047] C: Capacitance

[0048] LED: Light Emitting Diode

[0049] ND: Normal Direction

[0050] OS1: First metal oxide pattern

[0051] OS2: Second metal oxide pattern

[0052] T1, T2, T3: thickness DETAILED DESCRIPTION

[0053] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0054] Please refer to Figure 1 The semiconductor device 10 includes a substrate 100 , a first thin film transistor 200 , and a second thin film transistor 300 .

[0055] The material of the substrate 100 includes, for example, glass, quartz, organic polymer, or opaque / reflective material (eg, conductive material, metal, wafer, ceramic, or other applicable material) or other applicable materials.

[0056] The buffer layer 102 is formed on the surface of the substrate 100. The material of the buffer layer 102 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or other insulating materials. In some embodiments, the buffer layer 102 is a single-layer structure or a multi-layer structure.

[0057] The first thin film transistor 200 is disposed on the substrate 100. In this embodiment, the first thin film transistor 200 is formed on the buffer layer 102. The first thin film transistor includes a first metal oxide layer 210, a second metal oxide layer 220, a first gate 230, a first source 242 and a first drain 244.

[0058] The first metal oxide layer 210 and the second metal oxide layer 220 are located on the substrate 100 and stacked on each other. In the present embodiment, the first metal oxide layer 210 and the second metal oxide layer 220 are sequentially formed on the buffer layer 102. The oxygen concentration of the first metal oxide layer 210 is less than that of the second metal oxide layer 220. In some embodiments, the oxygen concentration of the first metal oxide layer 210 is 10 at% to 50 at%, and the oxygen concentration of the second metal oxide layer 220 is 30 at% to 70 at%. In some embodiments, by adjusting the oxygen concentration, the band gap of the first metal oxide layer 210 is smaller than the band gap of the second metal oxide layer 220, thereby forming a two-dimensional electron gas 2DEG at the interface between the first metal oxide layer 210 and the second metal oxide layer 220. The thickness T2 of the second metal oxide layer 220 is less than the thickness T1 of the first metal oxide layer 210, thereby making it easier for the two-dimensional electron gas 2DEG to form at the aforementioned interface. In some embodiments, the thickness T1 of the first metal oxide layer 210 is 10 nanometers to 60 nanometers, and the thickness T2 of the second metal oxide layer 220 is 5 nanometers to 30 nanometers. In some embodiments, the materials of the first metal oxide layer 210 and the second metal oxide layer 220 include quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or ternary compounds including two metal elements among the quaternary compounds and oxygen.

[0059] The second metal oxide layer 220 includes a first doping region 222, a second doping region 226, and a first channel region 224 located between the first doping region 222 and the second doping region 226. In some embodiments, the first doping region 222 and the second doping region 226 are formed by hydrogen plasma treatment, wherein the oxygen vacancy concentrations of the first doping region 222 and the second doping region 226 are lower than the oxygen vacancy concentration of the first channel region 224, and the conductivity of the first doping region 222 and the second doping region 226 is higher than the conductivity of the first channel region 224.

[0060] The gate dielectric layer 110 is located on the second metal oxide layer 220. In some embodiments, the material of the gate dielectric layer 110 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials. In some embodiments, the thickness of the gate dielectric layer 110 is 50 nanometers to 300 nanometers.

[0061] The first gate 230 is located on the gate dielectric layer 110. The first gate 230 overlaps the first metal oxide layer 210 and the first channel region 224 of the second metal oxide layer 220 in the normal direction ND of the top surface of the substrate 100. The gate dielectric layer 110 is located between the first gate 230 and the second metal oxide layer 220. The first gate 230 contacts the first channel region 224 of the second metal oxide layer 220 through the opening of the gate dielectric layer. In this embodiment, the width of the opening of the gate dielectric layer is smaller than the width of the first channel region 224. In some embodiments, the material of the first gate 230 includes tungsten, molybdenum, platinum, gold or other high work function metals or a combination of the above materials. There is a Schottky contact between the first gate 230 and the second metal oxide layer 220.

[0062] The interlayer dielectric layer 120 is disposed on the gate dielectric layer 110. The interlayer dielectric layer 120 covers the first gate 230. In some embodiments, the material of the interlayer dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide or other insulating materials. In some embodiments, the thickness of the interlayer dielectric layer 120 is 100 nanometers to 600 nanometers.

[0063] The first source 242 and the first drain 244 are disposed on the interlayer dielectric layer 120, and are respectively connected to the first doped region 222 and the second doped region 226 of the second metal oxide layer 220 through contact holes in the interlayer dielectric layer 120. In some embodiments, the materials of the first source 242 and the first drain 244 include aluminum, titanium, molybdenum, copper, or alloys of the above metals, or combinations of the above materials. In some embodiments, there is a Schottky contact or an Ohmic contact between the first source 242 and the second metal oxide layer 220, and between the first drain 244 and the second metal oxide layer 220.

[0064] In the present embodiment, the first thin film transistor 200 is a metal-semiconductor field effect transistor (Metal Semiconductor Field Effect Transistor, MESFET), and the first thin film transistor 200 is a normally-on transistor. Since the first thin film transistor 200 includes a two-dimensional electron gas 2DEG, the first thin film transistor 200 is suitable for a high current driving transistor. In addition, since the first gate 230 of the first thin film transistor 200 contacts the second metal oxide layer 220, the charge trapping effect (charge trapping effect) occurring in the insulating layer between the first gate 230 and the second metal oxide layer 220 can be reduced, thereby improving the efficiency of the first thin film transistor 200.

[0065] The second thin film transistor 300 is disposed on the substrate 100. In the present embodiment, the second thin film transistor 300 is formed on the buffer layer 102. The second thin film transistor includes a third metal oxide layer 320, a second gate 330, a second source 342 and a second drain 344. The second thin film transistor 300 is electrically connected to the first thin film transistor 200. For example, the second drain 344 of the second thin film transistor 300 is connected to the first thin film transistor 200 by Figure 1 The first gate 230 of the first thin film transistor 200 is electrically connected to the first gate 230 of the first thin film transistor 200 through a wire not shown in the figure.

[0066] The third metal oxide layer 320 is located on the substrate 100. In the present embodiment, the third metal oxide layer 320 is formed on the buffer layer 102. In some embodiments, the thickness T3 of the third metal oxide layer 320 is 5 nanometers to 30 nanometers. In some embodiments, the material of the third metal oxide layer 320 includes quaternary compounds such as indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, or a ternary compound including two metal elements and an oxygen element in the aforementioned quaternary compounds. The oxygen concentration of the first metal oxide layer 210 is less than the oxygen concentration of the third metal oxide layer 320. In some embodiments, the second metal oxide layer 220 and the third metal oxide layer 230 belong to the same patterned layer, or it can be said that the shapes of the second metal oxide layer 220 and the third metal oxide layer 230 are defined in the same patterning process. The second metal oxide layer 220 and the third metal oxide layer 230 include the same material.

[0067] The third metal oxide layer 320 includes a third doping region 322, a fourth doping region 326, and a second channel region 324 between the third doping region 322 and the fourth doping region 326. In some embodiments, the third doping region 322 and the fourth doping region 326 are formed by hydrogen plasma treatment, wherein the oxygen vacancy concentration of the third doping region 322 and the fourth doping region 326 is higher than the oxygen vacancy concentration of the second channel region 324, and the conductivity of the third doping region 322 and the fourth doping region 326 is higher than the conductivity of the second channel region 324. In some embodiments, the first doping region 222 and the second doping region 226 of the second metal oxide layer 220 and the third doping region 322 and the fourth doping region 326 of the third metal oxide layer 320 are formed by the same hydrogen plasma treatment.

[0068] The second gate 330 is located on the gate dielectric layer 110. The second gate 330 overlaps the second channel region 324 of the third metal oxide layer 320 in the normal direction ND of the top surface of the substrate 100. The gate dielectric layer 110 is located between the second gate 330 and the third metal oxide layer 320. The second gate 330 does not contact the third metal oxide layer 320. In some embodiments, the first gate 230 and the second gate 330 belong to the same patterned layer, which means that the shapes of the first gate 230 and the second gate 330 are defined in the same patterning process. The first gate 230 and the second gate 330 include the same material.

[0069] The second source 322 and the second drain 326 are disposed on the interlayer dielectric layer 120, and are respectively connected to the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320 through contact holes in the interlayer dielectric layer 120. In some embodiments, the materials of the second source 322 and the second drain 326 include aluminum, titanium, molybdenum, copper, or a combination of the above materials. In some embodiments, there is a Schottky contact or an Ohmic contact between the second source 322 and the third metal oxide layer 320 and between the second drain 326 and the third metal oxide layer 320. In some embodiments, the first source 222, the first drain 226, the second source 322, and the second drain 326 belong to the same patterned layer, which means that the shapes of the first source 222, the first drain 226, the second source 322, and the second drain 326 are defined in the same patterning process. The first source 222 , the first drain 226 , the second source 322 , and the second drain 326 include the same material.

[0070] In the present embodiment, the second thin film transistor 300 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the second thin film transistor 300 is a normally-off transistor.

[0071] FIG. 2A to FIG. 2E is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0072] Please refer to Figure 2A , a first metal oxide pattern OS1 is formed on the substrate 100 . The first metal oxide pattern OS1 includes a first metal oxide layer 210 .

[0073] Please refer to Figure 2B, forming a second metal oxide pattern OS2 on the first metal oxide pattern OS1 and the substrate 100. The second metal oxide pattern OS2 includes a second metal oxide layer 220a and a third metal oxide layer 320a.

[0074] Please refer to Figure 2C A gate dielectric layer 110 is formed on the second metal oxide pattern OS2. The gate dielectric layer 110 has an opening 112 overlapping and exposing the second metal oxide layer 220a.

[0075] Please refer to Figure 2C and 2D , a first gate 230 and a second gate 330 are formed on the gate dielectric layer 110. The second metal oxide layer 220a overlaps the first gate 230, and the third metal oxide layer 320a overlaps the second gate 330. The first gate 230 contacts the second metal oxide layer 220a through the opening 112.

[0076] The second metal oxide layer 220a and the third metal oxide layer 320a are subjected to a doping process using the first gate 230 and the second gate 330 as masks to form the second metal oxide layer 220 including the first doping region 222, the second doping region 226 and the first channel region 224 and the third metal oxide layer 320 including the third doping region 322, the fourth doping region 326 and the second channel region 324. The first channel region 224 is located between the first doping region 222 and the second doping region 226, and the second channel region 324 is located between the third doping region 322 and the fourth doping region 326. In the present embodiment, in the normal direction ND of the top surface of the substrate 100, the first channel region 224 and the second channel region 324 overlap the first gate 230 and the second gate 330, respectively.

[0077] In some embodiments, the doping process is, for example, a hydrogen plasma doping process or other suitable process, through which the oxygen vacancies in the first doping region 222, the second doping region 226, the third doping region 322 and the fourth doping region 326 are reduced to improve the conductivity of the first doping region 222, the second doping region 226, the third doping region 322 and the fourth doping region 326.

[0078] Please refer to Figure 2E, an interlayer dielectric layer 120 is formed on the gate dielectric layer 110. One or more etching processes are performed to form a first contact hole 122, a second contact hole 124, a third contact hole 126, and a fourth contact hole 128 passing through the interlayer dielectric layer 120 and the gate dielectric layer 110. The first contact hole 122 and the second contact hole 124 overlap and expose the first doped region 222 and the second doped region 226 of the second metal oxide layer 220, and the third contact hole 126 and the fourth contact hole 128 overlap and expose the third doped region 322 and the fourth doped region 326 of the third metal oxide layer 320.

[0079] Finally, please refer to Figure 2E and Figure 1 , a first source 242, a first drain 244, a second source 342 and a second drain 344 are formed on the interlayer dielectric layer 120, and the first source 242, the first drain 244, the second source 342 and the second drain 344 are formed in the first contact hole 122, the second contact hole 124, the third contact hole 126 and the fourth contact hole 128. The first source 242 and the first drain 244 are respectively connected to the first doping region 222 and the second doping region 226 of the second metal oxide layer 220, and the second source 342 and the second drain 344 are respectively connected to the third doping region 322 and the fourth doping region 326 of the third metal oxide layer 320.

[0080] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 3 The implementation examples are used Figures 1 to 2E The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0081] Figure 3 The semiconductor device 20 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 20 is that the first gate 230 of the semiconductor device 20 includes a multi-layer structure.

[0082] Please refer to Figure 3 The first gate 230 includes a stack of a metal layer 234 and a P-type semiconductor layer 232, wherein the P-type semiconductor layer 232 contacts the second metal oxide layer 220. In this embodiment, the first thin film transistor 200 is a normally-off transistor.

[0083] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 4 The implementation examples are used Figures 1 to 2E The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0084] Figure 4 The semiconductor device 30 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 30 is that the first source 242 and the first drain 244 of the semiconductor device 30 extend through the second metal oxide layer 220 .

[0085] Please refer to Figure 4 The first source 242 and the first drain 244 extend through the second metal oxide layer 220 and contact the interface between the first metal oxide layer 210 and the second metal oxide layer 220. In other words, the first source 242 and the first drain 244 directly contact the two-dimensional electron gas 2DEG, thereby increasing the output current of the first thin film transistor 200.

[0086] In this embodiment, the second source 342 and the second drain 344 also extend through the third metal oxide layer 320 , but the present invention is not limited thereto. In other embodiments, the second source 342 and the second drain 344 do not pass through the third metal oxide layer 320 .

[0087] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figures 1 to 2E The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0088] Figure 5 The semiconductor device 40 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 40 is that the first metal oxide layer 210 of the semiconductor device 40 includes a fifth doping region 212 and a sixth doping region 214 .

[0089] In the present embodiment, a doping process is performed to form a first doping region 222 and a second doping region 226 in the second metal oxide layer 220, and a fifth doping region 212 and a sixth doping region 214 are formed in the first metal oxide layer 210. In other words, dopants (e.g., hydrogen atoms) in the doping process pass through the second metal oxide layer 220 and reach the first metal oxide layer 210, and form the fifth doping region 212 and the sixth doping region 214 in the first metal oxide layer 210. The fifth doping region 212 and the sixth doping region 214 contact the bottom of the first doping region 222 and the bottom of the second doping region 226, respectively.

[0090] In some embodiments, the thickness of the fifth doping region 212 and the thickness of the sixth doping region 216 are less than the thickness of the first metal oxide layer 210 .

[0091] In some embodiments, the thickness of the first doping region 222, the second doping region 226, the third doping region 322, the fourth doping region 326, the fifth doping region 212 and the width of the sixth doping region 216 gradually decrease as they approach the substrate 100. The surfaces of the first doping region 222 and the second doping region 226 facing the first channel region 224 are curved surfaces, and the surfaces of the third doping region 322 and the fourth doping region 326 facing the second channel region 324 are curved surfaces.

[0092] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 6 The implementation examples are used Figures 1 to 2E The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0093] Figure 6 The semiconductor device 50 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 50 is that the second thin film transistor 300 of the semiconductor device 50 is a bottom gate thin film transistor.

[0094] Please refer to Figure 6 The second gate 330A of the second thin film transistor 300 is located between the third metal oxide layer 320 and the substrate 100. The first gate 230 and the second gate 330A belong to different patterned layers, which means that the shapes of the first gate 230 and the second gate 330A are defined in different patterning processes.

[0095] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 7The implementation examples are used Figures 1 to 2E The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0096] Figure 7 The semiconductor device 60 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 60 is that the second thin film transistor 300 of the semiconductor device 60 is a double-gate thin film transistor.

[0097] Please refer to Figure 6 The second thin film transistor 300 includes two gates, namely, a second gate 330 and a second gate 330A, wherein the third metal oxide layer 320 is located between the second gate 330 and the second gate 330A.

[0098] Figure 8 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. Figure 8 The circuit diagram of the semiconductor device may be any one of the above embodiments.

[0099] Please refer to Figure 8 , the first gate of the first thin film transistor 200 is electrically connected to the second drain of the second thin film transistor 300. In this embodiment, a capacitor C is included between the first drain of the first thin film transistor 200 and the second drain of the second thin film transistor 300, and the first drain of the first thin film transistor 200 is electrically connected to the light emitting diode LED.

[0100] In summary, the first thin film transistor of the present invention includes a first metal oxide layer and a second metal oxide layer, wherein the interface between the first metal oxide layer and the second metal oxide layer has a two-dimensional electron gas, thereby increasing the output current of the first thin film transistor 200 .

Claims

1. A semiconductor device comprising: a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor comprising a first metal oxide layer and a second metal oxide layer stacked, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer, and a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer; as well as a second thin film transistor disposed on the substrate and electrically connected to the first thin film transistor, wherein the second thin film transistor comprises a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer belong to the same patterned layer, The first thin film transistor further comprises: a first gate electrode, overlapping the first metal oxide layer and the second metal oxide layer in a normal direction of the top surface of the substrate, wherein a gate dielectric layer is located between the first gate electrode and the second metal oxide layer, the first gate electrode contacts the second metal oxide layer through an opening of the gate dielectric layer, and an interlayer dielectric layer is disposed on the gate dielectric layer; and A first source electrode and a first drain electrode are disposed on the interlayer dielectric layer and are respectively connected to the second metal oxide layer. The second thin film transistor further comprises: a second gate overlapping the third metal oxide layer in the normal direction of the top surface of the substrate, wherein the gate dielectric layer is located between the second gate and the third metal oxide layer; and A second source and a second drain are disposed on the interlayer dielectric layer and are respectively connected to the third metal oxide layer.

2. The semiconductor device as described in claim 1, wherein the second metal oxide layer includes a first doped region, a second doped region and a first channel region located between the first doped region and the second doped region, the interlayer dielectric layer includes a first contact hole overlapping the first doped region and a second contact hole overlapping the second doped region, the first source is connected to the first doped region through the first contact hole, and the first drain is connected to the second doped region through the second contact hole. 3 . The semiconductor device as claimed in claim 1 , wherein the first source and the first drain extend through the second metal oxide layer and contact the interface between the first metal oxide layer and the second metal oxide layer. 4 . The semiconductor device as claimed in claim 1 , wherein the first gate comprises a stack of a metal layer and a P-type semiconductor layer.

5. The semiconductor device as described in claim 1, wherein the third metal oxide layer includes a third doped region, a fourth doped region and a second channel region located between the third doped region and the fourth doped region, the interlayer dielectric layer includes a third contact hole overlapping the third doped region and a fourth contact hole overlapping the fourth doped region, the second source is connected to the third doped region through the third contact hole, and the second drain is connected to the fourth doped region through the fourth contact hole. 6 . The semiconductor device as claimed in claim 1 , wherein a material of the first gate and the second gate comprises tungsten, molybdenum, platinum, gold or a combination thereof. 7 . The semiconductor device as claimed in claim 2 , wherein the first metal oxide layer comprises a fifth doping region and a sixth doping region, wherein the fifth doping region and the sixth doping region contact the bottom of the first doping region and the bottom of the second doping region respectively. 8 . The semiconductor device as claimed in claim 7 , wherein a thickness of the fifth doping region and a thickness of the sixth doping region are smaller than a thickness of the first metal oxide layer. 9 . The semiconductor device as claimed in claim 1 , wherein materials of the first metal oxide layer, the second metal oxide layer and the third metal oxide layer include indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide or indium tungsten zinc oxide. 10 . The semiconductor device as claimed in claim 1 , wherein an oxygen concentration of the first metal oxide layer is lower than an oxygen concentration of the third metal oxide layer.

11. A method for manufacturing a semiconductor device, comprising: Forming a first thin film transistor on a substrate, the first thin film transistor comprising a first metal oxide layer and a second metal oxide layer stacked, wherein the oxygen concentration of the first metal oxide layer is less than the oxygen concentration of the second metal oxide layer, the thickness of the second metal oxide layer is less than the thickness of the first metal oxide layer, and a two-dimensional electron gas is located at an interface between the first metal oxide layer and the second metal oxide layer; as well as A second thin film transistor is formed on the substrate, wherein the second thin film transistor is electrically connected to the first thin film transistor, the second thin film transistor includes a third metal oxide layer, and the second metal oxide layer and the third metal oxide layer are formed simultaneously.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the method of forming the first thin film transistor on the substrate and the method of forming the second thin film transistor on the substrate comprises: forming a first metal oxide pattern on the substrate, wherein the first metal oxide pattern comprises the first metal oxide layer; forming a second metal oxide pattern on the first metal oxide pattern and the substrate, wherein the second metal oxide pattern includes the second metal oxide layer and the third metal oxide layer; forming a gate dielectric layer on the second metal oxide pattern, wherein the gate dielectric layer has an opening exposing the second metal oxide layer; forming a first gate on the gate dielectric layer, wherein the first gate contacts the second metal oxide layer through the opening; forming a second gate, wherein the third metal oxide layer overlaps the second gate; performing a doping process on the second metal oxide layer and the third metal oxide layer; forming an interlayer dielectric layer on the gate dielectric layer; A first source, a first drain, a second source and a second drain are formed on the interlayer dielectric layer, wherein the first source and the first drain are respectively connected to the second metal oxide layer, and the second source and the second drain are respectively connected to the third metal oxide layer.

13. A method for manufacturing a semiconductor device as described in claim 12, wherein the doping process is performed to form a first doping region, a second doping region and a first channel region located between the first doping region and the second doping region in the second metal oxide layer, and a third doping region, a fourth doping region and a second channel region located between the third doping region and the fourth doping region in the third metal oxide layer. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the doping process is performed to form a fifth doping region and a sixth doping region in the first metal oxide layer. 15 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein the doping process is performed using the first gate and the second gate as masks.

16. The method for manufacturing a semiconductor device according to claim 12, further comprising: Performing one or more etching processes to form a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole through the interlayer dielectric layer and the gate dielectric layer, wherein the first contact hole and the second contact hole overlap the second metal oxide layer, and the third contact hole and the fourth contact hole overlap the third metal oxide layer; and The first source, the first drain, the second source and the second drain are formed in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole. 17 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein the first source and the first drain extend through the second metal oxide layer, and the second source and the second drain extend through the third metal oxide layer.

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