A readout circuit with current mirror as input stage

Abstract

The present invention relates to the field of readout circuits, and discloses a readout circuit with a current mirror as an input stage, including a current mirror input circuit arranged outside a chip, the current mirror input circuit including a blind pixel branch, a first branch path mirroring the blind pixel branch, the gate of a first PMOS transistor in the blind pixel branch is connected to the gate of a second PMOS transistor in the first branch path, the source of a first NMOS transistor in the blind pixel branch is grounded through a series blind pixel resistor, and also includes a second branch path mirroring the input end of the basic pixel circuit, the gate of the second NMOS transistor in the first branch path is connected to the gate of a third NMOS transistor in the second branch path, and the gate and source of the third PMOS transistor in the second branch path are respectively connected to the gate and source of a fourth PMOS transistor in the basic pixel circuit. The present invention solves the problem of pixel-level circuits being limited in area by introducing a current mirror structure on a traditional bridge.

Description

Technical Field

[0001] The invention relates to the field of readout circuits, and in particular to a readout circuit with a current mirror as an input stage. Background Art

[0002] The infrared readout circuit is an important component of the infrared detector. Its functions are to provide the bias voltage required for the detection pixel and to output the information of the detection array in an orderly manner row by row and column by column. In the process of infrared radiation to image presentation, the performance of the readout circuit itself plays a great role. With the continuous development of the readout circuit technology, the readout circuit integrates more and more functions, such as on-chip analog-to-digital conversion and on-chip non-uniformity correction. Among them, the on-chip analog-to-digital conversion is divided into chip level, column level and pixel level. At present, infrared readout circuits mostly use column-level analog-to-digital conversion channels to perform analog-to-digital conversion on array signals row by row. When the infrared readout circuit occupies too large an area due to high precision or reduces the processing capacity of the circuit due to low power consumption, it is necessary to compromise its actual application scenario. The infrared readout circuit is generally composed of an input stage, an analog-to-digital conversion module, and a latch module, and is now gradually developing towards the pixel level.

[0003] The input stage in the traditional bridge subtracts the current flowing through the pixel and the blind pixel to "eliminate the large and keep the small". The small current integral of the pixel temperature change is read out. Although it can effectively read the infrared signal, it is not suitable for application scenarios that require high integration. The reason is that with the significant reduction in pixel area, the column-level circuit can no longer meet the needs of miniaturization due to its low integration. Therefore, in application scenarios where the temperature gradient is large and miniaturization is required, it is particularly important to carry out research on pixel-level input stage circuits. Summary of the invention

[0004] In order to solve the problem of limited area of ​​pixel-level circuits, the unit circuit no longer uses the traditional column-level structure, and the input stage is split outside the chip. The present invention copies the current of the blind pixel branch in the form of a current mirror, and eliminates the influence of the blind pixel in the form of a difference before amplifying the signal current.

[0005] The present invention is achieved through the following technical solutions:

[0006] A readout circuit with a current mirror as an input stage, including a basic pixel circuit arranged in a chip, and also including a current mirror input circuit arranged outside the chip, the current mirror input circuit includes a blind pixel branch, a first branch path mirroring the blind pixel branch, the gate of a first PMOS transistor in the blind pixel branch is connected to the gate of a second PMOS transistor in the first branch path, and the source of a first NMOS transistor in the blind pixel branch is grounded through a series blind pixel resistor, and also includes a second branch path that is a mirror image of the input end of the basic pixel circuit, the gate of the second NMOS transistor in the first branch path is connected to the gate of a third NMOS transistor in the second branch path, and the gate and source of the third PMOS transistor in the second branch path are respectively connected to the gate and source of a fourth PMOS transistor in the basic pixel circuit.

[0007] As an optimization, the blind element branch includes a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected to the bias voltage through a first resistor in series, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor.

[0008] As an optimization, the first branch includes a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is connected to the bias voltage through a second resistor in series, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor, and the source of the second NMOS transistor is grounded.

[0009] As an optimization, the second branch includes a third PMOS transistor and a third NMOS transistor, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is respectively connected to the drain of the third PMOS transistor and the gate of the third PMOS transistor.

[0010] As an optimization, the basic pixel circuit includes a pixel branch, an integration circuit and an A / D conversion module, the pixel branch includes a fourth PMOS transistor and a fourth NMOS transistor, the source and gate of the fourth PMOS transistor are respectively connected to the source and gate of the third PMOS tube, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the inverting input terminal of the integration circuit, the source of the fourth NMOS transistor is grounded through a series pixel resistor, and the source of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0011] As an optimization, the resistance of the first resistor and the second resistor is 4 times the resistance of the blind resistor.

[0012] As an optimization, one A / D conversion module corresponds to four integration circuits through control switches, and each integration circuit corresponds to a blind pixel branch, a first branch circuit, a second branch circuit and a pixel branch.

[0013] As an optimization, the first NMOS transistor and the fourth NMOS transistor are manufactured using a deep N-well process.

[0014] As an optimization, the blind element resistor and the pixel resistor are both manufactured using MEMS technology.

[0015] As an optimization, the pixel resistor is a thermistor with a negative temperature coefficient.

[0016] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0017] The present invention introduces a current mirror structure on a traditional bridge to convert temperature changes into current changes, and provides them for subsequent signal processing. It utilizes bridge balance, current replication, up and down difference and other methods to serve as the input stage of a pixel-level readout circuit and has performance reference value. It has a simple structure and a small area, and solves the problem of area limitation of pixel-level circuits. It is in line with the principle that current readout circuits are developing towards the pixel level. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 A circuit connection diagram of a readout circuit with a current mirror type as an input stage according to the present invention;

[0020] Figure 2 This is a basic circuit architecture diagram for a pixel.

[0021] Marks and corresponding parts names in the attached drawings:

[0022] 1-Current mirror input circuit, 2-Basic pixel circuit. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0024] Example

[0025] A readout circuit with a current mirror as an input stage, comprising a basic pixel circuit 2 arranged in a chip, and also comprising a current mirror input circuit 1 arranged outside the chip, wherein the current mirror input circuit 1 comprises a blind pixel branch, and a first branch path mirroring the blind pixel branch, wherein the gate of a first PMOS transistor M1 in the blind pixel branch is connected to the gate of a second PMOS transistor M2 in the first branch path, and the source of a first NMOS transistor M3 in the blind pixel branch is grounded via a series blind pixel resistor Rb, and also comprises a second branch path mirroring the input end of the basic pixel circuit, The gate of the second NMOS transistor M4 of the first branch is connected to the gate of the third NMOS transistor M5 of the second branch, and the gate and source of the third PMOS transistor M6 of the second branch are respectively connected to the gate and source of the fourth PMOS transistor M7 of the basic pixel circuit, that is, the gate of the third PMOS transistor M6 of the second branch is connected to the gate of the fourth PMOS transistor M7 of the basic pixel circuit, and the source of the third PMOS transistor M6 of the second branch is connected to the source of the fourth PMOS transistor M7 of the basic pixel circuit.

[0026] In this embodiment, the blind element branch includes a first PMOS transistor M1 and a first NMOS transistor M3, the source of the first PMOS transistor M1 is connected to the bias voltage Vsk through a first resistor R1 connected in series, and the drain of the first PMOS transistor M1 is connected to the drain of the first NMOS transistor M3 and the gate of the first NMOS transistor M3; the first branch includes a second PMOS transistor M2 and a second NMOS transistor M4, the source of the second PMOS transistor M2 is connected to the bias voltage Vsk through a second resistor R2 connected in series, the drain of the second PMOS transistor M3 is connected to the drain of the second NMOS transistor M4 and the gate of the second NMOS transistor M4, and the source of the second NMOS transistor M4 is grounded; the second branch includes a third PMOS transistor M6 and a third NMOS transistor M5, the source of the third NMOS transistor M5 is connected to the The basic pixel circuit comprises a pixel branch, an integration circuit and an A / D conversion module. The pixel branch comprises a fourth PMOS transistor M7 and a fourth NMOS transistor M8. The source and gate of the fourth PMOS transistor M7 are respectively connected to the source and gate of the third PMOS transistor, that is, the source of the fourth PMOS transistor M7 is connected to the source of the third PMOS transistor, the gate of the fourth PMOS transistor M7 is connected to the gate of the third PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the inverting input terminal of the integration circuit, the source of the fourth NMOS transistor is grounded through a series pixel resistor, and the source of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0027] like Figure 1 As shown in the figure, the current mirror input circuit 1 on the left is placed outside the chip, and the basic pixel circuit 2 on the right is inside the chip. One current mirror input circuit is configured for one row in the entire pixel plane, that is, in units of rows, there are several current mirror input circuits corresponding to several rows of the array, and the pixel branch, integration circuit, and A / D conversion module (analog-to-digital converter) can be placed inside the chip.

[0028] The first PMOS transistor M1 to the second NMOS transistor M4, the second NMOS transistor M4 to the third NMOS transistor M5, the third PMOS transistor M6 and the fourth PMOS transistor M7 form three pairs of basic current mirrors, with the same bias voltage V sk 、V ebIt is ensured that the source and gate voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are the same. It can be known from the square law relationship that the currents of the first branch and the blind branch are equal. In this way, the current of the blind branch is transmitted to the third NMOS transistor M5 through the second NMOS transistor M4. Since the third NMOS transistor M5 and the third PMOS transistor M6 are on the same branch (connected to the second branch), the current transmitted from the blind branch continues to maintain a 1:1 transmission in the form of a current mirror of the third PMOS transistor M6 to the fourth PMOS transistor M7. When there is no external input signal, the blind pixel current (the current flowing through the blind pixel resistor Rb) is equal to the pixel current flowing through the pixel resistor Rs, and the output is theoretically zero; when there is an external input signal (a change in the input signal, which is a change in the resistance of Rs caused by the change in ambient temperature), at the drain node of the fourth PMOS transistor M7 and the fourth NMOS transistor M8, the current of the blind pixel branch will differ from the current of the pixel branch, and the difference is manifested as flowing into or out of the CTIA (the circuit diagram shows an operational amplifier connected to a capacitor, and the full name of CTIA is capacitor feedback transimpedance amplifier, which is a reset integrator composed of an operational amplifier and a feedback integrating capacitor). The pixel resistor Rs is a thermistor with a negative temperature coefficient. Assuming that the ambient temperature rises, the resistance of the pixel resistor Rs decreases according to the negative temperature coefficient of the pixel resistor Rs, which means that the current in the pixel branch increases, that is, the current is "drawn" into the CTIA and integrated upward. In other words, the output integral voltage of the CTIA is higher than the reference voltage of the integral circuit. If the ambient temperature decreases, the opposite is true, that is, the integral voltage of the CTIA is lower than the reference voltage of the integral circuit. Finally, the integral result is input into the A / D conversion module to be compared with the ramp signal. After comparison, a flip signal is generated to be stored in the latch, and then digitized into Gray code with a low bit error rate, and then converted into binary as needed. The basic circuit architecture of a pixel is shown below. Figure 2 shown.

[0029] Specifically, the bias voltage V sk The external power supply is given as a value greater than the power supply voltage (the power supply value given outside the pixel on the chip), ensuring that the power supply voltage is almost "lossless" (because if the bias voltage is given by another source, it is not easily affected by the power supply voltage, and even if it passes through a MOS transistor to reach the determined Veb voltage point, the tiny voltage consumed will not have a big impact), through a four-fold blind element resistor (the first resistor and the second resistor, the resistance of the first resistor and the second resistor is equal to the bias voltage V sk After that, V eb (This voltage is the abbreviation of a bias voltage of the infrared balanced bridge) The DC bias is provided by the off-chip source follower (a circuit structure that provides a bias voltage in the bias module inside the chip outside the pixel), V fidThe DC bias is generated by short-circuiting the drain and source to the pixel resistor. Both blind pixel resistors and pixel resistors adopt MEMS technology. The main advantages of sensors made by MEMS technology are small size, light weight, low power consumption, high reliability, high sensitivity, easy integration, and low manufacturing cost after averaging. They are the main force of micro sensors.

[0030] The gates of the first PMOS transistor M1 to the second PMOS transistor M2 are all connected by an external V eb A bias voltage is provided, and when the current of the blind branch is determined, the connection relationship between the gate and the source determines that the current flowing through the first PMOS transistor and the second PMOS transistor is the same, that is, the current size of the second branch is determined.

[0031] The second NMOS transistor M4 and the third NMOS transistor M5 are used as the intermediate "carriers" for transmitting the blind element current. The degree of matching determines the accuracy of the copied current. Therefore, when designing the parameter channel length L of the second NMOS transistor and the third NMOS transistor, the L value needs to be designed to be slightly larger (by fine-tuning the width-to-length ratio, when L is about 4 times the minimum line width, it is not greatly affected by channel modulation and the current can be copied more accurately), and the coordination of the second NMOS transistor M4 and the third NMOS transistor M5 in the same branch is fully considered (the coordination here means that the currents on both sides of M1 to M4 are equal, which is symmetrical in a certain sense, so the accurate replication of the current mirror is very important, not just to avoid channel modulation). Doing so can not only avoid the channel modulation effect as much as possible, but also has certain benefits in reducing noise.

[0032] The first NMOS transistor M3 and the fourth NMOS transistor M8 are biased by a diode with a short gate and drain, and the gate voltages of the first NMOS transistor M3 and the fourth NMOS transistor M8 are the same, which means that the bias voltage of the blind element resistor and the pixel resistor is regulated by the drain voltage of the first PMOS transistor M1 and the blind element branch current. In addition, the first NMOS transistor M3 and the fourth NMOS transistor M8 are the connection points for the "communication" between the blind element resistor and the pixel resistor, and therefore, they are more sensitive to the noise of the substrate of the NMOS transistor and have stricter noise requirements. Therefore, the first NMOS transistor M3 and the fourth NMOS transistor M8 need to adopt DeepN-Well (deep N well process) for isolation and thus reduce noise.

[0033] According to the above analysis, M 3 、M 4 、M 6The size is very critical, because M6 and M7 have the same size, M7, M8 and the pixel divide the voltage of AVDD in this branch. To ensure balance (no input, output is zero), the voltage at the drain end of M7 and M8 is very critical. M7 needs to occupy a larger Vgs, so the width-to-length ratio needs to be smaller than the width. M8 does not need to be the same as M3, and it can be matched. It determines the accuracy of the readout signal, which is equivalent to the current path and is affected by multiple factors such as power consumption, size, bias current, and noise.

[0034] The blind pixel current of the traditional structure is only affected by the MOS transistor and the blind pixel resistor with fixed bias voltage. In the novel current mirror structure of the present invention, the blind pixel current and the pixel current can be mutually controlled after the size is designed. The purpose is to increase the coordination of the circuit and reduce the error between the blind pixel and the pixel. Compared with the traditional structure in which the blind pixel resistor and the pixel resistor adopt fixed bias voltage, the flexibility of self-adaptation is enhanced. The bias voltage of Veb and Vfid affects the current, and the current affects the bias voltage. The error between the current and the bias voltage can be offset back and forth in the operation of the structure of the present invention. In addition, since the present invention adopts a large number of current mirrors, in order to pursue perfect current mirror matching, the influence of channel modulation will be reduced as much as possible (through fine-tuning the width-to-length ratio, L is about 4 times the minimum line width, which is not greatly affected by channel modulation, and the current can be copied more accurately. When the noise is W*L slightly larger (L is large), the parasitic capacitor can also filter out a little noise, which can reduce flicker noise, and it will be better at low frequency). This purpose is the same as the requirement of suppressing noise.

[0035] When the ambient temperature changes, the pixel resistance and blind pixel resistance have a coefficient (different resistance values ​​caused by mismatch and temperature change) α:

[0036] R s =R b (1+α)

[0037] Assume that each MOS transistor operates in the saturation region and V gs (The first formula below is for M1, and the second is for M3) are almost equal, then:

[0038] V eb =V sk -4·I b ·R b -V gs1

[0039] V fid =I b ·R b +V gs3

[0040] I b -I s =1 / 2·μ1 C ox (W / L) 1 (V eb -V sk +4·I b ·R b -V TH1 ) 2 -1 / 2·μ 8 C ox (W / L) 8 (V fid -I s ·R s -V TH8 ) 2

[0041] Among them, I b Indicates that the current flows through the blind resistor R b The blind element current, I s Represents the current flowing through the pixel resistor R s The pixel current, μ 1 , μ 8 The mobilities of electrons and holes in the first PMOS transistor M1 and the fourth NMOS transistor M8 are respectively corresponding. W / L represents the width-to-length ratio of the MOS corresponding to the subscript. V eb 、V fid Represents a given bias voltage, V TH1 、V TH8 Each represents a threshold voltage of the first PMOS transistor M1 and the fourth NMOS transistor M8.

[0042] Substituting the mobility of NMOS into about twice that of PMOS (the multiple of mobility represents an estimate or a general rule, which may change slightly due to differences in process and temperature, etc.), and the absolute values ​​of the thresholds are approximately equal, then:

[0043] I b -I s =μ 1 / 2·C ox [(W / L) 1 (V eb -V sk -V TH1 +4·I b ·R b ) 2 -2(W / L) 8 (V fid -V TH8 -I s ·(1+α)·R b ) 2 ]

[0044] The simple derivation of the above formula proves again that Veb 、V fid Bias voltage affects current I b ,I s , the current affects the bias voltage, thus providing a more accurate reference for fixing the blind pixel resistor bias voltage, and the self-adjusting pixel resistor bias voltage has a certain positive effect on the adaptation of the blind pixel resistor and the pixel resistor, thereby reducing the noise and mismatch rate.

[0045] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A readout circuit with a current mirror as an input stage, comprising a basic pixel circuit arranged in a chip, characterized in that: It also includes a current mirror input circuit arranged outside the chip, the current mirror input circuit includes a blind pixel branch, a first branch path mirroring the blind pixel branch, the gate of the first PMOS transistor in the blind pixel branch is connected to the gate of the second PMOS transistor in the first branch path, the source of the first NMOS transistor in the blind pixel branch is grounded through a series blind pixel resistor, and also includes a second branch path mirroring the input end of the basic pixel circuit, the gate of the second NMOS transistor in the first branch path is connected to the gate of the third NMOS transistor in the second branch path, and the gate and source of the third PMOS transistor in the second branch path are respectively connected to the gate and source of the fourth PMOS transistor in the basic pixel circuit; The blind element branch includes a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected to a bias voltage via a first resistor in series, and the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the first NMOS transistor; The first branch includes a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is connected to the bias voltage through a second resistor in series, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor, and the source of the second NMOS transistor is grounded; The second branch includes a third PMOS transistor and a third NMOS transistor, the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor and the gate of the third PMOS transistor respectively; The basic pixel circuit includes a pixel branch, an integration circuit and an A / D conversion module. The pixel branch includes a fourth PMOS transistor and a fourth NMOS transistor. The source and gate of the fourth PMOS transistor are respectively connected to the source and gate of the third PMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor and the inverting input terminal of the integration circuit, the source of the fourth NMOS transistor is grounded through a series pixel resistor, and the source of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor.

2. A readout circuit with a current mirror as an input stage according to claim 1, characterized in that: The resistance of the first resistor and the second resistor is 4 times the resistance of the blind resistor.

3. The readout circuit with a current mirror as an input stage according to claim 1, characterized in that: One A / D conversion module corresponds to four integration circuits through control switches, and each integration circuit corresponds to a blind element branch, a first branch circuit, a second branch circuit and a pixel branch.

4. The readout circuit with a current mirror as an input stage according to claim 1, characterized in that: The first NMOS transistor and the fourth NMOS transistor are manufactured by using a deep N-well process.

5. The readout circuit with a current mirror as an input stage according to claim 1, characterized in that: The blind element resistor and the pixel resistor are both made using MEMS technology.

6. The readout circuit with a current mirror as an input stage according to claim 1, characterized in that: The pixel resistor is a thermistor with a negative temperature coefficient.

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