Electronic device, chip packaging structure and manufacturing method thereof

Abstract

An electronic device, a chip packaging structure and a manufacturing method thereof; wherein the chip packaging structure comprises a first chip (10), an adapter board (20) and at least one electrical connector (30) located between the first chip (10) and the adapter board (20), wherein two ends of the electrical connector (30) are electrically connected to the first chip (10) and the adapter board (20) respectively; and further comprises: a high thermal conductivity medium (40) located between the first chip (10) and the adapter board (20) and arranged around the outer periphery of the electrical connector (30), wherein one end of the high thermal conductivity medium (40) is in contact with the first chip (10) to achieve electrical connection to the first chip (10). The chip (10) and the electrical connector (30) are effectively cooled, thereby improving the integration of the chip packaging structure. An insulating layer (50) is provided between the high thermal conductivity medium (40) and the electrical connector (30). The insulating layer (50) is used to separate the high thermal conductivity medium (40) from the electrical connector (30) to prevent the current on the electrical connector (30) from diffusing to the high thermal conductivity medium (40) and causing leakage. This not only ensures the conduction stability between the first chip (10) and the adapter board (30), but also does not cause interference to the electrical signals of the components outside the chip packaging structure.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit packaging, and in particular to an electronic device, a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Flip chip is not only a chip interconnection technology, but also an ideal chip bonding technology. It has become a packaging form commonly used in high-end devices and high-density packaging fields. With the widespread application of flip chips, the power consumption density of chips is getting higher and higher. At the same time, packaging structures formed by stacking multiple chips have also appeared, which puts higher requirements on the heat dissipation of chips.

[0003] The existing flip chip packaging structure mainly includes a chip, electrical connectors such as copper pillars, and a substrate, wherein the electrical connector is located between the chip and the substrate, and the two ends are electrically connected to the chip and the substrate respectively to achieve conduction of electrical signals between the chip and the substrate. At the same time, the gap in the packaging structure formed by the chip, the electrical connector and the substrate is filled with underfill (UF) to reduce the stress between the substrate and the chip caused by the mismatch of thermal expansion coefficients, thereby improving the reliability of the electrical connection between the electrical connector and the substrate.

[0004] However, the existing bottom filler has limited heat dissipation performance, which seriously restricts the integration and power consumption of the chip. In addition, when a bottom filler with higher thermal conductivity is used, it will cause leakage in the electrical connector, affecting the conduction stability between the chip and the substrate. Summary of the invention

[0005] The present application provides an electronic device, a chip packaging structure and a manufacturing method thereof, which prevents the electrical connectors in the chip packaging structure from leaking electricity while ensuring the heat dissipation efficiency of the chip packaging structure, thereby ensuring the electrical conduction stability between the chip and an adapter board such as a substrate.

[0006] In a first aspect, an embodiment of the present application provides a chip packaging structure, comprising: a first chip, an adapter board, and at least one electrical connector located between the first chip and the adapter board, wherein two ends of the electrical connector are electrically connected to the first chip and the adapter board respectively;

[0007] It also includes: a high thermal conductivity medium located between the first chip and the adapter board and surrounding the outer periphery of the electrical connector, one end of the high thermal conductivity medium is in contact with the first chip, and an insulating layer is arranged between the high thermal conductivity medium and the electrical connector, and the insulating layer is used to separate the high thermal conductivity medium from the electrical connector.

[0008] By setting a high thermal conductivity medium on the periphery of the electrical connector between the first chip and the adapter board, and contacting one end of the high thermal conductivity medium with the first chip, the heat on the first chip and the electrical connector can be effectively diffused to the high thermal conductivity medium, and then the heat is released to the external environment through the high thermal conductivity medium, which effectively improves the heat dissipation efficiency of the first chip and the electrical connector, thereby providing a good heat dissipation foundation for improving the chip integration and power consumption. At the same time, the high thermal conductivity medium and the electrical connector are separated by an insulating layer to prevent the current on the electrical connector from diffusing to the high thermal conductivity medium and causing leakage, thereby not only ensuring the conduction stability between the first chip and the adapter board, but also preventing interference to the electrical signals of the components outside the chip packaging structure.

[0009] In a possible implementation of the first aspect, the insulating layer is wrapped around at least a portion of the side wall of the electrical connector, and the high thermal conductivity medium is wrapped around the surface of the insulating layer facing away from the electrical connector. In this way, not only is effective heat dissipation of the first chip achieved through the high thermal conductivity medium, but also the high thermal conductivity medium is prevented from directly contacting the electrical connector and causing leakage of the electrical connector.

[0010] In a possible implementation of the first aspect, there are multiple electrical connectors, and the multiple electrical connectors are arranged at intervals; and the intervals between adjacent electrical connectors are filled with the high thermal conductivity medium. In this way, on the one hand, the high thermal conductivity medium filled between two adjacent connectors can dissipate heat for the electrical connectors on both sides at the same time, thereby effectively improving the heat dissipation efficiency of the high thermal conductivity medium for each electrical connector. On the other hand, the high thermal conductivity medium filled between adjacent electrical connectors also supports the two electrical connectors and the first chip, so that the electrical connector can be more stably supported between the first chip and the adapter board, thereby ensuring the conduction between the first chip and the adapter board. At the same time, the high thermal conductivity medium located between two adjacent electrical connectors is separated from any of the electrical connectors by an insulating layer, so that there will be no short circuit between the adjacent electrical connectors due to the conductivity of the high thermal conductivity medium, further ensuring the normal conduction of the electrical signal by each electrical connector.

[0011] In a possible implementation of the first aspect, the first end of the insulating layer extends to an end of the electrical connector close to the first chip, and the second end of the insulating layer extends to a preset distance from the adapter board. In this way, while ensuring the coverage area of ​​the insulating layer on the surface of the electrical connector, by exposing a portion of the electrical connector close to the adapter board, the end of the electrical connector can be effectively wetted and spread when the electrical connector is welded on the adapter board, thereby further ensuring the welding stability between the electrical connector and the adapter board.

[0012] In a possible implementation of the first aspect, the distance between one end of the high thermal conductivity medium facing the adapter board and the adapter board is greater than or equal to the distance between the second end of the insulating layer and the adapter board. In other words, the end of the high thermal conductivity medium close to the adapter board can extend to be flush with the second end of the insulating layer, or can be higher than the second end of the insulating layer. In this way, while ensuring the heat dissipation effect of the high thermal conductivity medium surrounding the outer periphery of the insulating layer on the electrical connector and the first chip, the high thermal conductivity medium is effectively prevented from extending out of the second end of the insulating layer and contacting the electrical connector on one side of the insulating layer, thereby further preventing the electrical connector from leaking electricity. When the high thermal conductivity medium is filled in the gap between adjacent electrical connectors, a short circuit between adjacent electrical connectors due to current conduction by the high thermal conductivity medium is also avoided.

[0013] In a possible implementation manner of the first aspect, the chip packaging structure further includes an underfill, and a thermal conductivity of the underfill is smaller than a thermal conductivity of the high thermal conductivity medium;

[0014] The underfill is filled between the insulating layer and the adapter plate and between the high thermal conductivity medium and the adapter plate.

[0015] By filling a bottom filler with a higher thermal conductivity and a lower thermal conductivity between the insulating layer and the adapter board and between the high thermal conductivity medium and the adapter board, support is provided for the bottom of the insulating layer and the high thermal conductivity medium, thereby reducing the stress between the adapter board and the first chip caused by the mismatch of thermal expansion coefficients, improving the welding reliability between the electrical connector and the adapter board and the structural stability of the insulating layer and the high thermal conductivity medium, and at the same time, since the thermal conductivity of the bottom filler is relatively small, it will not have conductive properties, and therefore will not cause leakage or short circuit in the electrical connector.

[0016] In a possible implementation manner of the first aspect, the electrical connector is any one of a micro bump and a controllable collapse bump.

[0017] In a possible implementation of the first aspect, the electrical connector includes: a copper column and a tin bump electrically connected to the copper column, one end of the copper column is electrically connected to the first chip, the tin bump is arranged between the copper column and the adapter board and is electrically connected to the adapter board; the second end of the insulating layer extends to the end of the copper column close to the adapter board; part of the bottom filler extends to contact the outer side of the tin bump. By exposing the tin bump used to connect the copper column and the adapter board to the outside of the insulating layer, the diffusion process of the tin bump when welding with the adapter board is prevented from being hindered by the insulating layer and affecting the welding stability of the tin bump and the adapter board. In addition, by filling part of the bottom filler in the outer side wall of the tin bump, the structural stability of the tin bump in the chip structure after packaging is further improved, thereby further ensuring the reliability of the electrical connection between the tin bump and the adapter board.

[0018] In a possible implementation of the first aspect, the high thermal conductivity medium includes one or more of the following materials: solder, silver paste, graphene, and aluminum oxide particles. The above materials can improve the heat dissipation efficiency of the first chip and the electrical connector in the chip packaging structure.

[0019] In a possible implementation of the first aspect, the high thermal conductivity medium is formed by stacking nanowires or nanoparticles; and the gaps between the nanowires or between the nanoparticles are filled with an oxidizing medium to enhance the bonding strength between the nanowires or between the nanoparticles, thereby enhancing the structural stability of the high thermal conductivity medium formed by the stacking of nanowires or nanoparticles, thereby ensuring the thermal conductivity of the nano thermal conductive medium, and also improving its structural support effect on the first chip and each electrical connector.

[0020] In a possible implementation manner of the first aspect, the insulating layer is a copper oxide layer; or, the insulating layer is a tin oxide layer; or, the insulating layer is a dry film or a passivation layer made of an insulating material.

[0021] In a possible implementation of the first aspect, the insulating layer is a tin oxide layer, and a barrier layer is provided between the tin oxide layer and the outer side wall of the electrical connector. Generally, the manufacturing process of the tin oxide insulating layer is to first immerse tin on the surface of the electrical connector and then oxidize it into tin oxide. The present application provides a barrier layer on the surface of the electrical connector to prevent tin from excessively reacting with metals such as copper in the electrical connector to generate intermetallic compounds that are detrimental to the mechanical structure and electrical properties of the electrical connector, thereby further ensuring the structural stability of the electrical connector and the stable conduction between the first chip and the adapter board.

[0022] In a possible implementation of the first aspect, the barrier layer is a film layer made of Ni, Ti, W, or TaN. The film layer made of Ni, Ti, W, or TaN can block tin from metal compounds in the electrical connector, thereby ensuring smooth growth of tin oxide.

[0023] In a possible implementation of the first aspect, a mounting hole is provided on the adapter board, a ground connection point or a power connection point is provided in the mounting hole, and at least a portion of the second end of the high thermal conductivity medium is in contact with the ground connection point or the power connection point. By contacting the second end of the high thermal conductivity medium with the ground connection point or the power connection point on the adapter board, effective heat dissipation of the ground connection point or the power connection point is achieved, thereby improving the electrical performance of other connection points of the adapter board.

[0024] In a possible implementation of the first aspect, a metal pad is provided on the adapter board, one end of the metal pad extends into the mounting hole and contacts the ground connection point or the power connection point, and the other end of the metal pad contacts the high thermal conductivity medium.

[0025] In a possible implementation of the first aspect, the adapter board is a second chip; or the adapter board is a substrate. That is, the chip packaging structure can be mounted on a component such as a circuit board through the second chip or the substrate to achieve conduction between the first chip and the component such as the circuit board.

[0026] In a second aspect, an embodiment of the present application provides an electronic device, comprising any of the chip packaging structures described above.

[0027] By setting the above chip packaging structure in the electronic device, due to the good heat dissipation effect of the chip packaging structure, a highly integrated chip packaging structure can be set in the electronic device, so that while enhancing the function of the electronic device, the size occupied by the chip packaging structure in the electronic device is reduced, which not only provides effective space for the installation of other components in the electronic device, but also reduces the size of the entire electronic device and optimizes the experience effect of the electronic device. At the same time, it also ensures the stability of signal transmission in the electronic device and ensures the normal operation of the electronic device.

[0028] In a third aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, the method comprising:

[0029] providing a first chip;

[0030] Prepare at least one electrical connection member on one side of the first chip, and the electrical connection member is electrically connected to the first chip;

[0031] forming an insulating layer on the outer side wall of the electrical connector, wherein the insulating layer at least covers a portion of the outer side wall of the electrical connector;

[0032] A high thermal conductivity medium is arranged on a surface of the first chip having the electrical connector, the high thermal conductivity medium is arranged around the outer periphery of the electrical connector, and the insulating layer separates the high thermal conductivity medium from the electrical connector;

[0033] An adapter plate is provided, wherein the adapter plate is electrically connected to an end of the electrical connector facing away from the first chip to form a chip packaging structure.

[0034] By arranging a high thermal conductivity medium around the electrical connector, and contacting one end of the high thermal conductivity medium with the first chip, the heat on the first chip and the electrical connector can be effectively diffused to the high thermal conductivity medium, and then the heat is released to the external environment through the high thermal conductivity medium, which effectively improves the heat dissipation efficiency of the first chip and the electrical connector, thereby providing a good heat dissipation foundation for improving the integration and power consumption of the chip. At the same time, the high thermal conductivity medium and the electrical connector are separated by an insulating layer to avoid the current on the electrical connector from diffusing to the high thermal conductivity medium and causing leakage, thereby not only ensuring the conduction stability between the first chip and the adapter board, but also not causing electrical signal interference to the components outside the chip packaging structure. In addition, in the manufacturing process of the chip packaging structure, before welding the adapter board, the high thermal conductivity medium is first filled on the periphery of the electrical connector, making the filling process of the high thermal conductivity medium simpler and faster, and while ensuring the filling uniformity, it can reduce the difficulty of process manufacturing, effectively improving the manufacturing efficiency and product quality.

[0035] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, the method comprising:

[0036] providing a first chip;

[0037] Prepare at least one electrical connection member on one side of the first chip, and the electrical connection member is electrically connected to the first chip;

[0038] forming an insulating layer on the outer side wall of the electrical connector, wherein the insulating layer at least covers a portion of the outer side wall of the electrical connector;

[0039] Providing an adapter board, wherein the adapter board is electrically connected to an end of the electrical connector facing away from the first chip;

[0040] By arranging a high thermal conductivity medium around the electrical connector, and contacting one end of the high thermal conductivity medium with the first chip, the heat on the first chip and the electrical connector can be effectively diffused to the high thermal conductivity medium, and then the heat is released to the external environment through the high thermal conductivity medium, which effectively improves the heat dissipation efficiency of the first chip and the electrical connector, thereby providing a good heat dissipation foundation for improving the integration and power consumption of the chip. At the same time, the high thermal conductivity medium and the electrical connector are separated by an insulating layer to avoid the current on the electrical connector from diffusing to the high thermal conductivity medium and causing leakage, thereby not only ensuring the conduction stability between the first chip and the adapter plate, but also not causing interference to the electrical signals of the components outside the chip packaging structure. In addition, relative to the manufacturing method provided in the third aspect, the fourth aspect of the embodiment of the present application can first weld the adapter plate to the end of the electrical connector away from the first chip, and then fill the high thermal conductivity medium, that is, the present application does not have excessive requirements on the process manufacturing sequence, as long as a chip packaging structure that meets the requirements is finally made.

[0041] In a possible implementation manner of the third aspect or the fourth aspect, forming an insulating layer on an outer side wall of the electrical connector includes:

[0042] The outer side wall of the electrical connector is oxidized to form an oxide layer on the outer side wall of the electrical connector, and the oxide layer serves as the insulating layer.

[0043] By directly oxidizing the surface of the electrical connector to form an insulating layer that prevents current diffusion on the electrical connector, while ensuring that the electrical connector will not leak or short-circuit, it also simplifies the manufacturing process of the insulating layer and improves the manufacturing efficiency of the chip packaging structure.

[0044] In a possible implementation manner of the third aspect or the fourth aspect, forming an insulating layer on an outer side wall of the electrical connector includes:

[0045] Dipping the outer side wall of the electrical connector into tin to form a tin layer on the outer side wall of the electrical connector;

[0046] The tin layer is oxidized to form a tin oxide layer, and the tin oxide layer serves as the insulating layer.

[0047] The tin oxide layer is used as the insulating layer, which improves the insulating performance of the insulating layer and ensures that the electrical connector will not leak or short-circuit.

[0048] In a possible implementation manner of the third aspect or the fourth aspect, before tinning the outer side wall of the electrical connector, the method further includes:

[0049] forming a barrier layer on the outer side wall of the electrical connector by electroplating or sputtering;

[0050] The step of tinning the outer side wall of the electrical connector to form a tin layer on the outer side wall of the electrical connector comprises:

[0051] The barrier layer on the outer side wall of the electrical connector is tinned to form the tin layer on the barrier layer.

[0052] A barrier layer is formed on the outer wall of the electrical connector before tinning, and tinning is performed on the barrier layer to prevent tin from quickly combining with metals such as copper on the surface of the electrical connector to form intermetallic compounds that are detrimental to the mechanical structure and electrical properties of the electrical connector.

[0053] In a possible implementation of the third aspect or the fourth aspect, forming an insulating layer on the outer wall of the electrical connector includes: pasting an insulating dry film or an insulating passivation layer on the outer wall of the electrical connector, and the insulating dry film or the insulating passivation layer serves as the insulating layer to simplify the manufacturing process of the insulating layer.

[0054] In a possible implementation manner of the third aspect or the fourth aspect, the high thermal conductivity medium is a nanomaterial; after the high thermal conductivity medium is disposed around the periphery of the electrical connector, the method further includes: filling an oxidizing medium in gaps between the nanomaterials.

[0055] By filling the gaps between the nanomaterials with an oxidizing medium, the bonding strength between the nanowires or nanoparticles is enhanced, thereby enhancing the structural stability of the high thermal conductivity medium formed by the stacking of nanowires or nanoparticles, thereby ensuring the thermal conductivity of the nano thermal conductive medium, and also improving its structural support effect on the first chip and various electrical connectors.

[0056] In a possible implementation manner of the third aspect or the fourth aspect, preparing at least one electrical connection member on one side of the first chip includes:

[0057] Prepare at least one copper pillar on one side of the first chip;

[0058] A tin bump electrically connected to the copper column is formed at one end of the copper column facing the adapter plate;

[0059] The adapter board is electrically connected to an end of the electrical connector facing away from the first chip, including:

[0060] The adapter plate is electrically connected to an end of the tin bump facing away from the first chip.

[0061] By arranging a copper column with high conductivity and mechanical strength on one side of the first chip, stable transmission of electrical signals between the first chip and the adapter board is achieved, while ensuring the stability of the chip packaging structure. In addition, by arranging a tin bump at one end of the copper column, stable welding with the adapter board is achieved.

[0062] In a possible implementation manner of the third aspect or the fourth aspect, there is a gap between one end of the insulating layer facing the adapter plate and the adapter plate, and a distance between one end of the high thermal conductivity medium facing the adapter plate and the adapter plate is greater than or equal to a distance from the insulating layer to the adapter plate;

[0063] Before forming the chip packaging structure, the method further includes:

[0064] The gap between the insulating layer and the adapter plate and the gap between the high thermal conductivity medium and the adapter plate are filled with an underfill material, and the underfill material contacts the outer side surface of the tin bump.

[0065] By setting the insulating layer toward one end of the adapter plate and the interval between the adapter plate, so that the part of the electrical connector near the end of the adapter plate is exposed, it is ensured that the end of the electrical connector near the adapter plate can be smoothly wetted and extended when welding with the adapter plate, thereby further ensuring the stability of the electrical connection between the electrical connector and the adapter plate. At the same time, the end of the high thermal conductivity medium near the adapter plate can extend to be flush with the second end of the insulating layer, or can be higher than the second end of the insulating layer. In this way, while ensuring the heat dissipation effect of the high thermal conductivity medium surrounding the outer periphery of the insulating layer on the electrical connector and the first chip, it is effectively avoided that the high thermal conductivity medium extends out of the second end of the insulating layer and contacts the electrical connector on one side of the insulating layer, thereby further preventing the electrical connector from leaking electricity, and when the high thermal conductivity medium is filled in the interval between adjacent electrical connectors, it is also avoided that the short circuit between adjacent electrical connectors due to the current conduction of the high thermal conductivity medium occurs. By filling the bottom filler with a higher thermal conductivity and a smaller thermal conductivity between the insulating layer and the adapter plate and between the high thermal conductivity medium and the adapter plate, the bottom of the insulating layer and the high thermal conductivity medium can be supported, thereby reducing the stress between the adapter plate and the first chip caused by the mismatch of thermal expansion coefficients, improving the welding reliability between the electrical connector and the adapter plate and the structural stability of the insulating layer and the high thermal conductivity medium, and at the same time, since the thermal conductivity of the bottom filler is small, it will not have conductive properties, so it will not cause leakage or short circuit of the electrical connector. By filling part of the bottom filler on the outer side wall of the tin bump, the structural stability of the tin bump in the chip structure after packaging is further improved, thereby further ensuring the reliability of the electrical connection between the tin bump and the adapter plate.

[0066] In a possible implementation manner of the third aspect or the fourth aspect, before the adapter board is electrically connected to an end of the electrical connector facing away from the first chip, the method further includes:

[0067] A metal pad is formed on a surface of the adapter board facing the first chip, one end of the metal pad is electrically connected to a ground connection point or a power connection point on the adapter board, and the other end of the metal pad is used to contact the high thermal conductivity medium when the adapter board is connected to the electrical connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1a A schematic diagram of a first structure of a chip packaging structure provided in an embodiment of the present application;

[0069] Figure 1b A second structural schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0070] Figure 2 A third structural schematic diagram of the chip packaging structure provided in the first embodiment of the present application;

[0071] Figure 3A fourth structural schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0072] Figure 4 A fifth structural schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0073] Figure 5a A schematic diagram of the structure of a first chip in a first method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application;

[0074] Figure 5b A schematic diagram of a structure in which an electrical connector is manufactured on the surface of a first chip in a first manufacturing method of a chip packaging structure provided in Embodiment 1 of the present application;

[0075] Figure 5c A schematic diagram of a structure in which an insulating layer is formed on an outer side wall of an electrical connector in a first method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application;

[0076] Figure 5d A schematic diagram of the structure after the adapter plate is electrically connected to an end of the electrical connector facing away from the first chip in the first manufacturing method of the chip packaging structure provided in the first embodiment of the present application;

[0077] Figure 5e A schematic diagram of a structure in which a high thermal conductivity medium is filled around the periphery of an electrical connector in a first manufacturing method of a chip packaging structure provided in Embodiment 1 of the present application;

[0078] Figure 6a A schematic diagram of the structure of a first chip in a second method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application;

[0079] Figure 6b A schematic diagram of a structure in which an electrical connector is manufactured on the surface of a first chip in the second manufacturing method of the chip packaging structure provided in the first embodiment of the present application;

[0080] Figure 6c A schematic diagram of a structure in which an insulating layer is formed on an outer side wall of an electrical connector in a second method for manufacturing a chip packaging structure provided in the first embodiment of the present application;

[0081] Figure 6d A schematic diagram of a structure in which a high thermal conductivity medium is filled on the periphery of an electrical connector in a second method for manufacturing a chip packaging structure provided in the first embodiment of the present application;

[0082] Figure 6e A schematic diagram of the structure after the adapter plate is electrically connected to an end of the electrical connector facing away from the first chip in the second manufacturing method of the chip packaging structure provided in the first embodiment of the present application;

[0083] Figure 7A sixth structural schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0084] Figure 8 A seventh structural schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0085] Fig. 9 This is a schematic diagram of an eighth structure of a chip packaging structure provided in an embodiment of the present application.

[0086] Description of reference numerals:

[0087] 10 - first chip; 20 - adapter board; 30 - electrical connector; 31 - copper pillar; 32 - tin bump; 40 - high thermal conductivity medium; 41 - extension part; 50 - insulating layer; 60 - barrier layer; 70 - bottom filler; 80 - metal pad. DETAILED DESCRIPTION

[0088] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0089] As we all know, the chip is the core part of electronic devices, which has the function of logic processing and controlling the normal operation of the whole machine. In electronic devices, the chip is mainly fixed on the circuit board in the form of a chip packaging structure to achieve the purpose of stable control of the chip inside the chip packaging structure and the external circuit board. Flip chip is both a chip interconnection technology and an ideal chip bonding technology. It has become a packaging form commonly used in the field of high-end devices and high-density packaging.

[0090] With the development of science and technology and the growing needs of mankind, the integration of chips in flip-chip packaging structures needs to be further improved, that is, the number of connection points on the chips in the flip-chip packaging structure, i.e., the number of pins or chip stacks, needs to be increased to meet the needs of electronic devices with more functions without increasing the size of the structure. At the same time, the power consumption of the flip-chip packaging structure also increases. In order to meet the requirements of high integration and high power consumption of the flip-chip packaging structure, the heat dissipation efficiency of the chip packaging structure needs to be better.

[0091] In the related art, the flip chip packaging structure mainly includes a chip, electrical connectors such as copper pillars, and a substrate, wherein the electrical connector is located between the chip and the substrate, and the two ends are electrically connected to the chip and the substrate respectively to achieve the conduction of electrical signals between the chip and the substrate, and the electrical connection points on the substrate are electrically connected to the circuit board, thereby achieving the conduction between the chip and the circuit board in the flip chip packaging structure. Underfill (UF) is filled in the gap of the packaging structure formed by the chip, the electrical connector, and the substrate to reduce the stress between the substrate and the chip caused by the mismatch of the thermal expansion coefficient, thereby improving the reliability of the electrical connection between the electrical connector and the substrate.

[0092] Generally, the bottom filler can be composed of epoxy resin and silicon dioxide, which has low heat dissipation performance and cannot meet the requirements of high-integration and high-power chip packaging structures. Therefore, it will seriously restrict the integration and power density of the chip in the chip packaging structure, and thus it is impossible to increase the function of the electronic device on the basis of saving the internal space of the electronic device. In order to solve the above problems, the related art uses fillers with high heat dissipation performance to fill the gaps in the chip packaging structure to improve the heat dissipation effect of the chip.

[0093] It should be understood by those skilled in the art that materials with high thermal conductivity usually have a certain degree of electrical conductivity. Thus, when materials with high thermal conductivity are filled around electrical connectors such as copper pillars in a chip packaging structure, part or all of the current on the electrical connectors will diffuse into the materials with high thermal conductivity, causing leakage in the chip packaging structure, thereby affecting the conduction stability between the chip and the substrate.

[0094] Based on this, the present application provides an electronic device, a chip packaging structure and a manufacturing method thereof, by providing a high thermal conductivity medium on the periphery of the electrical connector, and providing an insulating layer between the high thermal conductivity medium and the outer wall of the electrical connector, so as to ensure the heat dissipation effect of the chip while preventing leakage of the electrical connector, thereby ensuring the signal conduction stability between the chip and the substrate and other adapter boards. The specific structure of the chip packaging structure is introduced below using different scenarios as examples.

[0095] Scene 1

[0096] Figure 1a A schematic diagram of a first structure of a chip packaging structure provided in an embodiment of the present application; Figure 1b A second structural schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 2 A third structural schematic diagram of the chip packaging structure provided in the first embodiment of the present application; Figure 3 A fourth structural schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 4 This is a fifth structural diagram of a chip packaging structure provided by an embodiment of the present application. Figures 1a to 4 As shown, the present application provides a chip packaging structure, including a first chip 10, an adapter board 20, and at least one electrical connector 30 located between the first chip 10 and the adapter board 20, wherein two ends of the electrical connector 30 are electrically connected to the first chip 10 and the adapter board 20, respectively, to achieve conduction of electrical signals between the first chip 10 and the adapter board 20.

[0097] The first chip 10 may be any chip structure in the prior art, and the embodiment of the present application does not limit the specific type or structure of the first chip 10 as long as it can realize certain logic processing or control functions.

[0098] It should be noted that the adapter board 20 of the embodiment of the present application specifically plays the role of achieving conduction between the first chip 10 and the external circuit board, carrying the first chip 10, and stabilizing the package structure formed by the first chip 10 on the external circuit board. The adapter board 20 can be a substrate (Substrate) in the usual sense, a redistribution layer (Redistribution Layer, RDL), a silicon substrate (also called interposer in English), etc.

[0099] The chip packaging structure of the present application is fixed on the circuit board of the electronic device through the adapter board 20, and the electrical connection points (metal pads) on the adapter board 20 are electrically connected to the corresponding electrical connection points (metal pads) on the circuit board, so as to realize the conduction between the first chip 10 and the external circuit board, thereby ensuring that the external circuit board provides a stable current to the first chip 10, and also realizing the signal transmission between the first chip 10 and the external circuit board.

[0100] In some scenarios, two or more chips are stacked up and packaged together, and signals can be transmitted between two adjacent chips through the electrical connector 30. Therefore, in a possible embodiment, the adapter board 20 can also be one or more chips. It should be noted that the first chip described in the embodiment of the present invention can be a bare chip (Die), or it can be a packaging structure formed by packaging one or more bare chips together.

[0101] When the adapter board 20 is a substrate, the substrate provides a rearrangement of the pins of the first chip 10 within a larger plane range to achieve multi-pinning and pin position rearrangement. In addition, because the connection points on the substrate are larger in size, the first chip 10 can be accurately connected to the corresponding connection points of the external circuit board. In other words, the substrate plays a role in enlarging the size of the connection points of the first chip 10, making the first chip 10 more accurate and quick to connect with the external circuit board. When the adapter board 20 is a chip, in order to distinguish it from the above-mentioned first chip 10, the chip used to carry the first chip 10 is called the second chip. The second chip realizes the conduction between the first chip 10 and the external circuit board, and at the same time realizes the fixation of the chip packaging structure with the external circuit board. Among them, the distribution position and number of the connection points of the second chip can be consistent with the substrate to ensure that the second chip can well realize the electrical connection with the corresponding electrical connector 30 and the external circuit board.

[0102] Reference Figure 1a As shown, the embodiment of the present application also includes a high thermal conductivity medium 40 located between the first chip 10 and the adapter board 20. The high thermal conductivity medium 40 is arranged around the periphery of the electrical connector 30, and one end of the high thermal conductivity medium 40 is in contact with the first chip 10, specifically, in contact with the surface of the first chip 10 facing the adapter board 20, so that the heat on the first chip 10 is effectively transferred to the high thermal conductivity medium 40, and then the high thermal conductivity medium 40 quickly transfers the heat to the outside, thereby achieving effective heat dissipation of the first chip 10 by the high thermal conductivity medium 40. At the same time, the high thermal conductivity medium 40 is also located on the periphery of the electrical connector 30, thereby also achieving effective heat dissipation of the electrical connector 30.

[0103] It is understandable that the high thermal conductivity medium 40 also supports the first chip 10 and the electrical connector 30 to reduce the deformation of the first chip 10 and the electrical connector 30, thereby making the connection between the first chip 10 and the electrical connector 30 more stable.

[0104] It should be noted that the thermal conductivity of the high thermal conductivity medium 40 is higher than the thermal conductivity of the bottom filler (UF) filled in the gap of the chip packaging structure in the related art, so as to improve the heat dissipation efficiency of the first chip 10 and the electrical connector 30, thereby meeting the heat dissipation requirements of the chip packaging structure with high integration and high power consumption.

[0105] The high thermal conductivity medium 40 may include but is not limited to any one or more of the following materials: solder, silver paste (epoxy), graphene. For example, the high thermal conductivity medium 40 of the present application may be a silver paste coated or printed on the periphery of the electrical connector 30 to achieve effective heat dissipation of the first chip 10 and the electrical connector 30. For another example, the high thermal conductivity medium 40 may be a mixed material composed of silver paste and solder coated or printed on the periphery of the electrical connector 30. It should be noted that the above-mentioned materials such as solder, silver paste (epoxy), and graphene are not nanomaterials.

[0106] As a possible implementation, the high thermal conductivity medium 40 may be formed by stacking nanomaterials such as nanowires (Nanowire, NW) or nanoparticles. The nanowires or nanoparticles may be composed of metal materials (such as Au, Ag, Ge), semiconductor materials (such as Si), metal alloy materials (such as Fe-Co), metal oxide materials (such as LiNiO2, CdO), etc. This embodiment does not specifically limit the composition of the nanowires or nanoparticles.

[0107] When the high thermal conductivity medium 40 is composed of nanowires, a plurality of nanowires are intertwined to form a structure similar to a ball of yarn, and the nanowires may be wound randomly or in accordance with certain rules.

[0108] Figure 1a What is shown is another winding method when the high thermal conductivity medium 40 is composed of nanowires, such as Figure 1a As shown, each nanowire of the nanowire structure extends from the first chip 10 toward the adapter board 20, and multiple nanowires are stacked in sequence along a direction parallel to the first chip 10 until the actual required thickness of the high thermal conductivity medium 40 is reached, completing the filling of the nanowire structure. The thickness of the high thermal conductivity medium 40 refers to the distance between the two side surfaces of the high thermal conductivity medium 40 along the extension direction parallel to the first chip 10, refer to Figure 1a As shown in d.

[0109] When the high thermal conductivity medium 40 is composed of nanoparticles, multiple nanoparticles can be stacked from the surface of the insulating layer 50 to the direction away from the insulating layer 50 until the required thickness of the high thermal conductivity medium 40 is reached, or multiple nanoparticles can be stacked from the surface of the first chip 10 toward the adapter board 20 to the adapter board 20 until the required height of the high thermal conductivity medium 40 is reached. It should be noted that the height of the high thermal conductivity medium 40 specifically refers to the distance between the two ends of the high thermal conductivity medium 40 along the direction perpendicular to the first chip 10, refer to Figure 1a As shown in e.

[0110] In actual applications, during the stacking process, nanowires or nanoparticles may produce gaps between individual nanowires or nanoparticles due to the stacking force, the structural characteristics of the material itself, etc., resulting in a large number of gaps in the high thermal conductivity medium 40 formed by the stacking of nanowires or nanoparticles. These gaps will directly affect the structural strength and thermal conductivity of the high thermal conductivity medium 40.

[0111] Based on this, as another possible implementation of the thermal conductive medium 40, an oxidizing medium can be filled in the gaps between the nanowires or nanoparticles of the high thermal conductive medium 40 to enhance the bonding strength between the nanowires or nanoparticles, thereby enhancing the structural stability of the high thermal conductive medium 40 formed by the nanomaterial, thereby ensuring the thermal conductivity of the nano thermal conductive medium, and also improving its structural support effect on the first chip 10 and the electrical connector 30. It can be understood that in this example, the high thermal conductive medium 40 is composed of a plurality of nanowires and an oxidizing medium disposed between the plurality of nanowires, or the high thermal conductive medium 40 is composed of a plurality of nanoparticles and an oxidizing medium disposed between the plurality of nanoparticles.

[0112] In order to improve the compatibility of the oxidizing medium and the nanomaterial, the other constituent elements in the oxidizing medium except oxygen can be consistent with the main constituent elements of the nanomaterial, so that the binding strength between the oxidizing medium and the nanomaterial can be enhanced, and then the binding strength between the nanowires or nanoparticles can be enhanced. For example, when the nanowire is a silver nanowire, the oxidizing medium is silver oxide; when the nanowire is a titanium nanowire, the oxidizing medium is titanium oxide; when the nanowire is a Si nanowire, the oxidizing medium is silicon dioxide.

[0113] In addition, the other constituent elements in the oxidizing medium except oxygen can be consistent with the main constituent elements of the nanomaterial, which can further ensure the thermal conductivity of the final high thermal conductivity medium 40.

[0114] Continue to refer to Figure 1a As shown, the structure of the embodiment of the present invention also includes an insulating layer 50. The insulating layer 50 wraps the side surface of the electrical connector 30 to isolate the high thermal conductivity medium 40 from the electrical connector 30. For example, the insulating layer 50 is wrapped on a part of the side wall of the electrical connector 30, and the high thermal conductivity medium 40 is wrapped on the surface of the insulating layer 50 away from the electrical connector 30, that is, the outer surface of the insulating layer 50. Such a configuration avoids the current on the electrical connector 30 from diffusing to the high thermal conductivity medium 40 and causing leakage, thereby not only ensuring the conduction stability between the first chip 10 and the adapter board 20, but also preventing interference to the electrical signals of the components outside the chip packaging structure.

[0115] In practical applications, the number of the electrical connector 30 can be one or more. When the number of the electrical connector 30 is one, a high thermal conductivity medium 40 is disposed around the outer periphery of the electrical connector 30, and an insulating layer 50 is disposed between the high thermal conductivity medium 40 and the electrical connector 30 to prevent the current on the electrical connector 30 from diffusing to the high thermal conductivity medium 40 and affecting the electrical transmission stability of the electrical connector 30. When there are multiple electrical connectors 30, the multiple electrical connectors 30 are arranged in a matrix at the bottom of the first chip 10, and the high thermal conductivity medium 40 is filled in the gaps between adjacent electrical connectors 30. In this way, on the one hand, the high thermal conductivity medium 40 filled between two adjacent connectors 30 can provide heat dissipation for the electrical connectors 30 on both sides at the same time, thereby effectively improving the heat dissipation efficiency of the high thermal conductivity medium 40 for each electrical connector 30. On the other hand, the high thermal conductivity medium 40 filled between adjacent electrical connectors 30 also supports the two electrical connectors 30 and the first chip 10, so that the electrical connector 30 can be more stably supported between the first chip 10 and the adapter board 20, thereby ensuring the conduction between the first chip 10 and the adapter board 20.

[0116] Generally, materials with high thermal conductivity will have electrical conductivity. Therefore, in order to achieve effective heat dissipation for the first chip 10 while avoiding direct contact between the high thermal conductivity medium 40 with certain electrical conductivity and the electrical connector 30, this embodiment provides an insulating layer 50 between the high thermal conductivity medium 40 located between two adjacent electrical connectors 30 and any one of the electrical connectors 30, that is, the high thermal conductivity medium 40 is separated from each electrical connector 30 by the insulating layer 50, so that adjacent electrical connectors 30 will not be short-circuited due to the conductivity of the high thermal conductivity medium 40, further ensuring that each electrical connector 30 is normally conductive to its corresponding electrical signal, while ensuring effective heat dissipation of the first chip 10 by the high thermal conductivity medium 40.

[0117] It can be understood that because one end of the high thermal conductivity medium 40 extends to contact the inner surface of the first chip 10 (i.e., the surface facing the adapter board 20), for example, one end of the high thermal conductivity medium 40 extends to the end of the electrical connector 30 close to the first chip 10, the first end of the insulating layer 50 also extends to the end of the electrical connector 30 close to the first chip 10, so as to avoid direct contact between the high thermal conductivity medium 40 and the side wall of the electrical connector 30.

[0118] It should be noted that the first end of the insulating layer 50 refers to an end of the insulating layer 50 close to the first chip 10 , and the second end of the insulating layer 50 refers to an end of the insulating layer 50 close to the adapter board 20 .

[0119] In practical applications, in order to achieve electrical conduction between the first chip 10 and the adapter board 20, the electrical connector 30 may be a micro bump or a controlled collapse chip interconnect structure (Controlled Collapse Chip Connection, referred to as C4), such as Figure 1b As shown, the controllable collapse chip interconnect structure is also called a controllable collapse bump. Figure 1b In the embodiment, the electrical connector 30 can be a micro-bump or a controllable collapse bump. The structures and components of the micro-bump and the controllable collapse bump in the present application can be directly referred to the contents recorded in the prior art.

[0120] Reference Figure 1a As shown, in some examples, the electrical connector 30 can also be a structure formed by a copper pillar (Cu Pillar, CuP) 31 and a tin bump 32 arranged at one end of the copper pillar 31, wherein the copper pillar 31 is electrically connected to the adapter board 20 through the tin bump 32. Any of the above types of electrical connectors 30 are fixed to the adapter board 20 by welding. It should be understood by those skilled in the art that the welding process needs to ensure that the end of the electrical connector such as the micro-bump or the controllable collapse bump close to the adapter board 20 has a certain degree of meltability and fluidity at high temperature, so that during the welding process, the end of the electrical connector 30 close to the adapter board 20 can be wetted and spread on the surface of the adapter board 20 under the action of high temperature, and stably welded to the adapter board 20 after cooling.

[0121] Based on this, the second end of the insulating layer 50 of the embodiment of the present application extends to a preset distance a between the second end and the adapter plate 20, such as Figure 1a and Figure 1b As shown. For example, the side wall of one end of the electrical connector 30 close to the adapter plate 20 is exposed, and the insulating layer 50 does not cover the side wall of the one end of the electrical connector 30 close to the adapter plate 20. In this way, when the electrical connector 30 is welded on the adapter plate 20, the end of the electrical connector 30 can effectively wet and spread in the horizontal direction, thereby further ensuring the welding stability between the electrical connector 30 and the adapter plate 20. It should be noted that when the insulating layer 50 does not cover the side wall of one end of the electrical connector 30 close to the adapter plate 20, the end of the high thermal conductivity medium 40 facing the adapter plate 20 will not exceed the end of the insulating layer 50 facing the adapter plate 20, for example, the high thermal conductivity medium 40 will not contact the exposed side wall of the electrical connector 30.

[0122] It can be understood that the specific value of the preset spacing a can be determined according to actual welding requirements, and the embodiments of the present application do not limit this.

[0123] In the embodiment of the present application, the arrangement of the insulating layer 50 is described by taking the electrical connector 30 including the copper column 31 and the tin bump 32 arranged at one end of the copper column 31 as an example. Figure 1a As shown, one end of the copper pillar 31 of the electrical connector 30 is electrically connected to the first chip 10, and the tin bump 32 is connected to one end of the copper pillar 31 close to the adapter board 20. For example, the tin bump 32 is located between the copper pillar 31 and the adapter board 20 and is electrically connected to the adapter board 20, thereby achieving electrical conduction between the first chip 10 and the adapter board 20. The tin bump 32 is a soldering tin bump made of tin, that is, a tin soldering tin bump, to ensure that the copper pillar 31 and the tin bump 32 are both electrical conductors. Because the copper pillar 31 itself cannot be connected to the adapter board 20 by welding, a tin bump 32 made of tin is set at the bottom end of the copper pillar 31, so as to achieve connection and conduction between the copper pillar 31 and the adapter board 20 by welding the tin bump 32 to the adapter board 20.

[0124] It is understandable that during the welding process of the tin bump 32 and the adapter plate 20, the tin bump 32 must first be properly wetted and spread on the adapter plate 20 under high temperature before the tin bump 32 can be stably welded on the adapter plate 20. Figure 1a As shown, the second end of the insulating layer 50 of the embodiment of the present application may extend to one end of the copper pillar 31 close to the adapter board 20. For example, the insulating layer 50 completely covers the outer wall of the copper pillar 31, but the tin bump 32 may not be covered by the insulating layer 50. In this way, the tin bump 32 under the copper pillar 31 is completely exposed at the insulating layer 50 to prevent the insulating layer 50 from hindering the wetting and spreading of the tin bump 32.

[0125] Of course, in some other examples, the second end of the insulating layer 50 may also extend to part of the outer side of the tin bump 32. For example, the outer side of one end of the tin bump 32 close to the copper column 31 may cover the insulating layer 50, and the insulating layer 50 partially covers the outer side of the tin bump 32.

[0126] In one possible implementation, Figure 3 As shown, the second end of the insulating layer 50 may also have a gap b with the end of the copper pillar 31 close to the adapter board 20. For example, the insulating layer 50 may also cover a portion of the copper pillar 31 along the axial direction. The embodiment of the present application does not limit the coverage area of ​​the insulating layer 50 on the copper pillar 31, as long as it can ensure that the high thermal conductivity medium 40 and the copper pillar 31 are effectively isolated.

[0127] like Figure 1a and Figure 4As shown, when the high thermal conductivity medium 40 is provided, the end of the high thermal conductivity medium 40 close to the adapter plate 20 can extend to be flush with the second end of the insulating layer 50 (i.e., the end of the insulating layer facing the adapter plate 20). For example, the distance c between the end of the high thermal conductivity medium 40 close to the adapter plate 20 and the adapter plate 20 is equal to the distance a between the second end of the insulating layer 50 and the adapter plate 20. In this way, while increasing the filling amount of the high thermal conductivity medium 40, it is prevented that the high thermal conductivity medium 40 extends out of the second end of the insulating layer 50 and directly contacts the surface of the electrical connector 30. This not only increases the heat dissipation efficiency of the high thermal conductivity medium 40 for the first chip 10 and the electrical connector 30, but also ensures that the electrical connector 30 will not leak electricity or short-circuit between adjacent electrical connectors 30 due to the high thermal conductivity medium 40. It should be noted that, referring to Figure 1a As shown, a refers to the distance between the second end of the insulating layer 50 and the adapter plate 20 , and c refers to the distance between the end of the high thermal conductive medium 40 close to the adapter plate 20 and the adapter plate 20 .

[0128] Still taking the example of the electrical connector 30 including the copper pillar 31 and the tin bump 32 connected to one end of the copper pillar 31, when the second end of the insulating layer 50 extends to the end of the copper pillar 31 close to the adapter board 20, one end of the high thermal conductivity medium 40 can be extended to be flush with the second end of the insulating layer 50 to increase the filling area and filling amount of the high thermal conductivity medium 40, so that more heat on the first chip 10 and the electrical connector 30 can be transferred to the high thermal conductivity medium 40 and dissipated to the outside with the high thermal conductivity medium 40, and will not cause leakage and short circuit of the electrical connector 30. In addition, the support strength of the high thermal conductivity medium 40 to the copper pillar 31 and the first chip 10 is also enhanced.

[0129] In some examples, the end of the high thermal conductivity medium 40 close to the adapter plate 20 may be higher than the second end of the insulating layer 50, for example, Figure 2 As shown, the distance between the end of the high thermal conductivity medium 40 close to the adapter board 20 and the adapter board 20 is greater than the distance between the second end of the insulating layer 50 and the adapter board 20, so as to further ensure that the high thermal conductivity medium 40 does not directly contact the surface of the electrical connector 30. For example, when the second end of the insulating layer 50 extends to the end of the copper pillar 31 close to the adapter board 20, one end of the high thermal conductivity medium 40 can extend to a certain distance from the end of the copper pillar 31 close to the adapter board 20, so as to ensure that the insulating layer 50 effectively isolates the high thermal conductivity medium 40 from the copper pillar 31.

[0130] It should be understood that the distance between the end of the high thermal conductivity medium 40 close to the adapter plate 20 and the second end of the insulating layer 50 can be adjusted according to actual heat dissipation requirements.

[0131] The insulating layer 50 in the embodiment of the present application may be a copper oxide layer or a tin oxide layer. In some examples, the insulating layer 50 may also be a dry film or a passivation layer made of an insulating material, wherein the insulating material may be a polymer such as polyvinyl chloride, styrene-butadiene rubber, polyamide, etc., and the composition of the insulating material is not limited in this embodiment.

[0132] When the insulating layer 50 is a copper oxide layer, the formation process of the insulating layer 50 may be: oxidizing the copper pillar 31 at high temperature or in a humidified manner to form a copper oxide layer on the surface of the copper pillar 31 , and the copper oxide layer serves as the insulating layer 50 .

[0133] The manufacturing process of the tin oxide layer as the insulating layer is to first immerse tin on the surface of the electrical connector 30, and then oxidize it into tin oxide, so as to form a tin oxide layer on the surface of the electrical connector 30, and serve as the insulating layer. The direct immersion of tin on the electrical connector 30 will inevitably cause the tin to react with the metal compound in the electrical connector 30, such as CuP on the surface of the copper column 31, to form CuSn, which will affect the mechanical structure of the electrical connector 30 and the electrical properties of the electrical connector 30. Therefore, referring to Figure 4 As shown, the present application sets a barrier layer 60 between the outer wall of the electrical connector 30 and the tin oxide layer (i.e., the insulating layer 50) to prevent tin from over-reacting with the metal in the electrical connector 30, such as copper, to generate intermetallic compounds that are detrimental to the mechanical structure and electrical properties of the electrical connector 30, thereby further ensuring the structural stability of the electrical connector 30 and the stable conduction between the first chip 10 and the adapter board 20. The barrier layer 60 can be a film layer made of Ni (nickel), Ti (titanium), W (tungsten), or TaN (tantalum nitride). The film layer made of Ni, Ti, W, and TaN can effectively block the metal compounds in the tin and the electrical connector 30, thereby ensuring the smooth growth of tin oxide.

[0134] The embodiment of the present application also provides a method for manufacturing a chip packaging structure, and the manufacturing method may specifically include the following steps.

[0135] Figure 5a A schematic diagram of the structure of a first chip in a first method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application; Figure 5b A schematic diagram of a structure in which an electrical connector is manufactured on the surface of a first chip in a first manufacturing method of a chip packaging structure provided in Embodiment 1 of the present application; Figure 5c A schematic diagram of a structure in which an insulating layer is formed on an outer side wall of an electrical connector in a first method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application; Figure 5d A schematic diagram of the structure after the adapter plate is electrically connected to an end of the electrical connector facing away from the first chip in the first manufacturing method of the chip packaging structure provided in the first embodiment of the present application; Figure 5eThis is a schematic diagram of a structure in which a high thermal conductivity medium is filled on the periphery of an electrical connector in a first method for manufacturing a chip packaging structure provided in the first embodiment of the present application. Referring to the first method for manufacturing a chip packaging structure provided in the embodiment of the present application, the details are as follows:

[0136] S101 . Provide a first chip 10 .

[0137] Reference Figure 5a As shown, a first chip 10 is provided, wherein the first chip 10 can directly adopt an existing chip structure, or a silicon wafer for making the chip 10 can be first obtained, and then the silicon wafer is cut by a cutting device to form the required first chip 10. Alternatively, the first chip 10 can be a wafer, and the wafer can be cut to form the required chip when the packaging is completed.

[0138] S102 , preparing at least one electrical connection member 30 on one surface of the first chip 10 , and the electrical connection member 30 is electrically connected to the first chip 10 .

[0139] Reference Figure 5b As shown, the first chip 10 is placed on the preparation platform, and then the electrical connector 30 is deposited on the upper surface of the first chip 10 until the electrical connector 30 reaches the required height. Figure 5b The electrical connector 30 is deposited in the direction of the middle arrow d, so that the deposition process of the electrical connector 30 is more stable and controllable.

[0140] One or more electrical connectors 30 may be deposited on the upper surface of the first chip 10 . When there are multiple electrical connectors 30 , the multiple electrical connectors 30 are spaced apart in a direction parallel to the first chip 10 .

[0141] When the electrical connector 30 includes a copper pillar 31 and a tin bump 32 disposed at one end of the copper pillar 31, S102 may include:

[0142] First, at least one copper pillar 31 is deposited on the upper surface of the first chip 10 along the direction of arrow a. When the copper pillar 31 reaches a certain height, tin is sputtered on the top of the copper pillar 31 to form a tin bump 32. It can be understood that the tin bump 32 is electrically connected to the top of the copper pillar 31.

[0143] S103 , forming an insulating layer 50 on the outer wall of the electrical connector 30 , wherein the insulating layer 50 at least covers a portion of the outer wall of the electrical connector 30 .

[0144] Reference Figure 5c As shown, an insulating layer 50 is formed on the outer wall of the electrical connector 30 . The insulating layer 50 can be formed on the outer wall of the electrical connector 30 by oxidation, sputtering or printing.

[0145] For example, forming the insulating layer 50 on the outer wall of the electrical connector 30 may include:

[0146] The outer side wall of the electrical connector 30 is oxidized by high temperature or moisture to form an oxide layer on the outer side wall of the electrical connector 30, and the oxide layer is used as the insulating layer 50. For example, when the electrical connector 30 includes a copper pillar 31 and a tin bump 32 disposed at one end of the copper pillar 31, the CuP on the surface of the copper pillar 31 is oxidized to form a copper oxide layer, and the copper oxide layer is used as the insulating layer 50. It can be seen that the insulating layer 50 can cover all or part of the side wall of the copper pillar 31.

[0147] In some examples, the process of forming the insulating layer 50 on the outer wall of the electrical connector 30 may also include: pasting an insulating dry film or an insulating passivation layer on the outer wall of the electrical connector 30, and using the insulating dry film or the insulating passivation layer as the insulating layer. The insulating dry film or the insulating passivation layer may be made of a polymer material such as polyvinyl chloride, styrene-butadiene rubber, and polyamide.

[0148] In a possible implementation, the process of forming the insulating layer 50 on the outer side wall of the electrical connector 30 may specifically include:

[0149] a1), immersing the outer wall of the electrical connector 30 in tin to form a tin layer on the outer wall of the electrical connector 30;

[0150] b1) Oxidizing the tin layer to form a tin oxide layer, and using the tin oxide layer as the insulating layer 50 .

[0151] Continuing with the example of the electrical connector 30 including the copper pillar 31 and the tin bump 32 disposed at one end of the copper pillar 31 , firstly, the surface of the copper pillar 31 is dipped in tin and then oxidized into SnOx, i.e., tin oxide, which serves as the insulating layer 50 .

[0152] In order to prevent the tin from reacting with the metal on the surface of the electrical connector 30, such as copper, to generate intermetallic compounds which may adversely affect the mechanical structure and electrical properties of the electrical connector 30 when the surface of the electrical connector 30 is dipped in tin, the process of forming the insulating layer 50 on the outer wall of the electrical connector 30 may further specifically include:

[0153] a2) forming a barrier layer 60 on the outer wall of the electrical connector 30 by electroplating or sputtering (see Figure 4 shown);

[0154] b2), immersing the barrier layer 60 on the outer side wall of the electrical connector 30 with tin to form a tin layer on the outer side wall of the barrier layer 60;

[0155] c) Oxidizing the tin layer to form a tin oxide layer, and using the tin oxide layer as the insulating layer 50 .

[0156] For example, a barrier layer 60 is firstly sputtered on the CuP surface of the copper pillar 31, and then the barrier layer 60 is immersed in tin, and finally the tin is oxidized into SnOx, i.e., tin oxide, and used as the insulating layer 50, thereby preventing CuSn from growing too fast and ensuring the structural stability and electrical performance of the electrical connector 30.

[0157] S104 , providing an adapter board 20 , and electrically connecting the adapter board 20 to an end of the electrical connector 30 facing away from the first chip 10 , so that the first chip 10 and the adapter board 20 are electrically connected through the electrical connector 30 .

[0158] Reference Figure 5d As shown, the adapter board 20 is connected to one end of the electrical connector 30, for example, the adapter board 20 can be connected to the tin bump 32 by welding. The adapter board 20 can be a substrate or a second chip. It should be understood that the substrate or the second chip can directly adopt the substrate or the second chip in the prior art.

[0159] It is understandable that when the electrical connector 30 includes a copper pillar 31 and a tin bump 32 disposed at one end of the copper pillar 31 , the transfer board 20 is electrically connected to an end of the tin bump 32 facing away from the first chip 10 .

[0160] S105 , filling a high thermal conductivity medium 40 between the first chip 10 and the adapter board 20 to form a chip packaging structure.

[0161] Reference Figure 5e As shown, the high thermal conductivity medium 40 can be coated or printed upward along the direction of arrow d starting from the upper surface of the first chip 10, that is, the surface facing the adapter board 20, until the high thermal conductivity medium 40 reaches the second end of the insulating layer 50, that is, one end close to the adapter board 20 or there is a gap between the top of the high thermal conductivity medium 40 and the second end of the insulating layer 50.

[0162] The high thermal conductivity medium 40 is arranged around the outer periphery of the electrical connector 30, and one end of the high thermal conductivity medium 40 contacts the first chip 10. The insulating layer 50 separates the high thermal conductivity medium 40 and the electrical connector 30 to prevent the electrical connector 30 from leaking or short-circuiting adjacent point connectors 30.

[0163] It should be understood that when the high thermal conductivity medium 40 is a nanomaterial formed by stacking nanowires or nanoparticles, after the high thermal conductivity medium 40 is surrounded by the outer periphery of the electrical connector 30, the oxidizing medium can continue to be filled in the gaps of the nanomaterial to enhance the bonding force between the nanowires or nanoparticles in the nanomaterial, thereby improving the structural strength of the high thermal conductivity medium 40 formed by the stacking of nanomaterials.

[0164] Figure 6aA schematic diagram of the structure of a first chip in a second method for manufacturing a chip packaging structure provided in Embodiment 1 of the present application; Figure 6b A schematic diagram of a structure in which an electrical connector is manufactured on the surface of a first chip in the second manufacturing method of the chip packaging structure provided in the first embodiment of the present application; Figure 6c A schematic diagram of a structure in which an insulating layer is formed on an outer side wall of an electrical connector in a second method for manufacturing a chip packaging structure provided in the first embodiment of the present application; Figure 6d A schematic diagram of a structure in which a high thermal conductivity medium is filled on the periphery of an electrical connector in a second method for manufacturing a chip packaging structure provided in the first embodiment of the present application;

[0165] Figure 6e This is a schematic structural diagram of the second manufacturing method of the chip packaging structure provided in the first embodiment of the present application after the adapter board is electrically connected to the end of the electrical connector facing away from the first chip.

[0166] Reference Figure 6a to Figure 6e As shown, the production process and sequence of S101 to S103 in the second preparation method provided in this embodiment are completely consistent with those of the first preparation method described above, and the specific production process of S101 to S103 can directly refer to the content of the first preparation method described above. Different from the first preparation method described above, S104 and S105 of the second preparation method provided in this embodiment are respectively:

[0167] S104, a high thermal conductivity medium 40 is disposed on the surface of the first chip 10 having the electrical connection member 30,

[0168] like Figure 6d As shown, the high thermal conductivity medium 40 is disposed around the outer periphery of the electrical connector 30 formed with the insulating layer 50 , and the insulating layer 50 separates the high thermal conductivity medium 40 from the electrical connector 30 .

[0169] S105 , providing an adapter plate 20 , wherein the adapter plate 20 is electrically connected to an end of the electrical connector 30 facing away from the first chip 10 , to form a chip packaging structure.

[0170] like Figure 6e As shown, it can be understood that the first preparation method and the second preparation method of the chip packaging structure are just different in that the order of the high thermal conductivity medium 40 and the fixing adapter plate 20 are swapped after the insulating layer 50 is manufactured.

[0171] It should be noted that in both the first and second preparation methods of the chip packaging structure, the electrical connector 30 and the high thermal conductivity medium 40 are directly manufactured on the first chip 10 .

[0172] In some other examples of the preparation method, a silicon wafer can be directly provided, and the electrical connector 30, the insulating layer 50 and the high thermal conductivity medium 40 can be manufactured on the silicon wafer. After the high thermal conductivity medium 40 is filled to the periphery of the electrical connector 30, the silicon wafer is cut into the first chip 10. The high thermal conductivity medium 40 can be before or after the adapter plate 20 is fixed. In other words, the silicon wafer can be cut before the adapter plate 20 is fixed to one end of the electrical connector 30 and after the high thermal conductivity medium 40 is filled to the periphery of the electrical connector 30. The silicon wafer can also be cut at the end of all the manufacturing steps.

[0173] Of course, in some other examples of the preparation method, a silicon wafer can be directly provided, and then after the electrical connector 30 and the insulating layer 50 are manufactured, the silicon wafer is cut before the high thermal conductivity medium 40 is filled, and then the high thermal conductivity medium 40 is filled in the gap between the first chip 10 and the electrical connector 30 formed by cutting. It can be understood that the cutting of the silicon wafer can be performed after the adapter plate 20 is fixed to one end of the electrical connector 30 and before the high thermal conductivity medium 40 is filled to the periphery of the electrical connector 30, or when the high thermal conductivity medium 40 and the adapter plate 20 are not set, the silicon wafer is cut first, so that the subsequent filling of the high thermal conductivity medium 40 and the fixing of the adapter plate 20 are both performed on the first chip 10.

[0174] Scene 2

[0175] Figure 7 A sixth structural schematic diagram of a chip packaging structure provided in an embodiment of the present application.

[0176] Reference Figure 7 As shown, based on scenario 1, the chip packaging structure of the present application further includes an underfill 70, the thermal conductivity of which is less than that of the high thermal conductivity medium 40. The thermal conductivity of the underfill 70 is generally lower than 3W / mK or even 1W / mK.

[0177] The bottom filler 70 of the present application is filled between the insulating layer 50 and the adapter board 20 and between the high thermal conductivity medium 40 and the adapter board 20, so that the bottom filler 70 can support the bottom of the insulating layer 50 and the high thermal conductivity medium 40, thereby reducing the stress between the adapter board 20 and the first chip 10 caused by the mismatch of thermal expansion coefficients, avoiding the breakage of the pad between the electrical connector 30 and the adapter board 20, and improving the welding reliability between the electrical connector 30 and the adapter board 20 and the structural stability of the insulating layer 50 and the high thermal conductivity medium 40. At the same time, because the thermal conductivity of the bottom filler 70 is small, it does not have conductive properties, so it will not cause leakage or short circuit of the electrical connector 30.

[0178] When the electrical connector 30 includes a copper pillar 31 and a tin bump 32 arranged at one end of the copper pillar 31, part of the bottom filler 70 extends to contact the outer side surface of the tin bump 32 to further improve the structural stability of the tin bump 32 in the packaged chip structure, thereby further ensuring the electrical connection reliability between the tin bump 32 and the adapter board 20.

[0179] The bottom filler 70 may directly adopt the filler of the existing chip packaging structure, for example, the bottom filler may be composed of epoxy resin and silicon dioxide.

[0180] In actual applications, due to the special material properties of the bottom filler 70, the bottom filler 70 has the ability to climb upward, so that the bottom filler 70 can climb to the outer surface of the high thermal conductivity medium 40, thereby strengthening the structural stability of the high thermal conductivity medium 40, so that the high thermal conductivity medium 40 has a tendency to converge toward the center of the packaging structure, thereby also ensuring the structural support of the high thermal conductivity medium 40 for the first chip 10 and the electrical connector 30, making the entire chip packaging structure more stable. In some examples, the bottom filler 70 can climb from the side of the adapter board 20 toward the first chip 10 to 2 / 3 of the high thermal conductivity medium 40 relative to the adapter board 20.

[0181] It is understandable that the filling of the bottom filler 70 needs to be performed after the transfer board 20 is electrically connected to the end of the electrical connector 30 away from the first chip 10 and the high thermal conductivity medium 40 is filled around the periphery of the electrical connector 30 .

[0182] Specifically, the manufacturing method of the fifth structure of the chip packaging structure can be directly carried out on the basis of the first manufacturing method or the second manufacturing method of the above-mentioned chip packaging structure, and specifically, the following steps are performed before forming the chip packaging structure: filling the bottom filler 70 in the gap between the insulating layer 50 and the adapter board 20 and in the gap between the high thermal conductivity medium 40 and the adapter board 20, wherein the bottom filler 70 is in contact with the outer side surface of the tin bump 32.

[0183] Scene 3

[0184] In practical applications, a mounting hole (not shown in the figure) is provided on the substrate or the second chip serving as the adapter board 20, and a ground connection point (also known as VSS, ground pin) or a power connection point (also known as VDD, ground pin) is provided in the mounting hole, wherein the ground connection point VSS extends out of the mounting hole away from the first chip 10, that is, extends out of the adapter board 20 and is used to connect to the ground wire to protect the power safety of the adapter board 20. The power connection point also extends out of the mounting hole away from the first chip 10, that is, extends out of the adapter board 20 and is used to connect to an external power supply to provide electrical signals for the chip packaging structure.

[0185] In order to achieve heat dissipation of the ground connection point or the power connection point, the embodiment of the present application can, on the basis of any of the above chip packaging structures, contact one end of the high thermal conductivity medium 40 facing the adapter board 20 with the ground connection point or the power connection point on the adapter board 20 to conduct the heat of the ground connection point or the power connection point to the high thermal conductivity medium 40, and then dissipate the heat to the outside through the thermal conductive medium 40, thereby ensuring the electrical performance of the ground connection point or the power connection point of the adapter board 20.

[0186] Figure 8 This is a seventh structural diagram of a chip packaging structure provided by an embodiment of the present application. Figure 8 As shown, as the seventh structure of the chip packaging structure, a metal pad 80 can be set at the end of the ground connection point or the power connection point facing the first chip 10, and the end of the high thermal conductivity medium 40 facing the adapter board 20 can be in contact with the metal pad 80, so that the heat of the ground connection point or the power connection point can be transferred to the high thermal conductivity medium 40 through the metal pad 80.

[0187] The metal pad 80 may be a copper pad or a tin pad or other metal pads with high thermal conductivity.

[0188] The manufacturing method of the sixth structure of the chip packaging structure of the present application is different from any of the manufacturing methods of the chip packaging structure mentioned above in that, before the adapter board 20 is electrically connected to the end of the electrical connector 30 away from the first chip 10, the manufacturing method of the sixth structure further includes:

[0189] A metal pad 80 is formed on the surface of the adapter board 20 facing the first chip 10, one end of the metal pad 80 is electrically connected to a ground connection point or a power connection point on the adapter board 20, and the other end of the metal pad 80 is in contact with the high thermal conductivity medium 40 when the adapter board 20 is connected to the electrical connector 30.

[0190] It should be understood that Figure 8 The seventh structure of the chip package structure shown is only a sixth structure of the chip package structure, that is, Figure 7 However, it cannot be ruled out that the seventh structure of the chip packaging structure of the embodiment of the present application can also be an improvement on the above other structures. For example, in the first structure of the chip packaging structure mentioned above, that is, Figure 1a On the basis of this, a metal pad 80 is set at one end of the ground connection point or the power connection point of the adapter board 20 facing the first chip 10, and the high thermal conductivity medium 40 is in contact with the metal pad 80 near one end of the adapter board 20, so that the heat on the ground connection point or the power connection point of the adapter board 20 is transferred to the high thermal conductivity medium 40 through the metal pad 80, thereby achieving effective heat dissipation of the ground connection point or the power connection point of the adapter board 20.

[0191] Reference Figure 8 As shown, in some examples, the metal pad 80 may extend to contact the end of the high thermal conductivity medium 40 close to the transfer board 20, without extending the end of the high thermal conductivity medium 40 close to the transfer board 20. Of course, in other examples, the portion of the end of the high thermal conductivity medium 40 close to the transfer board 20 may also be extended to form the extension portion 41 mentioned below, which is in contact with the metal pad 80.

[0192] Fig. 9 This is a schematic diagram of an eighth structure of a chip packaging structure provided by an embodiment of the present application. Fig. 9 As shown, in order to improve the heat dissipation efficiency of the high thermal conductivity medium 40 to the ground connection point or the power connection point on the adapter board 20, the eighth structure of the chip packaging structure is to extend a portion of the high thermal conductivity medium 40 close to one end of the adapter board 20 toward the direction close to the adapter board 20 to form an extension portion 41, one end of the extension portion 41 extends to the ground connection point or the power connection point, and directly contacts the ground connection point or the power connection point to reduce the heat conduction resistance between the high thermal conductivity medium 40 and the ground connection point or the power connection point in the adapter board 20, so that the heat at the ground connection point or the power connection point can be quickly and effectively transferred to the high thermal conductivity medium 40, and transferred to the external environment along with the high thermal conductivity medium 40, further ensuring the working performance of the adapter board 20.

[0193] It should be noted that the extension portion 41 of the high thermal conductivity medium 40 close to the adapter plate 20 or the metal pad 80 cannot contact the outer surface of the electrical connector 30 to prevent leakage and short circuit.

[0194] For example, Figure 8 and Fig. 9 As shown, when the second end of the insulating layer 50 extends to be flush with the end of the copper pillar 31 close to the adapter board 20, and the bottom filler 70 is filled between the second end of the insulating layer 50 and the adapter board 20 and between the end of the high thermal conductivity medium 40 close to the adapter board 20 and the adapter board 20, the extension portion 41 at one end of the high thermal conductivity medium 40 or the metal pad 80 will not directly contact the tin bump 32 and the outer wall of any copper pillar 31.

[0195] When Figure 1a On the basis of the first structure shown, when one end of the high thermal conductivity medium 40 close to the adapter board 20 contacts the ground connection point or the power connection point on the adapter board 20 through the metal pad 80 or the extension portion 41, it is also necessary to ensure that the outer wall of the metal pad 80 or the extension portion 41 does not contact the tin bump 32.

[0196] The embodiment of the present application does not elaborate on the situation of setting the outer side wall of the metal pad 80 or the extension part 41 based on the chip packaging structure of other structures. It is sufficient to ensure that the outer side wall of the metal pad 80 or the extension part 41 does not directly contact the outer side wall of the electrical connector 30.

[0197] An embodiment of the present application also provides a circuit board, which includes a chip packaging structure in any of the above scenarios.

[0198] An embodiment of the present application also provides an electronic device, which includes any one of the chip packaging structures in any of the above scenarios.

[0199] By setting the above chip packaging structure in the electronic device, due to the good heat dissipation effect of the chip packaging structure, a highly integrated chip packaging structure can be set in the electronic device, so that while enhancing the function of the electronic device, the size occupied by the chip packaging structure in the electronic device is reduced, which not only provides effective space for the installation of other components in the electronic device, but also reduces the size of the entire electronic device and optimizes the experience effect of the electronic device. At the same time, it also ensures the stability of signal transmission in the electronic device and ensures the normal operation of the electronic device.

[0200] It should be noted that the electronic devices provided in the embodiments of the present application may include but are not limited to mobile phones, tablet computers, laptop computers, ultra-mobile personal computers (UMPCs), handheld computers, walkie-talkies, netbooks, POS machines, personal digital assistants (PDAs), wearable devices, virtual reality devices, and other mobile or fixed terminals with chip packaging structures.

[0201] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0202] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

Claims

1. A chip packaging structure, It is characterized in that include: A first chip, an adapter board, and at least one electrical connector located between the first chip and the adapter board, wherein two ends of the electrical connector are electrically connected to the first chip and the adapter board respectively; the electrical connector comprises: a copper column and a tin bump connected to the copper column, wherein one end of the copper column is electrically connected to the first chip, and the tin bump is arranged between the copper column and the adapter board and is electrically connected to the adapter board; It also includes: a high thermal conductivity medium located between the first chip and the adapter board and surrounding the outer periphery of the electrical connector, one end of the high thermal conductivity medium is in contact with the first chip, an insulating layer is provided between the high thermal conductivity medium and the electrical connector, and the insulating layer is used to separate the high thermal conductivity medium from the electrical connector; The first end of the insulating layer extends to an end of the electrical connector close to the first chip, and the second end of the insulating layer extends to a preset distance between the insulating layer and the adapter board; the distance between an end of the high thermal conductivity medium close to the adapter board and the adapter board is greater than or equal to the distance between the second end of the insulating layer and the adapter board.

2. The chip packaging structure according to claim 1, characterized in that: The insulating layer is wrapped around at least a portion of the side wall of the electrical connector, and the high thermal conductivity medium is wrapped around a surface of the insulating layer facing away from the electrical connector.

3. The chip packaging structure according to claim 1, characterized in that: There are a plurality of electrical connectors, the plurality of electrical connectors are arranged at intervals, and the intervals between adjacent electrical connectors are filled with the high thermal conductivity medium.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure further includes an underfill, wherein the thermal conductivity of the underfill is smaller than the thermal conductivity of the high thermal conductivity medium; The underfill is filled between the insulating layer and the adapter plate and between the high thermal conductivity medium and the adapter plate.

5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The electrical connector is any one of a micro-bump or a controllable collapse bump.

6. The chip packaging structure according to claim 4, characterized in that: The second end of the insulating layer extends to an end of the copper column close to the adapter board; A portion of the underfill material extends to contact the outer side surface of the tin bump.

7. The chip packaging structure according to any one of claims 1 to 3 and 6, characterized in that: The high thermal conductivity medium includes one or more of the following materials: solder, silver paste, and graphene.

8. The chip packaging structure according to any one of claims 1 to 3 and 6, characterized in that: The high thermal conductivity medium is formed by stacking nanowires or nanoparticles; The gaps between the nanowires or between the nanoparticles are filled with an oxidizing medium.

9. The chip packaging structure according to any one of claims 1 to 3 and 6, characterized in that: The insulating layer is a copper oxide layer; or, The insulating layer is a tin oxide layer; or, The insulating layer is a dry film or a passivation layer made of insulating material.

10. The chip packaging structure according to claim 9, characterized in that: The insulating layer is a tin oxide layer, and a barrier layer is arranged between the tin oxide layer and the outer side wall of the electrical connector.

11. The chip packaging structure according to claim 10, characterized in that: The barrier layer is a film layer made of Ni, Ti, W, or TaN.

12. The chip packaging structure according to any one of claims 1-3, 6, 10-11, characterized in that: The adapter plate is provided with a mounting hole, a ground connection point or a power connection point is provided in the mounting hole, and at least a portion of the second end of the high thermal conductivity medium is in contact with the ground connection point or the power connection point.

13. The chip packaging structure according to claim 12, characterized in that: A metal pad is provided on the adapter board, one end of the metal pad extends into the mounting hole and contacts the ground connection point or the power connection point, and the other end of the metal pad contacts the high thermal conductivity medium.

14. The chip packaging structure according to any one of claims 1-3, 6, 10-11, and 13, characterized in that: The adapter board is a second chip; or, the adapter board is a substrate.

15. An electronic device, characterized in that: Comprising the chip packaging structure as described in any one of claims 1-14.

16. A method for manufacturing a chip packaging structure, characterized in that: The method comprises: providing a first chip; Prepare at least one electrical connection member on one side of the first chip, and the electrical connection member is electrically connected to the first chip; forming an insulating layer on the outer side wall of the electrical connector, wherein the insulating layer at least covers a portion of the outer side wall of the electrical connector; A high thermal conductivity medium is arranged on a surface of the first chip having the electrical connector, the high thermal conductivity medium is arranged around the outer periphery of the electrical connector, and the insulating layer separates the high thermal conductivity medium from the electrical connector; A transfer board is provided, wherein the transfer board is electrically connected to an end of the electrical connector facing away from the first chip to form a chip packaging structure; there is a gap between an end of the insulating layer facing the transfer board and the transfer board, and a distance between an end of the high thermal conductivity medium facing the transfer board and the transfer board is greater than or equal to a distance from the insulating layer to the transfer board; Preparing at least one electrical connection on one side of the first chip, comprising: Prepare at least one copper pillar on one side of the first chip; A tin bump electrically connected to the copper column is formed at one end of the copper column facing the adapter plate; The adapter board is electrically connected to an end of the electrical connector facing away from the first chip, including: The adapter plate is electrically connected to an end of the tin bump facing away from the first chip.

17. A method for manufacturing a chip packaging structure, characterized in that: The method comprises: providing a first chip; Prepare at least one electrical connection member on one side of the first chip, and the electrical connection member is electrically connected to the first chip; forming an insulating layer on the outer side wall of the electrical connector, wherein the insulating layer at least covers a portion of the outer side wall of the electrical connector; Providing an adapter board, wherein the adapter board is electrically connected to an end of the electrical connector facing away from the first chip; A high thermal conductivity medium is filled between the first chip and the adapter board to form a chip packaging structure, wherein the high thermal conductivity medium is arranged around the periphery of the electrical connector, and one end of the high thermal conductivity medium is in contact with the first chip, and the insulating layer separates the high thermal conductivity medium from the electrical connector; there is a gap between one end of the insulating layer facing the adapter board and the adapter board, and the distance between one end of the high thermal conductivity medium facing the adapter board and the adapter board is greater than or equal to the distance from the insulating layer to the adapter board; Preparing at least one electrical connection on one side of the first chip, comprising: Prepare at least one copper pillar on one side of the first chip; A tin bump electrically connected to the copper column is formed at one end of the copper column facing the adapter plate; The adapter board is electrically connected to an end of the electrical connector facing away from the first chip, including: The adapter plate is electrically connected to an end of the tin bump facing away from the first chip.

18. The method according to claim 16 or 17, characterized in that: The step of forming an insulating layer on the outer side wall of the electrical connector comprises: The outer side wall of the electrical connector is oxidized to form an oxide layer on the outer side wall of the electrical connector, and the oxide layer serves as the insulating layer.

19. The method according to claim 16 or 17, characterized in that: The step of forming an insulating layer on the outer side wall of the electrical connector comprises: Dipping the outer side wall of the electrical connector into tin to form a tin layer on the outer side wall of the electrical connector; The tin layer is oxidized to form a tin oxide layer, and the tin oxide layer serves as the insulating layer.

20. The manufacturing method according to claim 19, characterized in that: Before tinning the outer side wall of the electrical connector, the method further comprises: forming a barrier layer on the outer side wall of the electrical connector by electroplating or sputtering; The step of tinning the outer side wall of the electrical connector to form a tin layer on the outer side wall of the electrical connector comprises: The barrier layer on the outer side wall of the electrical connector is tinned to form the tin layer on the barrier layer.

21. The method according to claim 16 or 17, characterized in that: The step of forming an insulating layer on the outer side wall of the electrical connector comprises: An insulating dry film or an insulating passivation layer is pasted on the outer side wall of the electrical connector, and the insulating dry film or the insulating passivation layer serves as the insulating layer.

22. The production method according to any one of claims 16 to 17 and 20, characterized in that: The high thermal conductivity medium is a nano material; After the high thermal conductivity medium is arranged around the outer periphery of the electrical connector, the invention further comprises: The gaps between the nanomaterials are filled with an oxidizing medium.

23. The method according to claim 16 or 17, characterized in that: Before forming the chip packaging structure, the method further includes: The gap between the insulating layer and the adapter plate and the gap between the high thermal conductivity medium and the adapter plate are filled with an underfill material, and the underfill material contacts the outer side surface of the tin bump.

24. The method according to any one of claims 16 to 17 and 20, characterized in that: Before the adapter board is electrically connected to the end of the electrical connector facing away from the first chip, the method further includes: A metal pad is formed on a surface of the adapter board facing the first chip, one end of the metal pad is electrically connected to a ground connection point or a power connection point on the adapter board, and the other end of the metal pad is used to contact the high thermal conductivity medium when the adapter board is connected to the electrical connector.

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