Electronic device and method for manufacturing the same

Abstract

The present invention provides an electronic device including a semiconductor memory and a method for manufacturing the electronic device. An electronic device includes a semiconductor memory, the semiconductor memory including: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, wherein the first electrode layer includes a first carbon material doped with a first element, and wherein the first oxide layer includes a first oxide of the first element.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0046531, filed on April 9, 2021, which is incorporated herein by reference in its entirety. Technical field

[0003] This patent document relates to a memory circuit or a memory device and their applications in an electronic device or an electronic system. Background art

[0004] Recently, as electrical appliances tend to be miniaturized, low - power, high - performance, multi - functional, etc., there has been an urgent need in the art for semiconductor devices capable of storing information in various electrical appliances such as computers, portable communication devices, etc., and research has been conducted on such semiconductor devices. Such semiconductor devices can store data by utilizing the characteristic of switching between different resistance states according to the applied voltage or current. For example, RRAM (Resistive Random Access Memory), PRAM (Phase - Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), electric fuses, etc. Summary of the invention

[0005] The technologies disclosed in this patent document include various embodiments of an electronic device and a method of manufacturing the same, which can improve the operating characteristics of a semiconductor memory and substantially prevent process defects.

[0006] In one embodiment, an electronic device includes a semiconductor memory, the semiconductor memory including: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, wherein the first electrode layer includes a first carbon material doped with a first element, and wherein the first oxide layer includes a first oxide of the first element.

[0007] In another embodiment, a method of manufacturing an electronic device including a semiconductor memory includes: forming a first electrode layer and a first oxide layer over a substrate; and forming a variable resistance layer over the first oxide layer, wherein the step of forming the first electrode layer and the first oxide layer includes: forming an initial first electrode layer including a first carbon material doped with a first element; and forming the first oxide layer including the first oxide of the first element by treating a part of the initial first electrode layer with an oxygen-containing plasma or gas. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A and Figure 1B is a view showing a semiconductor memory according to an embodiment of the present disclosure.

[0009] Figure 2 is a view showing a process of forming an intermediate electrode layer and a first oxide layer of a semiconductor memory according to an embodiment of the present disclosure.

[0010] Figure 3 is a view showing a process of forming a second oxide layer and an upper electrode layer of a semiconductor memory according to an embodiment of the present disclosure.

[0011] Figure 4 is a view showing a semiconductor memory according to another embodiment of the present disclosure.

[0012] Figure 5 is a view showing a semiconductor memory according to another embodiment of the present disclosure.

[0013] Figure 6 is a view showing a semiconductor memory according to another embodiment of the present disclosure.

[0014] Figure 7 is an example of a configuration diagram of a microprocessor implementing a memory circuitry based on the disclosed technology.

[0015] Figure 8 is an example of a configuration diagram of a processor implementing a memory circuitry based on the disclosed technology.

[0016] Figure 9 is an example of a configuration diagram of a system implementing a memory circuitry based on the disclosed technology.

[0017] Figure 10 is an example of a configuration diagram of a memory system implementing a memory circuitry based on the disclosed technology. DETAILED DESCRIPTION

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some of the structures in the accompanying drawings may be exaggerated to more clearly illustrate certain features of the described embodiments. When presenting specific examples in the accompanying drawings or descriptions of a multi-layer structure having two or more layers, the relative positional relationships of these layers shown or the arrangement order of these layers reflect the specific implementation manners of the described examples or the illustrated examples, and different relative positional relationships or different orders of arranging these layers are possible. In addition, the described examples or illustrated examples of the multi-layer structure may not reflect all the layers existing within a specific multi-layer structure (for example, one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in a described or illustrated multi-layer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0020] Figure 1A and Figure 1B is a view showing a semiconductor memory according to an embodiment of the present disclosure. Figure 1A is a plan view, and Figure 1B is a cross-sectional view taken along Figure 1A lines A-A' and B-B' of

[0021] Referring to Figure 1A and Figure 1B According to the present embodiment, the semiconductor memory may include: a substrate 100; a first line 110 formed on the substrate 100 and each first line extending in a first direction; a second line 120 formed on the first line 110 to be spaced apart from the first line 110, and each second line extending in a second direction intersecting the first direction; and a memory cell 130 disposed at the intersection of the first line 110 and the second line 120 between the first line 110 and the second line 120.

[0022] The substrate 100 may include a semiconductor material such as silicon. A lower structure (not shown) may be formed in the substrate 100. For example, the substrate 100 may include a driving circuit (not shown) electrically connected to the first line 110 and / or the second line 120 to control these lines.

[0023] Each of the first line 110 and the second line 120 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof, and may have a single-layer structure or a multi-layer structure. The first line 110 and the second line 120 may be respectively connected to the lower end portion and the upper end portion of the storage cell 130, and may transmit a voltage or a current to the storage cell 130 to drive the storage cell 130. When the first line 110 is used as a word line, the second line 120 may be used as a bit line. Conversely, when the first line 110 is used as a bit line, the second line 120 may be used as a word line.

[0024] The storage cell 130 may include a variable resistance element that stores different data by switching between different resistance states according to the voltage or current applied to the first line 110 and the second line 120. As an example, in a plan view, the storage cell 130 may have a rectangular shape, in which two sidewalls in a first direction are aligned with the second line 120, and two sidewalls in a second direction are aligned with the first line 110. However, embodiments of the present disclosure are not limited thereto, and various modifications may be made to the planar shape of the storage cell 130 as long as the storage cell 130 overlaps the intersection of the first line 110 and the second line 120.

[0025] As an example, the storage cell 130 may include a stacked structure of a lower electrode layer 131, a select element layer 132, an intermediate electrode layer 133, a variable resistance layer 135, and an upper electrode layer 137. In addition, as an example, the storage cell 130 may include a first oxide layer 134 between the variable resistance layer 135 and the intermediate electrode layer 133 and a second oxide layer 136 between the variable resistance layer 135 and the upper electrode layer 137.

[0026] The lower electrode layer 131 may be between the first line 110 and the select element layer 132, and may serve to electrically connect and physically separate the first line 110 and the select element layer 132. The lower electrode layer 131 may include various conductive materials, such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. Alternatively, the lower electrode layer 131 may include a carbon layer with or without a dopant.

[0027] The select element layer 132 can serve to substantially prevent current leakage that may occur between the memory cells 130 sharing the first line 110 or the second line 120. To this end, the select element layer 132 can have threshold switching characteristics, that is, it can substantially block or limit current when the magnitude of the applied voltage is less than a predetermined threshold, and allow a sudden increase in current when the magnitude of the applied voltage is greater than the threshold. The select element layer 132 can be implemented in an on state or an off state based on the threshold. The select element layer 132 can include a diode, an OTS (bidirectional threshold switch) material (such as a chalcogenide material), an MIEC (mixed ionic electronic conductor) material (such as a metal-containing chalcogenide material), an MIT (metal insulator transition) material (such as NbO2, VO2), etc., or a tunnel insulating material having a relatively wide bandgap (such as SiO2, Al2O3), etc.

[0028] The intermediate electrode layer 133 can be interposed between the select element layer 132 and the variable resistance layer 135, and can serve to electrically connect and physically separate the select element layer 132 and the variable resistance layer 135. In one embodiment, the intermediate electrode layer 133 can include a carbon material doped with a first element. Here, the carbon material doped with the first element can include a carbon element and the first element, but can be a material in which the main element is carbon and the additional element is the first element. As an example, the content of the first element in the intermediate electrode layer 133 can be in the range from 1 at% to 10 at%. The first element can be an element that can be oxidized and / or is easily oxidized, and the oxide of the first element can have a higher specific resistance than the carbon material doped with the first element. This can be used to form the first oxide layer 134 described later. As an example, the first element can include metal elements such as aluminum (Al), titanium (Ti), vanadium (V), tungsten (W), molybdenum (Mo), tantalum (Ta), and hafnium (Hf), or semiconductor elements such as silicon (Si) and boron (B). In addition, the carbon material doped with the first element can be amorphous.

[0029] The first oxide layer 134 can be interposed between the intermediate electrode layer 133 and the variable resistance layer 135. The first oxide layer 134 can include an oxide of the first element. For example, when the first element includes aluminum (Al), the first oxide layer 134 can include aluminum oxide (Al2O3). As will be described later, the first oxide layer 134 can be formed by an initial electrode layer (e.g., Figure 2formed by oxidation of the initial intermediate electrode layer 233), and thus, can be formed to directly contact the upper surface of the intermediate electrode layer 133 above the intermediate electrode layer 133. The first oxide layer 134 may have a resistance greater than that of the intermediate electrode layer 133, and thus, the first oxide layer 134 may have a function of reducing / suppressing heat dissipation generated from the variable resistance layer 135. For example, when a reset current is applied to the memory cell 130 including the variable resistance layer 135 to reset the memory cell 130 to the amorphous phase, the first oxide layer 134 having a relatively high resistance can effectively block heat transfer from the variable resistance layer 135, and thus, the amount of the reset current flowing through the memory cell 130 can be reduced compared to the amount of the reset current used in a conventional memory cell. The first oxide layer 134 may be a conductive material having a resistance greater than that of the intermediate electrode layer 133, or may be an insulating material. When the first oxide layer 134 is an insulating material, the first oxide layer 134 may have such a thin thickness that current can flow through the thickness at the operating voltage of the memory cell 130. For example, the first oxide layer 134 may have a thickness of several to several tens . The thickness T2 of the first oxide layer 134 may be less than the thickness T1 of the intermediate electrode layer 133. When the carbon material doped with the first element is amorphous, the first oxide layer 134 having a uniform thickness can be formed. That is, the thickness T2 of the first oxide layer 134 may have a substantially fixed (or constant) value. For example, the difference between the maximum value and the minimum value of the thickness T2 of the first oxide layer 134 is equal to or less than 5%, 3%, 1%, 0.5%, 0.3%, or 0.1% of the average value of the thickness T2.

[0030] The variable resistance layer 135 may be a part of the memory cell 130 that stores data. To this end, the variable resistance layer 135 may have variable resistance characteristics of switching between different resistance states according to the applied voltage or current. The variable resistance layer 135 may have a single-layer structure or a multi-layer structure, including at least one of materials for RRAM, PRAM, MRAM, FRAM, etc., that is, metal oxides such as perovskite-based oxides and transition metal oxides; phase change materials such as chalcogenide-based materials, ferromagnetic materials, ferroelectric materials, etc. Specifically, as an example, the variable resistance layer 135 may include a phase change material that switches between an amorphous state and a crystalline state by Joule heat generated according to the flowing current. When the phase change material is in the amorphous state, the phase change material may be in a relatively high resistance state, while when the phase change material is in the crystalline state, the phase change material may be in a relatively low resistance state. The resistance difference of the phase change material can be used to store data.

[0031] The upper electrode layer 137 may be interposed between the variable resistance layer 135 and the second line 120, and may serve to electrically connect and physically separate the variable resistance layer 135 and the second line 120. The upper electrode layer 137 may include a carbon material doped with a second element. The second element may be an element that can be oxidized and / or is easily oxidized, and the oxide of the second element may have a higher specific resistance than the carbon material doped with the second element. The content of the second element in the upper electrode layer 137 may be in the range from 1 at% to 10 at%. As an example, the second element may include metal elements such as aluminum (Al), titanium (Ti), vanadium (V), tungsten (W), molybdenum (Mo), tantalum (Ta), and hafnium (Hf), or semiconductor elements such as silicon (Si) and boron (B). The second element may be the same as or different from the first element of the intermediate electrode layer 133 described above. In addition, the carbon material doped with the second element may be amorphous.

[0032] However, instead of the carbon material doped with the second element, other conductive materials such as metals such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), metal nitrides such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof may be used as the upper electrode layer 137. This is because, as will be described later with reference to Figure 3 what is described, the second oxide layer 136 may not be formed by the oxidation of the upper electrode layer 137. Even in such a case, the conductive material used to form the upper electrode layer 137 may be a material having a sufficiently low specific resistance such that the resistance of the upper electrode layer 137 is lower than the resistance of the second oxide layer 136.

[0033] The second oxide layer 136 may be interposed between the variable resistance layer 135 and the upper electrode layer 137. The second oxide layer 136 may include an oxide of the second element. When the second element is the same as the first element, the second oxide layer 136 may be the same oxide as the first oxide layer 134. As will be described later, the second oxide layer 136 may be formed by the oxidation of an initial carbon layer (e.g., Figure 3 the initial carbon layer 330 in), which includes a carbon material doped with the second element. The second oxide layer 136 may be formed to directly contact the lower surface of the upper electrode layer 137 below the upper electrode layer 137, and may have a larger resistance than the upper electrode layer 137. Therefore, the second oxide layer 136 may have a function of reducing / inhibiting the heat dissipation generated from the variable resistance layer 135. The second oxide layer 136 may be a conductive material having a larger resistance than the upper electrode layer 137, or may be an insulating material. When the second oxide layer 136 is an insulating material, the second oxide layer 136 may have such a thin thickness that current can flow through this thickness at the operating voltage of the memory cell 130. For example, the second oxide layer 136 may have a few Up to several tens The thickness of the second oxide layer 136. The thickness T3 of the second oxide layer 136 may be less than the thickness T4 of the upper electrode layer 137. When the initial carbon layer (see Figure 3 330 in) is amorphous, a second oxide layer 136 having a uniform thickness can be formed. That is, the thickness T3 of the second oxide layer 136 can have a substantially fixed value.

[0034] In the above-described memory cell 130, the first oxide layer 134 and the second oxide layer 136 can be disposed under and above the variable resistance layer 135 to be adjacent to the variable resistance layer 135, and thus, it can reduce / suppress heat generated from the variable resistance layer 135 from radiating to the outside, for example, radiating to an adjacent memory cell 130. If the first oxide layer 134 and the second oxide layer 136 do not exist, the heat generated from the variable resistance layer 135 can be transferred to an adjacent memory cell 130, and thus, problems such as an increase in the operating voltage of the memory cell 130 may occur, specifically, an increase in voltage during a reset operation in which the variable resistance layer 135 changes from a low resistance state to a high resistance state, a problem of changing the characteristics of an adjacent memory cell 130, etc. However, according to an embodiment of the present disclosure, these problems can be solved. In addition, when heat is generated by Joule heating of the variable resistance layer 135 during a reset operation, the first oxide layer 134 and the second oxide layer 136 can have a relatively high thermal resistance, thereby reducing a part of the heat transferred from the variable resistance layer 135 to the electrode layers 133 and 137, respectively. Therefore, another part of the heat used to change the variable resistance layer 135 from a low resistance state to a high resistance state can be increased. As a result, compared with the reset current amount in a conventional memory cell, the reset current amount for Joule heating of the variable resistance layer 135 in the memory cell 130 according to an embodiment of the present disclosure can be reduced. In addition, by making the first oxide layer 134 and the second oxide layer 136 each have a uniform thickness, the operating voltage of the memory cell 130 can be uniform.

[0035] The first oxide layer 134 and the second oxide layer 136 can directly contact the variable resistance layer 135. However, the embodiments of the present disclosure are not limited thereto, and at least one of the first oxide layer 134 and the second oxide layer 136 may not directly contact the variable resistance layer 135. That is, another layer (not shown) may be interposed between at least one of the first oxide layer 134 and the second oxide layer 136 and the variable resistance layer 135. These examples will be shown in Figure 3 and Figure 4 and will be described in more detail in the corresponding part.

[0036] The first oxide layer 134 and the second oxide layer 136 may be symmetric with respect to each other by means of the variable resistance layer 135 therebetween. That is, the first oxide layer 134 and the second oxide layer 136 may be formed of the same material, and the thickness T2 of the first oxide layer 134 and the thickness T3 of the second oxide layer 136 may be substantially the same as each other. However, embodiments of the present disclosure are not limited thereto, and the first oxide layer 134 and the second oxide layer 136 may be formed of different materials, and / or the thickness T2 of the first oxide layer 134 and the thickness T3 of the second oxide layer 136 may be different from each other. In addition, the intermediate electrode layer 133 and the upper electrode layer 137 may also be symmetric with respect to each other by means of the variable resistance layer 135 therebetween. That is, the intermediate electrode layer 133 and the upper electrode layer 137 may be formed of the same material, and the thickness T1 of the intermediate electrode layer 133 and the thickness T4 of the upper electrode layer 137 may be substantially equal to each other. However, embodiments of the present disclosure are not limited thereto, the intermediate electrode layer 133 and the upper electrode layer 137 may be formed of different materials, and / or the thickness T1 of the intermediate electrode layer 133 and the thickness T4 of the upper electrode layer 137 may be different from each other.

[0037] In addition, based on the assumption that the variable resistance layer 135 which is crucial for data storage and at least one of the first oxide layer 134 and the second oxide layer 136 which are crucial for suppressing heat dissipation are included in the memory cell 130, the layered structure of the memory cell 130 described above may be variously modified.

[0038] As an example, either the first oxide layer 134 or the second oxide layer 136 may be omitted. When the first oxide layer 134 is omitted, the intermediate electrode layer 133 may include a carbon material doped with a first element, or may include other conductive materials. Alternatively, when the second oxide layer 136 is omitted, the upper electrode layer 137 may include a carbon material doped with a second element, or may include other conductive materials.

[0039] Alternatively, as an example, at least one of the intermediate electrode layer 133 and the upper electrode layer 137 may be omitted.

[0040] Alternatively, as an example, at least one of the select element layer 132 and the lower electrode layer 131 may be omitted.

[0041] Alternatively, as an example, in addition to the above layers 131 to 137, the memory cell 130 may further include one or more layers for improving the characteristics of the memory cell 130. This example will be shown in Figure 4 and will be described in more detail in the corresponding section.

[0042] Alternatively, as an example, the positions of the select element layer 132 and the variable resistance layer 135 may be reversed with respect to each other. In this case, the relative positions / structures of the lower electrode layer 131, the intermediate electrode layer 133, the first oxide layer 134 and the second oxide layer 136, and the upper electrode layer 137 may also be changed. This example will be shown in Figure 5 and will be described in more detail in the corresponding section.

[0043] The space between the first line 110, the second line 120, and the memory cell 130 may be filled with an insulating material (not shown).

[0044] According to the semiconductor memory described above, the operating characteristics of the memory cell 130, such as a reduction in the operating voltage, the uniformity of the operating voltage, etc., can be improved.

[0045] Next, referring again to Figure 1A and Figure 1B , an example of a method for manufacturing a semiconductor memory according to the present embodiment will be described.

[0046] First, a conductive layer for forming the first line 110 and a material layer for forming the memory cell 130 may be formed over the substrate 100. Here, the process of forming the intermediate electrode layer 133 and the first oxide layer 134 will be described in more detail with reference to Figure 2 and the process of forming the second oxide layer 136 and the upper electrode layer 137 will be described in more detail with reference to Figure 3

[0047] Figure 2 is a view showing a process of forming an intermediate electrode layer and a first oxide layer of a semiconductor memory according to an embodiment of the present disclosure.

[0048] Referring to Figure 2 , in step (a), an initial intermediate electrode layer 233 may be formed over a substrate on which a conductive layer for forming Figure 1B the first line 110 and a material layer for forming Figure 1B ​The material layers of the lower electrode layer 131 and the select element layer 132. The initial intermediate electrode layer 233 may include a carbon material doped with a first element and may be formed by a deposition method such as physical vapor deposition (PVD). Specifically, the initial intermediate electrode layer 233 may be formed by a sputtering method using a target containing carbon and the first element. In this case, the first element may be doped in the initial intermediate electrode layer 233 substantially uniformly. That is, the concentration of the first element in the direction of the thickness T5 of the initial intermediate electrode layer 233 may be substantially constant. For example, the difference between the maximum concentration and the minimum concentration of the first element in the direction of the thickness T5 of the initial intermediate electrode layer 233 may be equal to or less than 5%, 3%, 1%, 0.5%, 0.3%, or 0.1% of the average concentration. Additionally, the initial intermediate electrode layer 233 may be amorphous.

[0049] Subsequently, in step (b), the initial intermediate electrode layer 233 may be treated with an oxygen-containing plasma or gas. For example, the initial intermediate electrode layer 233 may be subjected to an O2 plasma treatment. In this case, a part of the initial intermediate electrode layer 233 may be oxidized to form an oxide layer 234. The oxide layer 234 may include an oxide of the first element doped in the initial intermediate electrode layer 233. Another part of the initial intermediate electrode layer 233 that remains unoxidized will hereinafter be referred to as the intermediate electrode layer 233'. Since the initial intermediate electrode layer 233 includes a uniformly doped first element and is in an amorphous state, the oxidation process can be performed uniformly, and thus an oxide layer 234 having a substantially uniform thickness T6 can be formed. The thickness T6 of the oxide layer 234 may be less than the thickness T5' of the intermediate electrode layer 233'.

[0050] The oxide layer 234 may correspond to the first oxide layer 134 described above Figure 1B and the intermediate electrode layer 233' may correspond to the intermediate electrode layer 133 described above Figure 1B of.

[0051] Figure 3 is a view showing a process of forming a second oxide layer and an upper electrode layer of a semiconductor memory according to an embodiment of the present disclosure.

[0052] Referring to Figure 3 , in step (a), an initial carbon layer 330 may be formed over a substrate on which a conductive layer for forming Figure 1B the first line 110 and for forming Figure 1BThe material layers of the lower electrode layer 131, the select element layer 132, the intermediate electrode layer 133, the first oxide layer 134, and the variable resistance layer 135. The initial carbon layer 330 may include a carbon material doped with a second element and may be formed by a deposition method such as PVD. In this case, the second element may be doped substantially uniformly in the initial carbon layer 330. That is, the concentration of the second element in the direction of the thickness T7 of the initial carbon layer 330 may be substantially constant. In addition, the initial carbon layer 330 may be amorphous.

[0053] Subsequently, in step (b), the initial carbon layer 330 may be treated with an oxygen-containing plasma or gas. For example, the initial carbon layer 330 may be subjected to an O2 plasma treatment. In this case, the oxide layer 336 may be formed by partially or completely oxidizing the initial carbon layer 330. The oxide layer 336 may include an oxide of the second element doped in the initial carbon layer 330. Since the initial carbon layer 330 includes a uniformly doped second element and is in an amorphous state, the oxidation process may be uniformly performed to form the oxide layer 336 having a substantially uniform thickness T8.

[0054] In Figure 3 the embodiment of, the case where a part of the initial carbon layer 330 is oxidized has been described. The other part of the initial carbon layer 330 that remains unoxidized will be referred to as the carbon layer 330' hereinafter. When Figure 1B the variable resistance layer 135 of is directly present under the initial carbon layer 330, the carbon layer 330' can prevent the oxidation of the variable resistance layer 135. In this case, the carbon layer 330' can function to prevent direct contact between the oxide layer 336 and the variable resistance layer 135. The thickness T7' of the carbon layer 330' may be less than the thickness T8 of the oxide layer 336, and further, may have a relatively thin thickness of several angstroms. However, the embodiments of the present disclosure are not limited thereto, and when precise process control can be carried out to a degree that can substantially prevent the oxidation of the variable resistance layer 135, or another layer is interposed between the variable resistance layer 135 and the oxide layer 336, the entire initial carbon layer 330 may be oxidized. In this case, the carbon layer 330' may not exist.

[0055] Subsequently, in step (c), the upper electrode layer 337 may be formed over the oxide layer 336. The upper electrode layer 337 may include a carbon material doped with a second element or other conductive materials.

[0056] The oxide layer 336 may correspond to the second oxide layer 136 described above Figure 1B and the upper electrode layer 337 may correspond to the upper electrode layer 137 described above Figure 1B .

[0057] Return to referenceFigure 1A and Figure 1B , a linear mask pattern extending in a first direction may be used to etch a conductive layer for forming a first line 110 and a material layer for forming a memory cell 130, and thus, a stacked structure including the first line 110 and a material layer pattern having a shape overlapping the first line 110 thereon may be formed. The space between each stacked structure including the first line 110 and the material layer pattern may be filled with an insulating material.

[0058] Subsequently, a conductive layer for forming a second line 120 may be formed on each stacked structure including the first line 110, the material layer pattern, and the insulating material between the first line 110 and the material layer pattern.

[0059] Subsequently, a linear mask pattern extending in a second direction may be used to etch the conductive layer and the material layer pattern for forming the second line 120, thereby forming the second line 120 and the memory cell 130.

[0060] Figure 4 is a view showing a semiconductor memory according to another embodiment of the present disclosure. For convenience, only a single memory cell and a part of the upper and lower lines thereon are illustrated, but as described above with reference to Figure 1A and Figure 1B , a plurality of memory cells may be arranged between the lower line and the upper line intersecting the lower line. The differences from the above-described embodiment will be mainly described.

[0061] Referring to Figure 4 , the memory cell 430 may be disposed between the first line 410 and the second line 420.

[0062] As an example, the memory cell 430 may include a stacked structure of a lower electrode layer 431, a select element layer 432, an intermediate electrode layer 433, a first oxide layer 434, a variable resistance layer 435, a second oxide layer 436, and an upper electrode layer 437. In addition, as an example, the memory cell 430 may include a first interface electrode layer 438-1 between the variable resistance layer 435 and the first oxide layer 434 and a second interface electrode layer 438-2 between the variable resistance layer 435 and the second oxide layer 436. In addition, as an example, the memory cell 430 may include a resistance layer 439 between the upper electrode layer 437 and the second line 420.

[0063] The first interface electrode layer 438-1 may be interposed between the variable resistance layer 435 and the first oxide layer 434, or when the first oxide layer 434 is omitted, the first interface electrode layer 438-1 may be interposed between the variable resistance layer 435 and the intermediate electrode layer 433, and may be used to increase adhesion and reduce the contact resistance therebetween. Specifically, the first interface electrode layer 438-1 may be used to reduce the set voltage applied during the set operation in which the variable resistance layer 435 changes from a high resistance state to a low resistance state. The first interface electrode layer 438-1 may include a conductive material having low resistance and good adhesion. For example, a metal such as tungsten (W), lithium (Li), aluminum (Al), tin (Sn), bismuth (Bi), antimony (Sb), nickel (Ni), copper (Cu), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), zinc (Zn), and molybdenum (Mo).

[0064] The second interface electrode layer 438-2 may be interposed between the variable resistance layer 435 and the second oxide layer 436, or when the second oxide layer 436 is omitted, the second interface electrode layer 438-2 may be interposed between the variable resistance layer 435 and the upper electrode layer 437, and may be used to increase adhesion while reducing the contact resistance therebetween. Specifically, the second interface electrode layer 438-2 may be used to reduce the set voltage applied during the set operation in which the variable resistance layer 435 changes from a high resistance state to a low resistance state. The second interface electrode layer 438-2 may include a conductive material having low resistance and good adhesion. For example, a metal such as tungsten (W), lithium (Li), aluminum (Al), tin (Sn), bismuth (Bi), antimony (Sb), nickel (Ni), copper (Cu), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), zinc (Zn), and molybdenum (Mo).

[0065] When a relatively large amount of current is supplied to drive the memory cell 430, an overshooting current or a spike current may flow through the memory cell 430, resulting in the failure of the operation of the memory cell 430. The resistance layer 439 may be a layer for preventing such an operation failure of the memory cell 430. The resistance layer 439 may include a conductive material having a resistance greater than that of the lower electrode layer 431, the intermediate electrode layer 433, and the upper electrode layer 437. For example, the resistance layer 439 may include tungsten silicon nitride (WSiN). However, embodiments of the present disclosure are not limited thereto, and the resistance layer 439 may include several to several tens A thin insulating material to allow current to flow between the upper electrode layer 437 and the second line 420 at the operating voltage of the storage cell 430.

[0066] Figure 5 FIG. is a view showing a semiconductor memory according to another embodiment of the present disclosure. Differences from the above embodiment will be mainly described.

[0067] Referring to Figure 5 , the storage cell 530 may be disposed between the first line 510 and the second line 520.

[0068] As an example, the storage cell 530 may include a stacked structure of a lower electrode layer 531, a first oxide layer 532, a variable resistance layer 533, a second oxide layer 534, an intermediate electrode layer 535, a select element layer 536, and an upper electrode layer 537.

[0069] In Figure 5 the embodiment of, different from the above embodiment, the variable resistance layer 533 may be located below the select element layer 536. For this purpose, the first oxide layer 532 may be formed between the lower electrode layer 531 and the variable resistance layer 533, and the second oxide layer 534 may be formed between the intermediate electrode layer 535 and the variable resistance layer 533.

[0070] The stacked structure of the lower electrode layer 531 and the first oxide layer 532 may substantially correspond to the Figure 1B intermediate electrode layer 133 and the first oxide layer 134 of the above. The stacked structure of the second oxide layer 534 and the intermediate electrode layer 535 may substantially correspond to the Figure 1B second oxide layer 136 and the upper electrode layer 137 of the above. Therefore, detailed descriptions thereof will be omitted.

[0071] Figure 6 FIG. is a view showing a semiconductor memory according to another embodiment of the present disclosure. Differences from the above embodiment will be mainly described.

[0072] Referring to Figure 6 , the storage cell 630 may be disposed between the first line 610 and the second line 620.

[0073] As an example, the memory cell 630 may include a stacked structure of a lower electrode layer 631, a first oxide layer 632, a variable resistance layer 633, a second oxide layer 634, an intermediate electrode layer 635, a selection element layer 636, and an upper electrode layer 637. Further, as an example, the memory cell 630 may include a first interface electrode layer 638-1 between the variable resistance layer 633 and the first oxide layer 632 and a second interface electrode layer 638-2 between the variable resistance layer 633 and the second oxide layer 634. Further, as an example, the memory cell 630 may include a resistance layer 639 between the upper electrode layer 637 and the second line 620.

[0074] The first interface electrode layer 638-1, the second interface electrode layer 638-2, and the resistance layer 639 may substantially correspond to Figure 4 the first interface electrode layer 438-1, the second interface electrode layer 438-2, and the resistance layer 439. Therefore, detailed descriptions thereof will be omitted.

[0075] The above and other memory circuits or semiconductor devices based on the disclosed technology can be used in a series of devices or systems. Figures 7 to 10 Some examples of devices or systems that can implement the memory circuit disclosed herein are provided.

[0076] Figure 7 is an example of a configuration diagram of a microprocessor that implements a memory circuit system based on the disclosed technology.

[0077] Referring to Figure 7 , the microprocessor 1000 may perform tasks for controlling and adjusting a series of processes of receiving data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a memory cell 1010, an arithmetic unit 1020, a control unit 1030, etc. The microprocessor 1000 may be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0078] The memory cell 1010 is a part of the microprocessor 1000 that stores data, such as processor registers, registers, etc. The memory cell 1010 may include various registers, such as data registers, address registers, floating-point registers, etc. The memory cell 1010 may perform functions of temporarily storing data to be operated on by the arithmetic unit 1020, the result data of the operation, and storing the address of the data used for the operation.

[0079] The memory cell 1010 may include one or more of the above semiconductor devices according to an embodiment. For example, the memory cell 1010 may include: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, wherein the first electrode layer includes a first carbon material doped with a first element, and wherein the first oxide layer includes a first oxide of the first element. Accordingly, in the memory cell 101, the memory cell characteristics and the manufacturing process can be improved. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0080] The arithmetic unit 1020 may perform four arithmetic operations or logical operations according to the result of decoding a command by the control unit 1030. The arithmetic unit 1020 may include at least one arithmetic logic unit (ALU) or the like.

[0081] The control unit 1030 may receive signals from the memory cell 1010, the arithmetic unit 1020, and external devices of the microprocessor 1000, perform extraction and decoding of commands, control input and output of signals of the microprocessor 1000, and perform processing represented by a program.

[0082] The microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040, which may temporarily store data to be input from external devices other than the memory cell 1010 or data to be output to external devices. In this case, the cache memory unit 1040 may exchange data with the memory cell 1010, the arithmetic unit 1020, and the control unit 1030 through a bus interface 1050.

[0083] Figure 8 is an example of a configuration diagram of a processor that implements a memory circuit system based on the disclosed technology.

[0084] Reference Figure 8 , the processor 1100 may improve performance and achieve versatility by including various functions in addition to the functions of the above microprocessor 1000. The processor 1100 may include a core unit 1110 serving as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transferring data between internal devices and external devices. The processor 1100 may include various system-on-chips (SoCs), such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0085] The core unit 1110 of this embodiment is a part that performs arithmetic and logical operations on data input from an external device, and may include a storage unit 1111, an arithmetic unit 1112, and a control unit 1113. The storage unit 1111, the arithmetic unit 1112, and the control unit 1113 may be substantially the same as the storage unit 1010, the arithmetic unit 1020, and the control unit 1030.

[0086] The cache memory unit 1120 is a part that temporarily stores data to compensate for the difference in data processing speeds between the core unit 1110 operating at high speed and the external device operating at low speed. The cache memory unit 1120 may include a first-level storage unit 1121 and a second-level storage unit 1122. In addition, in cases where a high storage capacity is required, the cache memory unit 1120 may include a third-level storage unit 1123. Depending on the occasion, the cache memory unit 1120 may include an increased number of storage units. That is, the number of storage units included in the cache memory unit 1120 may be changed according to the design. The speeds at which the first-level storage unit 1121, the second-level storage unit 1122, and the third-level storage unit 1123 store and distinguish data may be the same or different. In cases where the speeds of the respective storage units 1121, 1122, and 1123 are different, the speed of the first-level storage unit 1121 may be the highest. At least one of the first-level storage unit 1121, the second-level storage unit 1122, and the third-level storage unit 1123 of the cache memory unit 1120 may include one or more of the above semiconductor devices according to the embodiment. For example, the cache memory unit 1120 may include: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, where the first electrode layer includes a first carbon material doped with a first element, and where the first oxide layer includes a first oxide of the first element. Thereby, the storage unit characteristics and manufacturing process in the cache memory unit 1120 can be improved. As a result, the operating characteristics of the processor 1100 can be improved.

[0087] Although in this embodiment it is shown that all of the first-level storage unit 1121, the second-level storage unit 1122, and the third-level storage unit 1123 are configured inside the cache memory unit 1120, at least one of the first-level storage unit 1121, the second-level storage unit 1122, and the third-level storage unit 1123 of the cache memory unit 1120 may be configured outside the core unit 1110 and may compensate for the difference in data processing speeds between the core unit 1110 and the external device.

[0088] The bus interface 1130 is a part that connects the core unit 1110, the cache storage unit 1120, and external devices and allows for efficient data transfer.

[0089] The processor 1100 according to this embodiment may include multiple core units 1110, and the multiple core units 1110 may share the cache storage unit 1120. The multiple core units 1110 and the cache storage unit 1120 may be directly connected or connected through the bus interface 1130. The multiple core units 1110 may be configured in the same manner as the configuration of the core unit 1110 described above. The storage unit in each core unit 1110 may be configured to share with a storage unit outside the core unit 1110 through the bus interface 1130.

[0090] The processor 1100 according to this embodiment may further include an embedded storage unit 1140 for storing data, a communication module unit 1150 capable of sending data to and receiving data from external devices in a wired or wireless manner, a memory control unit 1160 for driving an external storage device, and a media processing unit 1170 for processing data processed in the processor 1100 or data input from an external input device and outputting the processed data to an external interface device, etc. In addition, the processor 1100 may include multiple various modules and devices. In this case, the added multiple modules may exchange data with the core unit 1110, the cache storage unit 1120, and each other through the bus interface 1130.

[0091] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. The volatile memory may include DRAM (Dynamic Random Access Memory), mobile DRAM, SRAM (Static Random Access Memory), and memories having similar functions to the above memories, etc. The non-volatile memory may include ROM (Read Only Memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and memories having similar functions.

[0092] The communication module unit 1150 may include a module capable of connecting to a wired network, a module capable of connecting to a wireless network, and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, power line communication (PLC), such as various devices that transmit and receive data via transmission lines, etc. The wireless network module may include Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Wireless Personal Area Network (Zigbee), Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High Speed Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), Ultra Wideband (UWB), such as various devices that transmit and receive data without transmission lines, etc.

[0093] The memory control unit 1160 is used to manage and process data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, for example, devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) card, Mini Secure Digital (mSD) card, Micro Secure Digital (microSD) card, Secure Digital High Capacity (SDHC) card, Memory Stick card, Smart Media (SM) card, Multimedia Card (MMC), Embedded MMC (eMMC), CompactFlash (CF) card, etc.

[0094] The media processing unit 1170 may process the data processed in the processor 1100 or the data input in the form of images, voices, etc. from an external input device, and output the data to an external interface device. The media processing unit 1170 may include a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), a High Definition Audio device (HD audio), a High Definition Multimedia Interface (HDMI) controller, etc.

[0095] Figure 9 is an example of a configuration diagram of a system that implements a storage circuit system based on the disclosed technology.

[0096] Reference Figure 9, the system 1200, as a device for processing data, can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems operated by a processor, such as a computer, a server, a PDA (Personal Digital Assistant), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (Portable Multimedia Player), a camera, a Global Positioning System (GPS), a video camera, a recorder, a telematics, an audio-visual (AV) system, a smart TV, etc.

[0097] The processor 1210 can decode the input commands, operate on, compare, etc. the data stored in the system 1200, and control these operations. The processor 1210 may be substantially the same as the above-mentioned microprocessor 1000 or the above-mentioned processor 1100.

[0098] The main storage device 1220 is a storage device that can temporarily store, call, and execute program code or data from the auxiliary storage device 1230 when executing a program, and can also save the stored content even when the power is cut off. The auxiliary storage device 1230 is a storage device for storing program code or data. Although the speed of the auxiliary storage device 1230 is slower than that of the main storage device 1220, the auxiliary storage device 1230 can store a larger amount of data. The main storage device 1220 or the auxiliary storage device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiment. For example, the main storage device 1220 or the auxiliary storage device 1230 may include: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, wherein the first electrode layer contains a first carbon material doped with a first element, and wherein the first oxide layer includes a first oxide of the first element. Thus, the storage cell characteristics and manufacturing process in the main storage device 1220 or the auxiliary storage device 1230 can be improved. As a result, the operating characteristics of the system 1200 can be improved.

[0099] In addition, in addition to or excluding the above-mentioned semiconductor devices, the main storage device 1220 or the auxiliary storage device 1230 may include a storage system (see Figure 10 the reference numeral 1300 in the drawing).

[0100] The interface device 1240 can be used to perform the exchange of commands and data between the system 1200 of the present embodiment and an external device. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HIDs), a communication device, etc. The communication device can be substantially the same as the above-mentioned communication module unit 1150.

[0101] Figure 10 is an example of a configuration diagram of a storage system that implements a storage circuit system based on the disclosed technology.

[0102] Refer to Figure 10 , the storage system 1300 may include a memory 1310 having non-volatile characteristics as a component for storing data, a controller 1320 for controlling the memory 1310, an interface 1330 for connecting to an external device, and a buffer memory 1340 for temporarily storing data to effectively transfer data between the interface 1330 and the memory 1310. The storage system 1300 can simply represent a memory for storing data, and can also represent a data storage device for long-term storage of the stored data. The storage system 1300 can be a disk type such as a solid state drive (SSD), and can be a card type such as a USB memory (Universal Serial Bus memory), a Secure Digital (SD) card, a Mini Secure Digital (mSD) card, a Micro Secure Digital (micro SD) card, a Secure Digital High Capacity (SDHC) card, a Memory Stick card, a Smart Media (SM) card, a Multimedia Card (MMC), an Embedded MMC (eMMC), a Compact Flash (CF) card, etc.

[0103] The memory 1310 or the buffer memory 1340 may include one or more of the above-mentioned semiconductor devices according to an embodiment. For example, the memory 1310 or the buffer memory 1340 may include: a first line; a second line disposed above the first line and spaced apart from the first line; a variable resistance layer disposed between the first line and the second line; a first electrode layer disposed between the first line and the variable resistance layer; and a first oxide layer disposed between the variable resistance layer and the first electrode layer, wherein the first electrode layer contains a first carbon material doped with a first element, and wherein the first oxide layer includes a first oxide of the first element. Thus, in the memory 1310 or the buffer memory 1340, the storage cell characteristics and the manufacturing process can be improved. As a result, the operating characteristics of the storage system 1300 can be improved.

[0104] In addition to or excluding the above-mentioned semiconductor devices, the memory 1310 or the buffer memory 1340 may include various memories such as non-volatile memories or volatile memories.

[0105] The controller 1320 can control the data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 can include a processor 1321 for performing operations such as processing commands input through the interface 1330 from the outside of the storage system 1300.

[0106] The interface 1330 is used to perform the exchange of commands and data between the storage system 1300 and an external device. When the storage system 1300 is of a card type or a disk type, the interface 1330 can be compatible with the interfaces used in devices of a card type or a disk type, or with the interfaces used in devices similar to the above-mentioned devices. The interface 1330 can be compatible with one or more interfaces of different types from each other.

[0107] Based on the storage device disclosed in this document Figures 7 to 10 The features in the above examples of the electronic devices or systems in can be implemented in various devices, systems, or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebooks or laptop computers, game consoles, smart televisions, set-top boxes, multimedia servers, digital cameras with or without wireless communication functions, watches or other wearable devices with wireless communication functions.

[0108] Although this patent document contains many details, these should not be construed as limitations on the scope of any disclosure or the scope of the claimed subject matter, but rather as descriptions of features that may be specific to particular embodiments of a particular disclosure. Certain features described in the context of various embodiments in this patent document may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although the above features may be described as acting in certain combinations and even initially claimed as such, in some cases one or more features from the claimed combination may be removed from that combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0109] Similarly, although operations are depicted in the figures in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the illustrated operations be performed, to achieve the desired results. Additionally, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0110] Only several embodiments and examples have been described. Based on what is described and illustrated in this patent document, other embodiments, improvements, and variations can be made.

[0111] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present teachings as defined in the appended claims.

Claims

1. An electronic device including a semiconductor memory, the semiconductor memory comprising: A first line; A second line, the second line being disposed above the first line and spaced apart from the first line; A variable resistance layer, the variable resistance layer being disposed between the first line and the second line; A first electrode layer, the first electrode layer being disposed between the first line and the variable resistance layer; And A first oxide layer, the first oxide layer being disposed between the variable resistance layer and the first electrode layer, A second electrode layer, the second electrode layer being disposed between the second line and the variable resistance layer; And A second oxide layer, the second oxide layer being disposed between the second electrode layer and the variable resistance layer, and A carbon layer, the carbon layer being between the second oxide layer and the variable resistance layer and including a second carbon material doped with a second element, Wherein the first electrode layer includes a first carbon material doped with a first element, Wherein the first oxide layer includes a first oxide of the first element, Wherein the second oxide layer includes a second oxide of the second element.

2. The electronic device according to claim 1, wherein The thickness of the first oxide layer is less than the thickness of the first electrode layer.

3. The electronic device according to claim 1, wherein, The resistance of the first oxide layer is greater than the resistance of the first electrode layer.

4. The electronic device according to claim 1, wherein, The first carbon material doped with the first element is amorphous.

5. The electronic device according to claim 1, wherein, The first electrode layer and the first oxide layer are in direct contact with each other.

6. The electronic device according to claim 1, wherein, The second electrode layer includes a second carbon material doped with the second element.

7. The electronic device according to claim 1, wherein, The thickness of the second oxide layer is less than the thickness of the second electrode layer.

8. The electronic device according to claim 1, wherein, The thickness of the carbon layer is less than the thickness of the second oxide layer.

9. The electronic device according to claim 1, wherein, The resistance of the second oxide layer is greater than the resistance of the second electrode layer.

10. The electronic device according to claim 1, wherein, The second carbon material doped with the second element is amorphous.

11. The electronic device according to claim 1, wherein, The semiconductor memory further includes: A first interface electrode layer, the first interface electrode layer being between the first oxide layer and the variable resistance layer.

12. The electronic device according to claim 1, wherein, The semiconductor memory further includes: A second interface electrode layer, the second interface electrode layer being between the second oxide layer and the variable resistance layer.

13. The electronic device according to claim 1, wherein, The semiconductor memory further includes: A third electrode layer, the third electrode layer being between the second line and the variable resistance layer; and A resistance layer, the resistance layer being between the second line and the third electrode layer.

14. The electronic device according to claim 1, wherein, The semiconductor memory further includes: A selection element layer, the selection element layer being between the first electrode layer and the first line, or between the variable resistance layer and the second line.

15. The electronic device according to claim 1, further comprising a microprocessor, the microprocessor comprising: A control unit, the control unit receiving a signal including a command from outside the microprocessor and performing extraction, decoding of the command or controlling input or output of signals of the microprocessor; An arithmetic unit, the arithmetic unit performing an operation based on a result of decoding the command by the control unit; And A storage unit that stores data for performing the operation, data corresponding to the result of performing the operation, or an address of the data for performing the operation. Wherein the semiconductor memory is part of the storage unit in the microprocessor.

16. The electronic device according to claim 1, further comprising a processor, the processor comprising: A core unit that performs an operation corresponding to a command by using data based on the command input from outside the processor. A cache storage unit that stores data for performing the operation, data corresponding to the result of performing the operation, or an address of the data for performing the operation. And A bus interface that is connected between the core unit and the cache storage unit and transfers data between the core unit and the cache storage unit. Wherein the semiconductor memory is part of the cache storage unit in the processor.

17. The electronic device according to claim 1, further comprising a processing system, the processing system comprising: A processor that decodes a command received by the processor and controls an operation on information based on the result of decoding the command. An auxiliary storage device that stores a program for decoding the command and the information. A main storage device that calls and stores the program and the information from the auxiliary storage device such that the processor can use the program and the information to perform the operation when the program is executed. And An interface device that performs communication between at least one of the processor, the auxiliary storage device, and the main storage device and the outside. Wherein the semiconductor memory is part of the auxiliary storage device or the main storage device in the processing system.

18. The electronic device according to claim 1, further comprising a storage system, the storage system comprising: A memory that stores data and retains the stored data regardless of the power supply. A memory controller that controls data input to the memory and data output from the memory according to a command input from the outside. A buffer memory that buffers data exchanged between the memory and the outside. And An interface that performs communication between at least one of the memory, the memory controller, and the buffer memory and the outside. Wherein the semiconductor memory is part of the memory or the buffer memory in the storage system.

19. A method for manufacturing an electronic device including a semiconductor memory, the method comprising: Forming a first electrode layer and a first oxide layer on a substrate. Forming a variable resistance layer on the first oxide layer, and Forming a second oxide layer on the variable resistance layer. Wherein the step of forming the first electrode layer and the first oxide layer includes: Form an initial first electrode layer comprising a first carbon material doped with a first element; and Form the first oxide layer comprising a first oxide of the first element by treating a portion of the initial first electrode layer with an oxygen-containing plasma or gas, and wherein the step of forming the second oxide layer comprises: Form an initial carbon layer comprising a second carbon material doped with a second element; and Form the second oxide layer comprising a second oxide of the second element by treating at least a portion of the initial carbon layer with an oxygen-containing plasma or gas.

20. The method according to claim 19, wherein, Perform the formation of the initial first electrode layer such that the first carbon material doped with the first element is amorphous.

21. The method according to claim 19, wherein, Perform the formation of the initial first electrode layer such that the concentration of the first element is substantially constant in the thickness direction of the initial first electrode layer.

22. The method according to claim 19, wherein The remaining portion of the initial first electrode layer other than the first oxide layer forms the first electrode layer, and wherein the formation of the first oxide layer is performed such that the first oxide layer has a thickness smaller than the thickness of the first electrode layer.

23. The method according to claim 19, wherein, Perform the formation of the initial carbon layer such that the second carbon material doped with the second element is amorphous.

24. The method according to claim 19, wherein, Perform the formation of the initial carbon layer such that the concentration of the second element is substantially constant in the thickness direction of the initial carbon layer.

25. The method according to claim 19, wherein, When a portion of the initial carbon layer is oxidized, the remaining portion of the initial carbon layer other than the second oxide layer forms a carbon layer, and wherein the formation of the second oxide layer is performed such that the second oxide layer has a thickness larger than the thickness of the carbon layer.

26. The method according to claim 19, further comprising: Form a second electrode layer over the second oxide layer.

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