Display panel and display device

Abstract

The present invention provides a display panel and a display device. The display panel includes a substrate module, a first conductive layer arranged in the substrate module, an insulating module arranged on the substrate module, a connecting groove penetrating the insulating module and a part of the substrate module to a surface of the first conductive layer, and a second conductive layer arranged on a surface of the insulating module away from the substrate module. The first wiring in the first conductive layer extends along a first direction and is arranged along a second direction intersecting with the first direction. The second wiring in the second conductive layer extends along the first direction and is arranged along the second direction. In the second direction, the width of the connecting groove is greater than or equal to the width of the first conductive layer, and each of the second wirings extends into the connecting groove to be electrically connected to the first conductive layer, thereby reducing the groove area, reducing the area of ​​the non-display area, and thus realizing a narrow-frame display.

Description

Technical Field

[0001] The present invention relates to the field of display equipment, and in particular to a display panel and a display device. Background Art

[0002] The concept of full screen has exploded in 2018 and has become the goal pursued by most smartphones. Among them, the penetration rate of OLED (Organic Light-Emitting Diode) full screen accounts for about 80%. Visually narrow borders, or even zero borders, have become the goal that the market continues to pursue. Among them, the routing design of the border area is one of the key factors affecting the distance to the non-display area.

[0003] In the non-display area of ​​a traditional display panel, the upper wiring is usually connected to the lower wiring by drilling holes independently. Generally speaking, the width of the hole is slightly larger than the line width of the wiring, which means that in many cases, the holes need to be arranged in multiple rows and columns in an interlaced manner to prevent interference between adjacent wirings, which will increase the area of ​​the non-display area, making it impossible to further achieve narrow or no borders. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a display device to solve the problem that the width of the non-display area of ​​the existing display panel cannot be reduced, thereby failing to further achieve narrow frame or frameless display.

[0005] To achieve the above-mentioned object, the present invention provides a display panel, which includes a substrate module, a first conductive layer, an insulating module, a connecting groove and a second conductive layer. The first conductive layer is arranged in the substrate module, and has a plurality of first wirings. The first wirings extend along a first direction and are arranged along a second direction intersecting with the first direction. The insulating module is arranged on the substrate module. The connecting groove passes through the insulating module and a part of the substrate module to a surface of the first conductive layer. The second conductive layer is arranged on a surface of the insulating module away from the substrate module, and has a plurality of second wirings. The second wirings extend along the first direction and are arranged along the second direction. In the second direction, the width of the connecting groove is greater than or equal to the width of the first conductive layer, and each of the second wirings extends into the connecting groove and is electrically connected to the first conductive layer.

[0006] Further, the second wiring includes a first connection portion and a second connection portion. The first connection portion is disposed on the insulating module. The second connection portion is attached to a side wall of the connection groove close to the first connection portion. An end of the second connection portion close to the bottom of the connection groove is electrically connected to the first wiring. An end of the second connection portion close to the notch of the connection groove is electrically connected to an end of the first connection portion close to the connection groove.

[0007] Furthermore, the display panel further comprises a passivation layer, wherein the passivation layer is disposed on the insulating module, covers the second conductive layer and fills the connection groove.

[0008] Further, the substrate module comprises a first flexible layer and a first barrier layer. The first flexible layer and the first conductive layer are arranged on the first flexible layer. The first barrier layer is arranged on the first flexible layer and covers the first conductive layer. The insulating module is arranged on a surface of the first barrier layer away from the first flexible layer.

[0009] Furthermore, the substrate module further comprises a second flexible layer, a second barrier layer and a buffer layer. The second flexible layer is arranged on a surface of the first barrier layer away from the first flexible layer. The second barrier layer is arranged on a surface of the second flexible layer away from the first barrier layer. The buffer layer is arranged on a surface of the second barrier layer away from the second flexible layer.

[0010] Furthermore, the insulating module comprises a gate insulating layer and an interlayer dielectric layer. The gate insulating layer is arranged on the substrate module. The interlayer dielectric layer is arranged on a surface of the gate insulating layer away from the substrate module. The second conductive layer is arranged on a surface of the interlayer dielectric layer away from the gate insulating layer.

[0011] Further, the display panel has a display area and a non-display area connected to the display area; a transition area is provided in the display area or the non-display area, and the connection groove is located in the transition area;

[0012] The display panel further comprises an array substrate, wherein the array substrate comprises the insulating module and a plurality of thin film transistors arranged in the insulating module. Therefore, the thin film transistor is located in the display area, and the second wiring is electrically connected to at least one of the thin film transistors. The insulating module extends from the display area to the non-display area. The first conductive layer extends from the non-display area to the transfer area. The second conductive layer extends from the display area to the transfer area.

[0013] Furthermore, the display panel further comprises a light emitting device layer and an encapsulation layer. The light emitting device layer is arranged on the array substrate in the display area and is electrically connected to the thin film transistors in the array substrate. The encapsulation layer is arranged on the array substrate and covers the light emitting device layer.

[0014] Furthermore, the display panel further comprises a chip-on-film, and the chip-on-film is electrically connected to an end of the first conductive layer away from the display area through a connecting terminal.

[0015] The present invention further provides a display device, comprising the display panel as described above.

[0016] The advantages of the present invention are as follows: a display panel and a display device of the present invention electrically connect the signal lines in the display area and the non-display area in the same connection groove, without separating the lines by multiple rows and columns of multiple independent slots, which greatly reduces the slot area, and further reduces the area of ​​the non-display area, thereby realizing narrow frame display. At the same time, the reduction in the number and density of slots can also reduce the accuracy of patterning during preparation, thereby reducing the difficulty of preparation and improving the yield rate of production. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic diagram of the partitions of the display panel in Embodiment 1 of the present invention;

[0019] Figure 2 for Figure 1 The cross-sectional structure diagram of the display panel at line AA';

[0020] Figure 3 This is a schematic diagram of the arrangement of the first routing line and the second routing line in Embodiment 1 of the present invention;

[0021] Figure 4 A schematic diagram of partitions of a display panel in Embodiment 2 of the present invention;

[0022] Figure 5 for Figure 4 The cross-sectional structure diagram of the display panel at line AA';

[0023] Figure 6 Schematic diagram of the arrangement of the first routing line and the second routing line in Embodiment 2 of the present invention.

[0024] The components in the figure are shown as follows:

[0025] Display panel 10; Display area 11;

[0026] Non-display area 12; Transfer area 13;

[0027] First direction X; Second direction Y;

[0028] Substrate module 100; First flexible layer 110;

[0029] A first barrier layer 120; A second flexible layer 130;

[0030] A second barrier layer 140; A buffer layer 150;

[0031] Array substrate 200; Source and drain electrodes 210 of thin film transistors;

[0032] Insulation module 220; Gate insulation layer 221;

[0033] Interlayer dielectric layer 222; Passivation layer 230;

[0034] planar layer 240; third conductive layer 250;

[0035] Pixel electrode layer 260; Pixel defining layer 270;

[0036] Light emitting device layer 300; Light emitting device 310;

[0037] Encapsulation layer 400; Covering layer 500;

[0038] Chip-on-film 600; Connecting terminal 610;

[0039] First conductive layer 700; First trace 710;

[0040] Second conductive layer 800; Second trace 810;

[0041] A first connection portion 811; A second connection portion 812;

[0042] Connection slot 900. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0044] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0045] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0046] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0047] Example 1

[0048] In an embodiment of the present invention, a display device is provided, which is an OLED (Organic Light-Emitting Diode) display device, which includes a display panel 10, and the display panel 10 is used to provide a display image for the display device. The display device can be any display device with a display function, such as a mobile phone, a tablet computer, a television, etc.

[0049] like Figure 1 and Figure 2As shown, the display panel 10 has a display area 11 and a non-display area 12 connected to the display area 11. The light-emitting display devices in the display panel 10 are mostly located in the display area 11, so that the image is presented in the display area 11. In the non-display area 12, there are mostly signal transmission devices, such as wiring, etc., which are connected to the light-emitting display devices in the display area 11 to transmit display signals. Furthermore, the non-display area 12 also has a transfer area 13, and the transfer area 13 is located on the side of the non-display area 12 close to the display area 11.

[0050] like Figure 2 As shown, the display panel 10 includes a substrate module 100 , a first conductive layer 700 , an array substrate 200 and a second conductive layer 800 .

[0051] The substrate module 100 covers the display area 11 and the non-display area 12, and includes a first flexible layer 110, a first barrier layer 120, a second flexible layer 130, a second barrier layer 140, and a buffer layer 150. The first barrier layer 120 covers a surface of the first flexible layer 110, the second flexible layer 130 covers a surface of the first barrier layer 120 away from the first flexible layer 110, the second barrier layer 140 covers a surface of the second flexible layer 130 away from the first barrier layer 120, and the buffer layer 150 covers a surface of the second barrier layer 140 away from the second flexible layer 130. The first flexible layer 110 and the second flexible layer 130 may be made of polyimide (PI) material, and the materials of the first barrier layer 120, the second barrier layer 140, and the buffer layer 150 contain inorganic materials, such as silicon nitride, silicon oxide, etc.

[0052] The first conductive layer 700 is disposed between the first flexible layer 110 and the first barrier layer 120 and has a plurality of first traces 710. The first conductive layer 700 is located in the non-display area 12 and extends from a side of the non-display area 12 away from the display area 11 into the transfer area 13.

[0053] The array substrate 200 is disposed on the buffer layer 150, and has a stacked insulating module 220 and a plurality of thin film transistors. The insulating module 220 is disposed on the buffer layer 150 in the display area 11, and extends from the display area 11 to cover the buffer layer 150 in the non-display area 12. The thin film transistors are disposed in the insulating module 220 and arranged in an array in the display area 11.

[0054] The insulating module 220 includes a gate insulating layer 221 and an interlayer dielectric layer 222. The gate insulating layer 221 is disposed on a surface of the buffer layer 150 away from the second barrier layer 140, and the interlayer dielectric layer 222 is disposed on a surface of the gate insulating layer 221 away from the buffer layer 150. The second conductive layer 800 is disposed on a surface of the interlayer dielectric layer 222 away from the gate insulating layer 221, is located in the display area 11, and is electrically connected to the source and drain electrodes 210 of the thin film transistors in the display area 11. One end of the second conductive layer 800 close to the non-display area 12 extends to the transfer area 13, and is electrically connected to the first conductive layer 700 through a connection groove 900.

[0055] Specifically, the connection groove 900 is located in the transfer area 13, and sequentially penetrates the interlayer dielectric layer 222, the gate insulating layer 221, the buffer layer 150, the second barrier layer 140, the second flexible layer 130 and the first barrier layer 120 to the surface of the first conductive layer 700, so that the first trace 710 in the first conductive layer 700 is exposed in the connection groove 900, and the exposed surface of the first conductive layer 700 and the first flexible layer 110 in the connection groove 900 is the bottom of the connection groove 900.

[0056] The second wiring 810 in the second conductive layer 800 includes a first connection portion 811 and a second connection portion 812. The first connection portion 811 is provided on the interlayer dielectric layer 222, one end of which is electrically connected to the source and drain 210 in the thin film transistor, and the other end thereof extends to the notch of the connection groove 900. The second connection portion 812 is attached to a side wall of the connection groove 900 near the first connection portion 811, one end of which is near the notch of the connection groove 900 is electrically connected to one end of the first connection portion 811 near the notch, and the other end thereof extends to the bottom of the connection groove 900 and is electrically connected to the first wiring 710 located at the bottom of the groove. The second wiring 810 attached to the side wall of the connection groove 900 can be realized by adjusting the spray direction of the evaporation source during evaporation or by patterning.

[0057] Furthermore, if Figure 3 As shown, the first wirings 710 in the first conductive layer 700 extend from the non-display area 12 to the transfer area 13 along the first direction X, and are arranged at intervals along the second direction Y perpendicular to the first direction X, and two adjacent first wirings 710 are electrically insulated from each other. The second wirings 810 in the second conductive layer 800 also extend from the connection grooves 900 to the display area 11 along the first direction X, and are also arranged at intervals along the second direction Y, and two adjacent second wirings 810 are electrically insulated from each other.

[0058] In the second direction Y, the width of the connection groove 900 is greater than or equal to the width of the first conductive layer 700, so that all the first wirings 710 in the first conductive layer 700 are exposed in the same connection groove 900. At the same time, in the connection groove 900, each second wiring 810 is electrically connected to a corresponding first wiring 710 to realize the transmission of the display signal. Even if all the first wirings 710 and all the second wirings 810 are electrically connected in the same connection groove 900, the adjacent signal transmission circuits are electrically insulated and will not be affected. Moreover, only one column of slots is needed to realize the connection of all wirings in the same connection groove 900, and there is no need to make electrical connections through multiple rows and columns of independent slots, which greatly reduces the slot area, and further reduces the area of ​​the non-display area 12, which is conducive to realizing narrow frame display.

[0059] like Figure 2 As shown, the array substrate 200 further includes a double-layer flat layer 240, a third conductive layer 250, a pixel electrode layer 260 and a pixel defining layer 270. The double-layer flat layer 240 is stacked on a surface of the passivation layer 230 away from the second conductive layer 800, and the third conductive layer 250 is disposed between the double-layer flat layers 240 and is electrically connected to the source and drain electrodes 210 of the thin film transistor. The pixel electrode layer 260 is disposed on a surface of the flat layer 240 away from the third conductive layer 250, and is electrically connected to the third conductive layer 250 through the flat layer 240, thereby being indirectly electrically connected to the source and drain electrodes 210 of the thin film transistor through the third conductive layer 250. The pixel defining layer 270 is disposed on a surface of the flat layer 240 away from the third conductive layer 250, and has an opening corresponding to the pixel electrode layer 260, so that the upper surface of the pixel electrode layer 260 is exposed.

[0060] Furthermore, the display panel 10 further includes a light emitting device layer 300 , an encapsulation layer 400 , a cover layer 500 and a chip-on-film 600 .

[0061] The light emitting device layer 300 is provided on the array substrate 200 and is located in the display area 11. The light emitting device layer 300 includes a plurality of light emitting devices 310, and the light emitting devices 310 are provided in the openings of the pixel defining layer 270 and are electrically connected to the pixel electrode layer 260 in the openings, and the pixel electrode layer 260 is the cathode or anode of the light emitting device 310. The cathode or anode of the light emitting device 310 is electrically connected to the thin film transistor through the third conductive layer 250, and the thin film transistor is used as a switching device to control the opening and closing of each light emitting device 310 in the light emitting device layer 300, thereby realizing the display of the picture. In the embodiment of the present invention, the light emitting device 310 is an OLED light emitting device 310.

[0062] The encapsulation layer 400 covers the exposed surface of the light emitting device layer 300 and the array substrate 200, and is prepared by thin film encapsulation technology (Thin Film Encapsulastion, TFE), and is used to protect the light emitting device layer 300 and the conductive structure in the array substrate 200 to prevent water and oxygen from invading. The covering layer 500 is an overcoat (OC) film, which is arranged on a surface of the encapsulation layer 400 away from the light emitting device layer 300, and extends from the display area 11 to cover the non-display area 12. The covering layer 500 is used to flatten the panel surface in the display area 11 to facilitate the lamination of other film layers.

[0063] The COF 600 is disposed on a side of the display area 11 away from the display area 11, and is electrically connected to an end of the first conductive layer 700 away from the display area 11 through a connection terminal 610, and is further electrically connected to the array substrate 200. The COF 600 is provided with an IC chip for processing image information and forming a display signal, and is transmitted to each thin film transistor through a first wiring 710 in the first conductive layer 700 and a second wiring 810 in the second conductive layer 800. The thin film transistor in the array substrate 200 then controls the light emission of each light emitting device 310 in the light emitting device layer 300 according to the display signal, so as to form a desired display screen.

[0064] In the display panel provided in the embodiment of the present invention, the first wiring of the first conductive layer and the second wiring of the second conductive layer are electrically connected in the same connection groove, and there is no need to electrically connect through multiple rows and columns of multiple independent slots, which greatly reduces the slot area, and further reduces the area of ​​the non-display area to achieve narrow frame display. At the same time, the reduction in the number and density of slots can also reduce the accuracy of patterning during preparation, thereby reducing the difficulty of preparation and improving the yield rate of production.

[0065] Example 2

[0066] In an embodiment of the present invention, a display panel 10 is provided. Figure 4 and Figure 5 As shown, the display panel 10 has a display area 11 and a non-display area 12 connected to the display area 11. The light-emitting display devices in the display panel 10 are mostly located in the display area 11, so that the image is presented in the display area 11. In the non-display area 12, there are mostly signal transmission devices, such as wiring, etc., which are connected to the light-emitting display devices in the display area 11 to transmit display signals. Furthermore, the display area 11 also has a transfer area 13, and the transfer area 13 is located on the side of the display area 11 close to the non-display area 12.

[0067] like Figure 5 As shown, the display panel 10 includes a substrate module 100 , a first conductive layer 700 , an array substrate 200 and a second conductive layer 800 .

[0068] The substrate module 100 covers the display area 11 and the non-display area 12, and includes a first flexible layer 110, a first barrier layer 120, a second flexible layer 130, a second barrier layer 140, and a buffer layer 150. The first barrier layer 120 covers a surface of the first flexible layer 110, the second flexible layer 130 covers a surface of the first barrier layer 120 away from the first flexible layer 110, the second barrier layer 140 covers a surface of the second flexible layer 130 away from the first barrier layer 120, and the buffer layer 150 covers a surface of the second barrier layer 140 away from the second flexible layer 130. The first flexible layer 110 and the second flexible layer 130 may be made of polyimide (PI) material, and the materials of the first barrier layer 120, the second barrier layer 140, and the buffer layer 150 contain inorganic materials, such as silicon nitride, silicon oxide, etc.

[0069] The first conductive layer 700 is disposed between the first flexible layer 110 and the first barrier layer 120, and has a plurality of first traces 710. The first conductive layer 700 is located in the non-display area 12, and extends from a side of the non-display area 12 away from the display area 11 into the transfer area 13 located in the display area 11.

[0070] The array substrate 200 is disposed on the buffer layer 150, and has a stacked insulating module 220 and a plurality of thin film transistors. The insulating module 220 is disposed on the buffer layer 150 in the display area 11, and extends from the display area 11 to cover the buffer layer 150 in the non-display area 12. The thin film transistors are disposed in the insulating module 220 and arranged in an array in the display area 11.

[0071] The insulating module 220 includes a gate insulating layer 221 and an interlayer dielectric layer 222. The gate insulating layer 221 is disposed on a surface of the buffer layer 150 away from the second barrier layer 140, and the interlayer dielectric layer 222 is disposed on a surface of the gate insulating layer 221 away from the buffer layer 150. The second conductive layer 800 is disposed on a surface of the interlayer dielectric layer 222 away from the gate insulating layer 221, is located in the display area 11, and is electrically connected to the source and drain electrodes 210 of the thin film transistors in the display area 11. One end of the second conductive layer 800 close to the non-display area 12 extends to the transfer area 13, and is electrically connected to the first conductive layer 700 through a connection groove 900.

[0072] Specifically, the connection groove 900 is located in the transfer area 13, and sequentially penetrates the interlayer dielectric layer 222, the gate insulating layer 221, the buffer layer 150, the second barrier layer 140, the second flexible layer 130 and the first barrier layer 120 to the surface of the first conductive layer 700, so that the first trace 710 in the first conductive layer 700 is exposed in the connection groove 900, and the exposed surface of the first conductive layer 700 and the first flexible layer 110 in the connection groove 900 is the bottom of the connection groove 900.

[0073] The second wiring 810 in the second conductive layer 800 includes a first connection portion 811 and a second connection portion 812. The first connection portion 811 is provided on the interlayer dielectric layer 222, one end of which is electrically connected to the source and drain 210 in the thin film transistor, and the other end thereof extends to the notch of the connection groove 900. The second connection portion 812 is attached to a side wall of the connection groove 900 close to the first connection portion 811, one end of which close to the notch of the connection groove 900 is electrically connected to one end of the first connection portion 811 close to the notch, and the other end thereof extends to the bottom of the connection groove 900 and is electrically connected to the first wiring 710 located at the bottom of the groove. The second wiring 810 attached to the side wall of the connection groove 900 can be realized by adjusting the spray direction of the evaporation source during evaporation or by patterning.

[0074] Furthermore, if Figure 6As shown, the first wiring 710 in the first conductive layer 700 extends from the non-display area 12 to the transfer area 13 along the first direction X, and is arranged at intervals along the second direction Y perpendicular to the first direction X, and two adjacent first wirings 710 are electrically insulated from each other. The second wiring 810 in the second conductive layer 800 also extends from the source and drain electrodes 210 of the thin film transistor to the bottom of the connecting groove 900 along the first direction X, and is also arranged at intervals along the second direction Y, and two adjacent second wirings 810 are electrically insulated from each other.

[0075] In the second direction Y, the width of the connection groove 900 is greater than or equal to the width of the first conductive layer 700, so that all the first wirings 710 in the first conductive layer 700 are exposed in the same connection groove 900. At the same time, in the connection groove 900, each second wiring 810 is electrically connected to a corresponding first wiring 710 to realize the transmission of the display signal. Even if all the first wirings 710 and all the second wirings 810 are electrically connected in the same connection groove 900, the adjacent signal transmission circuits are electrically insulated and will not be affected. Moreover, only one column of slots is needed to realize the connection of all wirings in the same connection groove 900, and there is no need to make electrical connections through multiple rows and columns of independent slots, which greatly reduces the slot area, and further reduces the area of ​​the non-display area 12, which is conducive to realizing narrow frame display. Moreover, in the present embodiment, a connection groove 900 is further arranged in the display area 11, and the orthographic projection of the connection groove 900 in the display panel 10 is made to coincide with the orthographic projections of other display devices in the display area 11 without affecting the display device structure (such as the light-emitting device 310 and the third conductive layer 250) in the display area 11, thereby further reducing the area of ​​the non-display area 12 without affecting the resolution of the display area 11.

[0076] like Figure 5As shown, the array substrate 200 further includes a double-layer flat layer 240, a third conductive layer 250, a pixel electrode layer 260 and a pixel defining layer 270. The double-layer flat layer 240 is stacked on a surface of the passivation layer 230 away from the second conductive layer 800, and the third conductive layer 250 is disposed between the double-layer flat layers 240 and is electrically connected to the source and drain electrodes 210 of the thin film transistor. The pixel electrode layer 260 is disposed on a surface of the flat layer 240 away from the third conductive layer 250, and is electrically connected to the third conductive layer 250 through the flat layer 240, thereby being indirectly electrically connected to the source and drain electrodes 210 of the thin film transistor through the third conductive layer 250. The pixel defining layer 270 is disposed on a surface of the flat layer 240 away from the third conductive layer 250, and has an opening corresponding to the pixel electrode layer 260, so that the upper surface of the pixel electrode layer 260 is exposed.

[0077] Furthermore, the display panel 10 further includes a light emitting device layer 300 , an encapsulation layer 400 , a cover layer 500 and a chip-on-film 600 .

[0078] The light emitting device layer 300 is provided on the array substrate 200 and is located in the display area 11. The light emitting device layer 300 includes a plurality of light emitting devices 310, and the light emitting devices 310 are provided in the openings of the pixel defining layer 270 and are electrically connected to the pixel electrode layer 260 in the openings, and the pixel electrode layer 260 is the cathode or anode of the light emitting device 310. The cathode or anode of the light emitting device 310 is electrically connected to the thin film transistor through the third conductive layer 250, and the thin film transistor is used as a switching device to control the opening and closing of each light emitting device 310 in the light emitting device layer 300, thereby realizing the display of the picture. In the embodiment of the present invention, the light emitting device 310 is an OLED light emitting device 310.

[0079] The encapsulation layer 400 covers the exposed surface of the light emitting device layer 300 and the array substrate 200, and is prepared by thin film encapsulation technology (Thin Film Encapsulastion, TFE), and is used to protect the light emitting device layer 300 and the conductive structure in the array substrate 200 to prevent water and oxygen from invading. The covering layer 500 is an overcoat (OC) film, which is arranged on a surface of the encapsulation layer 400 away from the light emitting device layer 300, and extends from the display area 11 to cover the non-display area 12. The covering layer 500 is used to flatten the panel surface in the display area 11 to facilitate the lamination of other film layers.

[0080] The COF 600 is disposed on a side of the display area 11 away from the display area 11, and is electrically connected to an end of the first conductive layer 700 away from the display area 11 through a connection terminal 610, and is further electrically connected to the array substrate 200. The COF 600 is provided with an IC chip for processing image information and forming a display signal, and is transmitted to each thin film transistor through a first wiring 710 in the first conductive layer 700 and a second wiring 810 in the second conductive layer 800. The thin film transistor in the array substrate 200 then controls the light emission of each light emitting device 310 in the light emitting device layer 300 according to the display signal, so as to form a desired display screen.

[0081] The embodiment of the present invention is a preferred embodiment. In the embodiment of the present invention, the orthographic projection of the connection groove in the display panel can coincide with the orthographic projection of the light-emitting device layer or the third connection layer in the display panel, and while achieving all the technical effects in the embodiment 1 of the present invention, the area of ​​the non-display area can be further reduced, thereby achieving a narrow frame or even a frameless display.

[0082] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A display panel, characterized in that: include: Substrate module; A first conductive layer, disposed in the substrate module, having a plurality of first traces; The first traces extend along a first direction and are arranged along a second direction intersecting the first direction; An insulating module, wherein the insulating module is arranged on the substrate module; a connecting groove, penetrating the insulating module and a portion of the substrate module to a surface of the first conductive layer; A second conductive layer is disposed on a surface of the insulating module away from the substrate module and has a plurality of second traces; The second traces extend along the first direction and are arranged along the second direction; In the second direction, the width of the connection groove is greater than or equal to the width of the first conductive layer, each of the second routing lines extends into the connection groove and is electrically connected to the first conductive layer, and each second routing line is electrically connected to a corresponding first routing line.

2. The display panel according to claim 1, wherein: The second routing includes: A first connecting portion, provided on the insulating module; A second connecting portion, attached to a side wall of the connecting groove close to the first connecting portion; One end of the second connection portion close to the bottom of the connection groove is electrically connected to the first wiring; One end of the second connection portion close to the connection slot is electrically connected to one end of the first connection portion close to the connection slot.

3. The display panel according to claim 1, wherein: Also includes: A passivation layer is disposed on the insulating module, covers the second conductive layer and fills the connecting groove.

4. The display panel according to claim 1, wherein: The substrate module comprises: a first flexible layer, wherein the first conductive layer is disposed on the first flexible layer; a first barrier layer, disposed on the first flexible layer and covering the first conductive layer; The insulating module is disposed on a surface of the first barrier layer away from the first flexible layer.

5. The display panel according to claim 4, wherein: The substrate module also includes: A second flexible layer is disposed on a surface of the first barrier layer away from the first flexible layer; A second barrier layer is disposed on a surface of the second flexible layer away from the first barrier layer; The buffer layer is disposed on a surface of the second barrier layer away from the second flexible layer.

6. The display panel according to claim 1, wherein: The insulation module comprises: A gate insulating layer, disposed on the substrate module; An interlayer dielectric layer is disposed on a surface of the gate insulating layer away from the substrate module; The second conductive layer is disposed on a surface of the interlayer dielectric layer away from the gate insulating layer.

7. The display panel according to claim 1, wherein: Having a display area and a non-display area connected to the display area; A transfer area is provided in the display area or the non-display area, and the connection groove is located in the transfer area; The display panel further includes: An array substrate, comprising the insulating module and a plurality of thin film transistors arranged in the insulating module; The thin film transistor is located in the display area, and the second wiring is electrically connected to at least one of the thin film transistors; The insulating module extends from the display area to the non-display area; The first conductive layer extends from the non-display area to the transfer area; The second conductive layer extends from the display area to the transfer area.

8. The display panel according to claim 7, wherein: Also includes: A light emitting device layer, provided on the array substrate in the display area and electrically connected to the thin film transistor in the array substrate; The packaging layer is disposed on the array substrate and covers the light emitting device layer.

9. The display panel according to claim 7, wherein: A chip-on-chip film is also included, and the chip-on-chip film is electrically connected to an end of the first conductive layer away from the display area through a connecting terminal.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-9.

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