Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate, the substrate comprising a chip region, the chip region comprising a device region and a cutting road region surrounding the device region; a guard ring structure located on the cutting road region, the guard ring structure surrounding the device region, the guard ring structure comprising: a plurality of first metal layers overlapping in a direction perpendicular to the substrate surface and a second metal structure, the second metal structure comprising at least one second metal layer, the second metal layer being located between two adjacent first metal layers, any second metal layers being separated from each other, and the center lines of two adjacent second metal layers not overlapping. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] Since silicon materials are brittle, when the wafer is cut, the cutting method of the cutting knife will generate certain mechanical stress on the front and back of the wafer, which may cause chip edge collapse. The chip edge collapse problem will reduce the mechanical strength of the chip. The initial chip edge crack will further spread in the subsequent packaging process or in the use of the chip product, which is likely to cause the chip to break, resulting in electrical failure of the chip. In order to protect the internal circuit of the chip, prevent dicing damage, and improve chip reliability, a chip seal ring (SR) structure is usually designed around the chip.

[0003] When the wafer is cut along the cutting path, the chip sealing ring structure can prevent unnecessary stress expansion and cracking from the cutting path to the chip caused by the wafer cutting process. In addition, the chip sealing ring structure also has the ability to resist gas and liquid erosion, and can prevent the penetration and damage of water vapor or other chemical pollution sources.

[0004] In today's semiconductor technology, the size of semiconductor components has been miniaturized, which has put forward higher requirements on the crack prevention capability and gas-liquid shielding capability of the chip sealing ring.

[0005] Therefore, how to enhance the gas-liquid barrier capability and crack barrier capability of the chip sealing ring structure is an urgent problem to be solved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to enhance the performance of a chip sealing ring structure.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a chip area, the chip area including a device area and a cutting road area surrounding the device area; a guard ring structure located on the cutting road area, the guard ring structure surrounding the device area, the guard ring structure including: a plurality of first metal layers and a second metal structure overlapping in a direction perpendicular to the surface of the substrate, the second metal structure including at least one second metal layer, the second metal layer being located between two adjacent first metal layers, any second metal layers being separated from each other, and the center lines of two adjacent second metal layers do not overlap.

[0008] Optionally, the second metal structure includes a plurality of second metal layers, and in a direction parallel to the substrate surface, the plurality of second metal layers are concentrically distributed around the device region.

[0009] Optionally, there are multiple first metal layers, and in a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed around the device region, and the first metal layer and the second metal layer are overlapped and arranged in a direction perpendicular to the substrate surface.

[0010] Optionally, there are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device area.

[0011] Optionally, the projection pattern of the first metal layer on the substrate is a closed ring having a first width; the projection pattern of the second metal layer on the substrate is a discontinuous ring having a second width.

[0012] Optionally, the first width is greater than the second width, or the first width is less than the second width.

[0013] Optionally, the guard ring structure also includes: a plurality of third metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers located on the third metal layers, the projection pattern of the third metal layer on the substrate is a closed ring, and the projection pattern of the fourth metal layer on the substrate is a closed ring.

[0014] Optionally, the guard ring structure also includes: several layers of fifth metal layers and several layers of sixth metal layers alternately arranged in a direction perpendicular to the substrate surface, any layers of the fifth metal layers are separate from each other, any layers of the sixth metal layers are separate from each other, center lines of two adjacent layers of the fifth metal layers do not overlap, and center lines of two adjacent layers of the sixth metal layers do not overlap.

[0015] Optionally, the projection pattern of the fifth metal layer on the substrate forms a discontinuous ring, and the projection pattern of the sixth metal layer on the substrate forms a discontinuous ring.

[0016] Optionally, it further includes: a dielectric structure located on the substrate, and the guard ring structure is located in the dielectric structure.

[0017] Optionally, the material of the first metal layer includes metal or metal nitride; the material of the second metal layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes: a combination of one or more of tantalum nitride and titanium nitride.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a chip area, the chip area including a device area and a cutting road area surrounding the device area; forming a guard ring structure in the cutting road area, the guard ring structure surrounding the device area, the guard ring structure comprising: a plurality of first metal layers overlapping in a direction perpendicular to the substrate surface and a second metal structure, the second metal structure comprising at least one second metal layer, the second metal layer being located between two adjacent first metal layers, any second metal layers being separated from each other, and the center lines of two adjacent second metal layers do not overlap.

[0019] Optionally, the second metal structure includes a plurality of second metal layers, and in a direction parallel to the substrate surface, the plurality of second metal layers are concentrically distributed around the device region.

[0020] Optionally, there are multiple first metal layers, and in a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed around the device region, and the first metal layer and the second metal layer are overlapped and arranged in a direction perpendicular to the substrate surface.

[0021] Optionally, there are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device area.

[0022] Optionally, the projection pattern of the first metal layer on the substrate is a closed ring having a first width; the projection pattern of the second metal layer on the substrate is a discontinuous ring having a second width.

[0023] Optionally, the first width is greater than the second width, or the first width is less than the second width.

[0024] Optionally, the guard ring structure also includes: a plurality of third metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers located on the third metal layers, the projection pattern of the third metal layer on the substrate is a closed ring, and the projection pattern of the fourth metal layer on the substrate is a closed ring.

[0025] Optionally, the guard ring structure also includes: a plurality of fifth metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of sixth metal layers located on the fifth metal layers, any layer of the fifth metal layers are separate from each other, any layer of the sixth metal layers are separate from each other, center lines of two adjacent fifth metal layers do not overlap, and center lines of two adjacent sixth metal layers do not overlap.

[0026] Optionally, the first metal layer and the third metal layer are formed simultaneously; the second metal layer and the fourth metal layer are formed simultaneously.

[0027] Optionally, the method further includes: forming a dielectric structure on the substrate, wherein the guard ring structure is located within the dielectric structure.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The semiconductor structure of the technical solution of the present invention has a guard ring structure on the cutting road area, and the guard ring structure surrounds the device area. The guard ring structure includes: a plurality of first metal layers and a second metal structure that overlap in a direction perpendicular to the substrate surface, and the second metal structure includes a plurality of second metal layers, and the second metal layer is located between two adjacent first metal layers. Any second metal layer is separated from each other, and the center lines of two adjacent second metal layers do not overlap. Therefore, the stress of the plurality of second metal layers is small, so that the buffering capacity of the guard ring structure is enhanced, so that when crack expansion occurs when cutting the substrate, the guard ring structure can weaken the crack expansion force, reduce the situation where the crack expands to the device area, and improve the performance of the chip.

[0030] Furthermore, the projection pattern of the first metal layer on the substrate is a closed ring, so that the protection ring structure has a certain gas-liquid blocking ability.

[0031] Furthermore, the guard ring structure further includes: a plurality of third metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers located on the third metal layers, the projection pattern of the third metal layers on the substrate is a closed ring, and the projection pattern of the fourth metal layers on the substrate is a closed ring. Thus, the guard ring structure has a good gas-liquid blocking ability, thereby compensating for the situation that when the second metal layer is a mesh structure, the gas and liquid are easy to penetrate from the mesh structure of the second metal layer.

[0032] Furthermore, the guard ring structure also includes: a plurality of fifth metal layers and a plurality of sixth metal layers alternately arranged in a direction perpendicular to the substrate surface, any of the fifth metal layers are separated from each other, any of the sixth metal layers are separated from each other, the center lines of two adjacent fifth metal layers do not overlap, and the center lines of two adjacent sixth metal layers do not overlap. The fifth metal layer and the sixth metal layer can work together with the second metal layer to weaken the crack expansion force, reduce the situation where the crack expands to the device area, and improve the performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 6 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background art, the gas-liquid blocking capability and crack blocking capability of the existing chip sealing ring structure need to be enhanced.

[0035] Specifically, as the size of semiconductor structures becomes smaller and smaller, the corresponding cutting channels become narrower and narrower. Therefore, when the cutting knife cuts the wafer along the cutting channel, the distance between the cutting knife and the chip becomes smaller and smaller. If the sealing ring structure around the chip does not have sufficient crack prevention ability, the cracks generated by the cutting knife cutting the wafer can easily spread to the chip, thereby causing electrical failure of the chip.

[0036] In order to solve the above problems, the technical solution of the present invention also provides a semiconductor structure and a method for forming a semiconductor structure, wherein a guard ring structure is provided on the cutting road area, the guard ring structure surrounds the device area, and the guard ring structure includes: a plurality of first metal layers and a second metal structure overlapping in a direction perpendicular to the substrate surface, the second metal structure includes a plurality of second metal layers, the second metal layer is located between two adjacent first metal layers, any second metal layers are separated from each other, and the center lines of two adjacent second metal layers do not overlap. Thus, the stress of the plurality of second metal layers is small, so that the buffering capacity of the guard ring structure is enhanced, so that when crack expansion occurs when cutting the substrate, the guard ring structure can weaken the crack expansion force, reduce the situation where the crack expands to the device area, and improve the performance of the chip.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 1 to 5 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0039] Please refer to Figure 1 , providing a substrate, wherein the substrate includes a chip region, wherein the chip region includes a device region 200 and a cutting road region 201 surrounding the device region 200 .

[0040] The device region 200 is used to form semiconductor devices; the dicing road region 201 is used to divide the device region 200 along the dicing road region 201 .

[0041] In this embodiment, the material of the substrate is silicon.

[0042] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0043] Please refer to Figures 2 to 4 , Figure 2 for Figure 3 and Figure 4 A top view of Figure 3 for Figure 2 A schematic cross-sectional structure diagram along the direction of the cross-sectional line BB1 ​​omitting the dielectric structure 209, Figure 4 for Figure 2 A schematic structural diagram in which the dielectric structure 209 is omitted along the section line CC1 direction, wherein a guard ring structure is formed in the cutting path area 201, and the guard ring structure surrounds the device area 200, and the guard ring structure includes: a plurality of first metal layers 202 and a second metal structure overlapping in a direction perpendicular to the substrate surface, wherein the second metal structure includes at least one second metal layer 203, and the second metal layer 203 is located between two adjacent first metal layers 202, and any layer of the second metal layer 203 is separated from each other, and the center lines of two adjacent second metal layers 203 do not overlap.

[0044] As a result, the stress of the second metal layer 203 is relatively small, so that the buffering capacity of the guard ring structure is enhanced. When crack expansion occurs when cutting the substrate, the guard ring structure can weaken the crack expansion force and reduce the crack expansion to the device area 200, thereby improving the performance of the chip.

[0045] In this embodiment, the second metal structure includes a plurality of second metal layers 203 . In a direction parallel to the substrate surface, the plurality of second metal layers 203 are concentrically distributed around the device region 200 .

[0046] There are multiple first metal layers 202, and in a direction parallel to the substrate surface, multiple first metal layers 202 are concentrically distributed around the device region, and the first metal layer 202 and the second metal layer 203 are overlapped and arranged in a direction perpendicular to the substrate surface. In this embodiment, one first metal layer 202 is schematically shown.

[0047] There are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device region 200 .

[0048] In this embodiment, the projection pattern of the first metal layer 202 on the substrate is a closed ring having a first width. The projection pattern of the first metal layer 203 on the substrate is a closed ring, so that the guard ring structure has a certain gas-liquid blocking ability.

[0049] In this embodiment, the projection pattern of the second metal layer 203 on the substrate forms a discontinuous ring shape, and the discontinuous ring shape has a second width.

[0050] In this embodiment, the first width is greater than the second width.

[0051] In another embodiment, the first width is smaller than the second width.

[0052] Please refer to Figure 5 , Figure 5 for Figure 2 The schematic cross-sectional structure diagram of the dielectric structure 209 is omitted along the direction of the cross-sectional line DD1.

[0053] In this embodiment, the guard ring structure also includes: a plurality of third metal layers 204 alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers 205 located on the third metal layers 204, the projection pattern of the third metal layer 204 on the substrate is a closed ring, and the projection pattern of the fourth metal layer 205 on the substrate is a closed ring.

[0054] Therefore, the protection ring structure has a good gas-liquid blocking capability, thereby compensating for the situation that when the second metal layer 203 is a mesh structure, the gas and liquid are easy to penetrate from the mesh structure of the second metal layer 203 .

[0055] There may be a plurality of the third metal layer 204 and the fourth metal layer 205 , and the plurality of the third metal layers 204 and the fourth metal layers 205 are concentrically distributed around the device region 200 .

[0056] In other embodiments, the third metal layer and the fourth metal layer may not be formed.

[0057] Please refer to Figure 6 , Figure 6 for Figure 2 The schematic cross-sectional structure diagram of the dielectric structure 209 is omitted along the direction of the cross-sectional line EE1.

[0058] In this embodiment, the guard ring structure also includes: a plurality of fifth metal layers 206 alternately arranged in a direction perpendicular to the substrate surface and a plurality of sixth metal layers 207 located on the fifth metal layers 206, any layer of the fifth metal layers 205 are separated from each other, any layer of the sixth metal layers 207 are separated from each other, the center lines of two adjacent layers of the fifth metal layers 205 do not overlap, and the center lines of two adjacent layers of the sixth metal layers 207 do not overlap.

[0059] The fifth metal layer 206 and the sixth metal layer 207 can work together with the second metal layer 203 to weaken the crack expansion force, reduce the crack expansion to the device area 200, and improve the performance of the chip.

[0060] There may be a plurality of the fifth metal layer 206 and the sixth metal layer 207 , and the plurality of the fifth metal layers 206 and the sixth metal layers 207 are concentrically distributed around the device region 200 .

[0061] In other embodiments, the fifth metal layer and the sixth metal layer may not be formed.

[0062] In this embodiment, the first metal layer 202, the third metal layer 204 and the fifth metal layer 206 are formed simultaneously; the second metal layer 203, the fourth metal layer 205 and the sixth metal layer 207 are formed simultaneously.

[0063] The method for forming the guard ring structure includes: forming a dielectric structure 209 on a substrate; forming an overlapping first metal layer 202 and a second metal structure in the dielectric structure 209 , forming an overlapping third metal layer 204 and a fourth metal layer 205 in the dielectric structure 209 , and forming an overlapping fifth metal layer 206 and a sixth metal layer 207 in the dielectric structure 209 .

[0064] The materials of the first metal layer 202, the third metal layer 204 and the fifth metal layer 206 include metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0065] The materials of the second metal layer 203, the fourth metal layer 205 and the sixth metal layer 207 include metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0066] The material of the dielectric structure 209 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0067] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figures 1 to 6 , include:

[0068] A substrate, the substrate includes a chip area, the chip area includes a device area 200 and a cutting road area 201 surrounding the device area 200; a guard ring structure located on the cutting road area 201, the guard ring structure surrounds the device area 200, and the guard ring structure includes: a plurality of first metal layers 202 and a second metal structure overlapping in a direction perpendicular to the substrate surface, the second metal structure includes at least one second metal layer 203, the second metal layer 203 is located between two adjacent first metal layers 202, any second metal layers 203 are separated from each other, and the center lines of two adjacent second metal layers 203 do not overlap.

[0069] In this embodiment, the second metal structure includes a plurality of second metal layers 203 , and the plurality of second metal layers 203 are concentrically distributed around the device region 200 .

[0070] In this embodiment, there are multiple first metal layers 202. In the direction parallel to the substrate surface, the multiple first metal layers 202 are concentrically distributed around the device area, and the first metal layer 202 and the second metal layer 203 are overlapped and arranged in a direction perpendicular to the substrate surface.

[0071] In this embodiment, there are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device region 200 .

[0072] In this embodiment, the projection pattern of the first metal layer 203 on the substrate is a closed ring having a first width; the projection pattern of the second metal layer 203 on the substrate is a discontinuous ring having a second width.

[0073] In this embodiment, the first width is greater than the second width, or the first width is less than the second width.

[0074] In this embodiment, the guard ring structure also includes: a plurality of third metal layers 204 alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers 205 located on the third metal layers 204, the projection pattern of the third metal layer 204 on the substrate is a closed ring, and the projection pattern of the fourth metal layer 205 on the substrate is a closed ring.

[0075] In this embodiment, the guard ring structure also includes: several layers of fifth metal layers 206 and several layers of sixth metal layers 207 alternately arranged in a direction perpendicular to the substrate surface, any layers of the fifth metal layers 206 are separated from each other, any layers of the sixth metal layers 207 are separated from each other, the center lines of two adjacent layers of the fifth metal layers 206 do not overlap, and the center lines of two adjacent layers of the sixth metal layers 207 do not overlap.

[0076] In this embodiment, the projection pattern of the fifth metal layer 206 on the substrate forms a discontinuous ring shape, and the projection pattern of the sixth metal layer 207 on the substrate forms a discontinuous ring shape.

[0077] In this embodiment, the device further includes: a dielectric structure 209 located on the substrate, and the guard ring structure is located in the dielectric structure 209 .

[0078] In this embodiment, the material of the first metal layer 202 includes metal or metal nitride; the material of the second metal layer 203 includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a chip region, the chip region comprising a device region and a scribe line region surrounding the device region; A guard ring structure located on a cutting path area, the guard ring structure surrounds the device area, the guard ring structure comprises: a plurality of first metal layers and a second metal structure overlapping in a direction perpendicular to a substrate surface, the second metal structure comprises at least one second metal layer, the second metal layer is located between two adjacent first metal layers, any two second metal layers are separated from each other, the center lines of two adjacent second metal layers do not overlap, the two adjacent second metal layers are shifted and misaligned, the projection pattern of the first metal layer on the substrate is a closed ring, and the projection pattern of the second metal layer on the substrate constitutes an intermittent ring.

2. The semiconductor structure according to claim 1, wherein: The second metal structure includes a plurality of second metal layers. In a direction parallel to the substrate surface, the plurality of second metal layers are concentrically distributed with the device region as the center.

3. The semiconductor structure according to claim 2, wherein: There are multiple first metal layers. In a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed with the device area as the center. The first metal layer and the second metal layer are overlapped and arranged in a direction perpendicular to the substrate surface.

4. The semiconductor structure according to claim 1, wherein: There are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device area.

5. The semiconductor structure according to claim 1, wherein: The closed ring has a first width, and the discontinuous ring has a second width; the first width is greater than the second width, or the first width is less than the second width.

6. The semiconductor structure according to claim 1, wherein: The guard ring structure also includes: a plurality of third metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers located on the third metal layers, the projection pattern of the third metal layer on the substrate is a closed ring, and the projection pattern of the fourth metal layer on the substrate is a closed ring.

7. The semiconductor structure according to claim 1, wherein: The guard ring structure also includes: several layers of fifth metal layers and several layers of sixth metal layers alternately arranged in a direction perpendicular to the substrate surface, any layers of the fifth metal layers are separate from each other, any layers of the sixth metal layers are separate from each other, the center lines of two adjacent layers of the fifth metal layers do not overlap, and the center lines of two adjacent layers of the sixth metal layers do not overlap.

8. The semiconductor structure according to claim 7, wherein: The projection pattern of the fifth metal layer on the substrate forms a discontinuous ring, and the projection pattern of the sixth metal layer on the substrate forms a discontinuous ring.

9. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric structure is located on the substrate, and the guard ring structure is located in the dielectric structure.

10. The semiconductor structure according to claim 1, wherein: The material of the first metal layer includes metal or metal nitride; the material of the second metal layer includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a chip region, the chip region comprising a device region and a scribe line region surrounding the device region; A guard ring structure is formed in the cutting path area, and the guard ring structure surrounds the device area. The guard ring structure includes: a plurality of first metal layers and a second metal structure overlapping in a direction perpendicular to the substrate surface, the second metal structure includes at least one second metal layer, the second metal layer is located between two adjacent first metal layers, any two second metal layers are separated from each other, the center lines of two adjacent second metal layers do not overlap, the two adjacent second metal layers are shifted and misaligned, the projection pattern of the first metal layer on the substrate is a closed ring, and the projection pattern of the second metal layer on the substrate constitutes an intermittent ring.

12. The method for forming a semiconductor structure according to claim 11, wherein: The second metal structure includes a plurality of second metal layers. In a direction parallel to the substrate surface, the plurality of second metal layers are concentrically distributed with the device region as the center.

13. The method for forming a semiconductor structure according to claim 12, wherein: There are multiple first metal layers. In a direction parallel to the substrate surface, the multiple first metal layers are concentrically distributed with the device area as the center. The first metal layer and the second metal layer are overlapped and arranged in a direction perpendicular to the substrate surface.

14. The method for forming a semiconductor structure according to claim 11, wherein: There are multiple guard ring structures, and the multiple guard ring structures are concentrically distributed around the device area.

15. The method for forming a semiconductor structure according to claim 11, wherein: The closed ring has a first width, and the discontinuous ring has a second width; the first width is greater than the second width, or the first width is less than the second width.

16. The method for forming a semiconductor structure according to claim 11, wherein: The guard ring structure also includes: a plurality of third metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of fourth metal layers located on the third metal layers, the projection pattern of the third metal layer on the substrate is a closed ring, and the projection pattern of the fourth metal layer on the substrate is a closed ring.

17. The method for forming a semiconductor structure according to claim 11, wherein: The guard ring structure also includes: a plurality of fifth metal layers alternately arranged in a direction perpendicular to the substrate surface and a plurality of sixth metal layers located on the fifth metal layers, any layer of the fifth metal layers are separate from each other, any layer of the sixth metal layers are separate from each other, the center lines of two adjacent fifth metal layers do not overlap, and the center lines of two adjacent sixth metal layers do not overlap.

18. The method for forming a semiconductor structure according to claim 16, wherein: The first metal layer and the third metal layer are formed simultaneously; the second metal layer and the fourth metal layer are formed simultaneously.

19. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: A dielectric structure is formed on a substrate, and the guard ring structure is located in the dielectric structure.

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