Electronic components

Abstract

The present invention provides an electronic component, which includes a terminal electrode structure that can ensure heat resistance during solder mounting and in the use environment. A chip resistor 10, which includes: an insulating substrate (part body) 1 on which a resistor element 3 is formed; connecting terminals (surface electrodes 2, end electrodes 6, and back electrodes 5) formed at both ends of the insulating substrate 1; a base layer 7 covering the connecting terminals formed by electrolytic plating; a barrier layer 8 covering the base layer 7 formed by electrolytic plating; and an external connection layer 9 with tin as the main component formed on the surface of the barrier layer 8. The barrier layer 8 is formed by an alloy plating containing nickel as the main component and containing 3% to 15% of phosphorus, and the base layer 7 is formed by a copper plating layer having higher ductility and / or ductility than the barrier layer 8.

Description

Technical Field

[0001] The present invention relates to electronic parts such as chip parts and connectors, and in particular to a welding electrode terminal structure formed on a part body of the electronic part. Background Art

[0002] When electronic parts such as chip parts and connectors are mounted on a circuit board, a plating layer containing Sn (tin) or Sn-Pb (lead) is formed on the surface of the connection terminal of the part body of the electronic part as an external connection layer, and this external connection layer is bonded to the pad of the wiring pattern provided on the circuit board using a solder material. For example, in the case of a surface mounted part such as a chip resistor in which an external connection layer to be soldered is formed at both ends of the part body, after applying solder paste (solder material) to the pad of the wiring pattern, the electronic part is placed on the circuit board so that the external connection layer overlaps with the solder paste. In this state, the plating layer of the external connection layer and the solder paste are melted by the heat of the reflow furnace, and then the solder paste is cooled and solidified to connect the connection terminal to the pad. In addition, in the case of a wire part such as a connector in which a needle-shaped connection terminal protruding from the part body is soldered, after the connection terminal is inserted into the through hole of the circuit board, the external connection layer (plating layer) of the connection terminal and the solder material are melted by the heat of a soldering iron, etc., and then the solder material is cooled and solidified to connect the connection terminal to the pad.

[0003] As a solder material used when mounting electronic components on a circuit board, for example, a so-called eutectic solder in which tin (Sn) and lead (Pb) are mixed in a ratio of about 6:4 (Sn 63% - Pb 37%) is known. The melting point of a eutectic solder of this composition is 183°C, but in order to melt the solder, heat above the melting point needs to be applied. Therefore, due to the heat during soldering, Ag or Cu constituting the connection terminal seeps out on the solder material side, which is a phenomenon called "solder corrosion". In order to prevent such solder corrosion, a barrier layer is provided. In the past, an electrode terminal structure has been proposed in which a barrier layer composed of nickel and lead is provided between the connection terminal of the electronic component and the external connection layer to prevent solder corrosion (for example, see Patent Document 1).

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2001-210545 Summary of the invention

[0005] [The problem that the invention aims to solve]

[0006] In recent years, from the perspective of environmental protection, lead-free is recommended, and so-called lead-free solder that contains almost no lead is used. Here, for example, when a lead-free solder with a composition of Sn 96.5%-Ag 3%-Cu 0.5% is used, the melting point of the lead-free solder is 220°C, and the heating temperature during solder mounting becomes higher than when a eutectic solder is used. Therefore, even if the barrier layer is made of nickel, nickel is easily diffused to the solder material side, and the function as a barrier layer cannot be fully exerted. Therefore, it is necessary to thicken the nickel plating layer to delay solder corrosion, but when the plating layer is thickened, not only is it easy to generate cracks due to external stress and internal stress, but the plating time and material cost will also increase.

[0007] In addition, in the automotive industry, technologies such as autonomous driving devices and safety devices have been rapidly developed in recent years, and the number of electronic parts installed has increased dramatically. In addition, electronic parts installed in automobiles require higher reliability than consumer parts. Since the use environment is also harsh, the requirements for high heat resistance are particularly high, and high heat resistance that can be used without problems even in an environment of about 200°C is required. However, when electronic parts are used in a high temperature environment of about 200°C, the nickel plating layer that constitutes the barrier layer diffuses to the surface and cannot function as a barrier layer. That is, the existing electrode terminal structure has the problem of difficulty in ensuring heat resistance not only during solder installation but also in the use environment.

[0008] The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to provide an electronic component having a terminal electrode structure capable of ensuring heat resistance during solder mounting or in a use environment.

[0009] [Methods of solving the problem]

[0010] In order to achieve the above-mentioned purpose, the electronic component of the present invention is characterized in that it includes: a component body, a connecting terminal formed on the aforementioned component body, a base layer formed by electrolytic plating to cover the aforementioned connecting terminal, a barrier layer formed by electrolytic plating to cover the aforementioned base layer, and an external connection layer with tin as the main component formed on the surface of the aforementioned barrier layer, the aforementioned barrier layer is made of an alloy plating layer in which 3% to 15% of phosphorus is added to nickel, and the aforementioned base layer is at least one metal layer that is more ductile and ductile than the aforementioned barrier layer.

[0011] The electronic parts thus manufactured are made of an alloy (Ni-P) plating layer containing 3% to 15% phosphorus (P) and a barrier layer covered by an external connection layer. Since the alloy plating layer diffuses into tin more slowly than nickel, the heat resistance during solder mounting and in the use environment can be ensured even if the barrier layer is not formed unnecessarily thick. Moreover, the base layer as the barrier layer forms a metal layer with more malleability or ductility than the barrier layer. Even if the internal stress increases due to the addition of phosphorus to nickel, the stress is relieved by the base layer, thereby suppressing the occurrence of cracks.

[0012] In the electronic component constructed as described above, the base layer may be at least one metal layer having greater ductility and malleability than the barrier layer, and may be gold, silver, platinum, or alloys thereof as main components, but is preferably copper or an alloy thereof as main component due to its cost advantage.

[0013] In the electronic component having the above structure, if the base layer is too thin, the stress relaxation effect cannot be fully exerted. On the contrary, if the base layer is too thick, the cost productivity decreases. Therefore, the base layer is preferably 3 μm to 25 μm thick.

[0014] In addition, in the electronic components constructed as described above, when a magnetic layer is formed between the connecting terminals and the barrier layer, the magnetic properties of the magnetic layer are utilized. For example, when the product is packaged in a strip-shaped packaging body during a wrapping process, or when the product is taken out of the packaging body and installed on a circuit board, it is possible to stabilize the position of the product through magnetism.

[0015] [Effects of the invention]

[0016] According to the electronic component of the present invention, it is possible to realize a terminal electrode structure capable of ensuring heat resistance during solder mounting or in a use environment, while suppressing the occurrence of cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A cross-sectional view of a chip resistor according to a first embodiment of the present invention;

[0018] Figure 2 A cross-sectional view showing the manufacturing process of the chip resistor;

[0019] Figure 3 A cross-sectional view of a chip resistor according to a second embodiment of the present invention;

[0020] Figure 4 A cross-sectional view showing the manufacturing process of the chip resistor.

[0021] Description of reference numerals:

[0022] 1 Insulating substrate (part body)

[0023] 2 Surface electrode (connection terminal)

[0024] 3 Resistor

[0025] 4. Protective layer

[0026] 4a Base coat

[0027] 4b Outer coating

[0028] 5 Back electrode (connection terminal)

[0029] 6 End electrode (connection terminal)

[0030] 7 Basal layer

[0031] 8 barrier layer

[0032] 9 External connection layer

[0033] 10 Chip resistors (electronic parts)

[0034] 11 Magnetic layer DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view of a chip resistor according to the first embodiment of the present invention.

[0036] like Figure 1 As shown, a chip resistor 10 as an example of an electronic component is mainly composed of the following: an insulating substrate 1 in a rectangular shape, a pair of surface electrodes 2 formed on the two ends of the long side direction of the surface of the insulating substrate 1, a resistor element 3 formed in a manner of bridging the pair of surface electrodes 2, a protective layer 4 covering the entire resistor element 3 and a portion of the surface electrodes 2, a pair of back electrodes 5 formed on the two end surfaces in the long side direction of the back side of the insulating substrate 1, a pair of end surface electrodes 6 formed between the corresponding surface electrodes 2 and the back electrodes 5 on the two end surfaces in the long side direction of the insulating substrate 1, a pair of base layers 7 covering these surface electrodes 2 and the back electrodes 5 and the end surface electrodes 6, a pair of barrier layers 8 covering each base layer 7, and a pair of external connection layers 9 covering each barrier layer 8.

[0037] The insulating substrate 1 is a component body made of ceramic or the like, and is obtained by dividing a large-format substrate described later along vertical and horizontal dividing grooves into a plurality of insulating substrates.

[0038] A pair of front electrodes 2 are formed on the opposite short sides of the insulating substrate 1 at a predetermined interval. The front electrodes 2 are obtained by screen-printing Ag-based paste, followed by drying and firing.

[0039] The resistor element 3 is obtained by screen printing a resistor paste such as ruthenium oxide, drying and firing, and both ends of the resistor element 3 overlap with the surface electrodes 2. In addition, a trimming groove (not shown) is formed in the resistor element 3, and the resistance value of the resistor element 3 is adjusted by the trimming groove.

[0040] The protective layer 4 has a two-layer structure including a primer layer 4a and an outer coating layer 4b. The primer layer 4a is obtained by screen printing a glass paste and then firing it. The primer layer 4a is formed in a manner to cover the resistor element 3 before forming the trimming groove. The outer coating layer 4b is obtained by screen printing an epoxy resin paste and then heating and curing it. After forming the trimming groove on the resistor element 3 from above the primer layer 4a, the outer coating layer 4b is formed in a manner to cover the resistor element 3 and the primer layer 4a as a whole, including the trimming groove.

[0041] A pair of back electrodes 5 are formed at predetermined intervals on the back surface of the insulating substrate 1 at positions corresponding to the front electrodes 2 . The back electrodes 5 are obtained by screen-printing Ag paste, followed by drying and firing.

[0042] A pair of end surface electrodes 6 is obtained by sputtering Ni-Cr on the end surface of the insulating substrate 1 or applying an Ag-based paste on the end surface of the insulating substrate 1 and then heating and hardening. The end surface electrodes 6 are formed in a manner that conducts between the corresponding surface electrodes 2 and the back electrodes 5, and the surface electrodes 2, the end surface electrodes 6, and the back electrodes 5 form a connecting terminal with a U-shaped cross section.

[0043] A pair of base layers 7 is a copper plating layer formed by electrolytic plating to cover the connection terminal. The base layer 7 reduces the internal stress generated by the electroplating formation of the barrier layer 8 in the subsequent process. Here, if the film thickness of the base layer 7 is insufficient, the stress relaxation effect cannot be fully exerted. On the contrary, if the film thickness of the base layer 7 is too thick, the cost and productivity are reduced. The base layer 7 is set in the range of 3μm to 25μm. These base layers 7 can be any metal layer rich in at least one metal with higher ductility and ductility than the barrier layer 8, and can be gold, silver, platinum, or alloys thereof as the main component. In this embodiment, copper or an alloy thereof as the main component is used because it is more cost-effective than these metals.

[0044] The pair of barrier layers 8 is an alloy plating layer (Ni-P plating layer) with nickel (Ni) as the main component and phosphorus (P) formed by electrolytic plating in a manner covering the base layer 7, and its thickness is set to a range of 2μm to 15μm. Here, the alloy plating layer constituting the barrier layer 8, the more phosphorus content contained in nickel, the more it can inhibit diffusion to the tin plating layer constituting the external connection layer 9. If the phosphorus content contained in nickel is insufficient, the diffusion prevention effect cannot be fully exerted. However, if the phosphorus content is too high, even in the base layer 7, the internal stress will become too high and cannot be relaxed, so the phosphorus content in the barrier layer 8 is set to be in the range of 3% to 15% relative to nickel.

[0045] The pair of external connection layers 9 are tin (Sn) plated layers formed by electrolytic plating so as to cover the barrier layer 8 , and the thickness thereof is set in the range of 2 μm to 15 μm.

[0046] Next, for the manufacturing method of the chip resistor 10 constructed as described above, see Figure 2 The cross-sectional view shown is used for explanation.

[0047] First, a large-format substrate from which a plurality of insulating substrates 1 can be obtained is prepared. The large-format substrate is preliminarily provided with grid-like primary dividing grooves and secondary dividing grooves, and each square separated by the two dividing grooves becomes a chip area. Figure 2 Although a large-format substrate 10A corresponding to one chip region is shown as a representative example, each process described below is actually performed commonly on large-format substrates corresponding to a plurality of chip regions.

[0048] That is, Figure 2 As shown in (a), Ag-Pd paste is screen-printed and dried on the surface of the large-format substrate 10A, and a pair of surface electrodes 2 are formed with a predetermined interval at both ends of the long side direction of each chip forming area. In addition, at the same time or before and after, Ag paste is screen-printed and dried on the back side of the large-format substrate 10A, and a pair of back electrodes 5 are formed with a predetermined interval at both ends of the long side direction of each chip forming area.

[0049] Then, if Figure 2As shown in (b), a resistor paste containing ruthenium oxide or the like is screen-printed on the surface of a large-format substrate 10A and dried to form a resistor element 3 with both ends overlapping the surface electrode 2, which is then fired at a high temperature of about 850°C. Next, a glass paste is screen-printed on the area covering the resistor element 3 and dried to form a primer layer 4a covering the resistor element 3, which is then fired at a temperature of about 600°C. Next, a laser beam is irradiated from above the primer layer 4a to form a trimming groove (not shown) on the resistor element 3 to adjust the resistance value. Then, an epoxy resin paste is screen-printed from above the primer layer 4a, and is heated and hardened at a temperature of about 200°C to form an outer coating layer 4b, thereby forming a protective layer 4 having a two-layer structure including the primer layer 4a and the outer coating layer 4b.

[0050] Next, the large-format substrate 10A is divided into long strip substrates 10B along the main dividing grooves, and Ni / Cr is sputtered on the dividing surfaces of the long strip substrates 10B. Figure 2 As shown in (c), an end surface electrode 6 is formed to connect the front electrode 2 and the back electrode 5 provided on the front and back surfaces of the long strip substrate 10B. In addition, instead of sputtering Ni / Cr on the dividing surface of the long strip substrate 10B, the end surface electrode 6 can also be formed by applying an Ag-based paste and hardening it by heating.

[0051] Next, the strip-shaped substrate 10B is subdivided into a plurality of chip-shaped substrates 10C along the subdividing grooves, and then electrolytic plating is applied to the chip-shaped substrates 10C. Figure 2 As shown in (d), a base layer 7 covering the connection terminals (the surface electrode 2, the end surface electrode 6 and the back electrode 5) is formed at both ends of the chip-like substrate 10C. The base layer 7 is made of copper plating, and its film thickness is set to a range of 3μm to 25μm (10μm in this embodiment).

[0052] Next, by applying electrolytic plating to the chip-like substrate 10C, as Figure 2 As shown in (e), a barrier layer 8 covering the base layer 7 is formed. The barrier layer 8 is made of an alloy plating layer (Ni-P plating layer) containing nickel (Ni) as a main component and phosphorus (P), and its thickness is set to a range of 2μm to 15μm (5μm in this embodiment). The content of phosphorus relative to nickel in the barrier layer 8 is set to a range of 3% to 15% (5% in this embodiment), and even if internal stress is generated by adding phosphorus to nickel, the stress is alleviated by the base layer 7.

[0053] Next, by applying electrolytic plating to the chip-like substrate 10C, as Figure 2As shown in (f), an external connection layer 9 is formed to cover the surface of the barrier layer 8. The external connection layer 9 is a Sn plating layer with tin (Sn) as the main component, and its thickness is set to a range of 2μm to 15μm. In this way, a terminal electrode structure with excellent heat resistance characteristics including the barrier layer 8, the external connection layer 9, etc. is formed, and the Figure 1 The chip resistor 10 is shown.

[0054] As described above, in the chip resistor 10 involved in the first embodiment, the barrier layer 8 covered with the external connection layer 9 made of tin plating is made of an alloy (Ni-P) plating containing nickel (Ni) as the main component and 3% to 15% phosphorus (P). Since the alloy plating diffuses into tin more slowly than nickel, even if a thick barrier layer 8 is formed in vain, heat resistance can be ensured during solder installation or in the use environment. In addition, since the base layer 7 as the barrier layer 8 is formed of copper plating by electrolytic plating, even if the internal stress increases with the addition of phosphorus to nickel, the stress is relieved by the base layer 7, and cracks caused by the internal stress can be suppressed.

[0055] In addition, since these base layer 7, barrier layer 8, and external connection layer 9 are formed by electrolytic plating, each is formed by a dense film and can maximize the characteristics of each (stress relief, barrier function, weldability). Since a series of electroplating can be carried out, corrosion due to the environment between the electroplating processes for forming each layer can be prevented as much as possible, while ensuring the adhesion and productivity at the boundaries of each layer.

[0056] Figure 3 This is a cross-sectional view of a chip resistor 20 according to a second embodiment of the present invention. The chip resistor 20 according to the second embodiment is different from the chip resistor 10 according to the first embodiment in that a magnetic layer 11 is formed between the connecting terminals (the surface electrode 2, the end electrode 6, and the back electrode 5) and the barrier layer 8, and the other structures are basically the same.

[0057] That is, Figure 3 As shown, the chip resistor 20 is mainly composed of the following: an insulating substrate 1 of a rectangular shape, a pair of surface electrodes 2 formed on the two end portions of the surface of the insulating substrate 1 in the long side direction, a resistor element 3 formed in a manner of bridging the pair of surface electrodes 2, a protective layer 4 covering the entire resistor element 3 and a portion of the surface electrodes 2, a pair of back electrodes 5 formed on the two end portions in the long side direction of the back side of the insulating substrate 1, a pair of end surface electrodes 6 formed on the two end surfaces in the long side direction of the insulating substrate 1 and conducting between the corresponding surface electrodes 2 and the back electrodes 5, a pair of magnetic layers 11 covering these surface electrodes 2, the back electrodes 5 and the end surface electrodes 6, a pair of base layers 7 covering each magnetic layer 11, a pair of barrier layers 8 covering each base layer 7, and a pair of external connection layers 9 covering each barrier layer 8.

[0058] The pair of magnetic layers 11 are nickel (Ni) plating layers formed by electrolytic plating in a manner covering the connection terminals, and the thickness thereof is set to a range of 2 μm to 15 μm. The magnetic layer 11 can be formed between the base layer 7 and the barrier layer 8 by increasing the magnetic properties of the barrier layer 8 which is reduced by adding phosphorus to nickel. In addition, since the configuration other than the magnetic layer 11 is the same as that of the first embodiment, by attaching the same Figure 1 The same symbols will be omitted here for repeated explanation.

[0059] Next, for the manufacturing method of the chip resistor 20 constructed as described above, see Figure 4 In addition, Figure 4 The manufacturing process shown, Figure 4 (a) Corresponding to the first embodiment Figure 2 (c) The steps up to this point are the same as those in the first embodiment.

[0060] That is, after forming the front electrode 2, the resistor element 3, the protective layer 4 (undercoat layer 4a and outer coat layer 4b), and the back electrode 5 on the large-format substrate (not shown in the figure), the long strip substrate 10B obtained by main-dividing the large-format substrate is formed by sputtering Ni / Cr on the divided surface, such as Figure 4 As shown in (a), the end surface electrodes 6 are formed to connect the front electrodes 2 and the back electrodes 5 provided on both the front and back surfaces of the long-sized substrate 10B.

[0061] Next, the strip-shaped substrate 10B is subdivided into a plurality of chip-shaped substrates 10C along the subdividing grooves, and then electrolytic plating is applied to the chip-shaped substrates 10C. Figure 4 As shown in (b), a magnetic layer 11 covering the connection terminals (the surface electrode 2, the end surface electrode 6 and the back electrode 5) is formed at both ends of the chip-like substrate 10C. The magnetic layer 11 is made of nickel (Ni) plating, and its thickness is set to a range of 2μm to 15μm (5μm in this embodiment).

[0062] Next, by applying electrolytic plating to the chip-like substrate 10C, as Figure 4 As shown in (c), base layer 7 is formed at both ends of chip substrate 10C to cover magnetic layer 11. Base layer 7 is made of copper plating, and its film thickness is set to a range of 3 μm to 25 μm (10 μm in this embodiment).

[0063] Next, by applying electrolytic plating to the chip-like substrate 10C, as Figure 4As shown in (d), a barrier layer 8 covering the base layer 7 is formed. The barrier layer 8 is made of an alloy plating layer (Ni-P plating layer) containing nickel (Ni) as a main component and phosphorus (P), and its thickness is set to a range of 2μm to 15μm (5μm in this embodiment). In addition, the content ratio of phosphorus to nickel in the barrier layer 8 is set to a range of 3% to 15% (5% in this embodiment).

[0064] Next, by applying electrolytic plating to the chip-like substrate 10C, as Figure 4 As shown in (e), an external connection layer 9 is formed to cover the surface of the barrier layer 8. The external connection layer 9 is a Sn plating layer with tin (Sn) as the main component, and its thickness is set in the range of 2μm to 15μm. Thus, a terminal electrode structure with excellent heat resistance characteristics including the barrier layer 8, the external connection layer 9, etc. is formed, and the Figure 3 The chip resistor 20 is shown.

[0065] As described above, in the chip resistor 20 involved in the second embodiment, since a magnetic layer 11 made of a nickel-plated layer is formed between the connecting terminals (the surface electrodes 2, the end electrodes 6 and the back electrodes 5) and the barrier layer 8, the magnetic properties of the magnetic layer 11 can be utilized to stabilize the position of the product by magnetism, for example, during the tape wrapping process of storing the product in a strip-shaped packaging body, or when the product is taken out of the packaging body and installed on a circuit board.

[0066] In the chip resistor 20 according to the second embodiment, the magnetic layer 11 is formed between the connection terminal (the surface electrode 2, the end electrode 6, and the back electrode 5) and the base layer 7, but there is no problem if the magnetic layer 11 is formed between the connection terminal and the barrier layer 8. That is, the magnetic layer 11 may be formed between the base layer 7 and the barrier layer 8, or the magnetic layer 11 may be formed both between the connection terminal and the base layer 7 and between the base layer 7 and the barrier layer 8.

[0067] In addition, in the above-mentioned embodiments, the case where the present invention is applied to a chip resistor as an example of a surface mounted component is described, but the present invention may also be applicable to electronic components other than chip resistors, for example, wire components having needle-shaped connecting terminals such as connectors.

Claims

1. An electronic component, characterized in that: include: A part body, connecting terminals formed on the part body, a base layer formed by electrolytic plating to cover the connecting terminals, a barrier layer formed by electrolytic plating to cover the base layer, and an external connection layer with tin as the main component formed on the surface of the barrier layer, wherein the barrier layer is made of an alloy plating layer in which 3% to 15% of phosphorus is added to nickel, and the base layer is made of copper or an alloy with copper as the main component, and the film thickness of the base layer is 3μm to 25μm.

2. The electronic component according to claim 1, characterized in that: A magnetic layer is formed between the connection terminal and the barrier layer.

Images