Circuit board and method for manufacturing the same
By burying the second circuit layer and the third circuit layer on the surface on the circuit board, the problem of large circuit board thickness is solved, and a thinner circuit board design and a more efficient production process are realized.
Patent Information
- Application Number
- CN202110460666.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-04-27
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2041-04-27
AI Technical Summary
The existing circuit boards are large in thickness and have low space utilization, making it difficult to meet the requirements of lightness, shortness and multifunctionality.
Using a manufacturing method, it includes forming an insulating layer and a first metal layer on the circuit substrate, etching to form a line pattern and opening a line groove, burying the second line layer, and forming a third line layer on the surface of the insulating layer, through plasma etching and electroplating processes avoid adding additional insulation, simplifying the process and reducing costs.
The overall thickness of the circuit board is reduced, the space utilization is improved, the circuit board is thinner, and the circuit board is simplified. The circuit production process is reduced, and the cost is reduced.
Smart Images
Figure CN115250583B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to printed circuit board technology, and in particular to a circuit board and a manufacturing method thereof. Background Art
[0002] With the development trend of electronic equipment becoming more multifunctional, thinner and smaller, the design of circuit boards must meet both the requirements of being thinner and smaller and the requirements of being multifunctional.
[0003] However, most of the existing circuit boards are relatively thick and large in size. Due to the existence of the insulating layer, the distance between each circuit layer along the thickness direction of the circuit board is large, and the space utilization rate of the circuit board is low, making it difficult to meet the above requirements. Summary of the invention
[0004] In view of the above, in order to solve at least one of the above defects, it is necessary to propose a method for manufacturing a circuit board.
[0005] In addition, the present invention also provides a circuit board manufactured by the above manufacturing method.
[0006] The present invention provides a method for manufacturing a circuit board, comprising the following steps:
[0007] A circuit substrate is provided, comprising a base layer and a first circuit layer arranged on at least one surface of the base layer.
[0008] An insulating layer and a first metal layer are formed on the surface of the first circuit layer.
[0009] The first metal layer is etched to form a circuit pattern, wherein the circuit pattern is provided with a circuit opening for exposing a portion of the insulating layer.
[0010] A circuit groove is opened in the insulating layer exposed to the circuit opening.
[0011] A second circuit layer is formed by electroplating in the circuit groove, and electroplating is performed at least in the circuit opening, so as to form a second metal layer together with the circuit pattern.
[0012] And, the second metal layer is etched to form a third circuit layer, thereby obtaining the circuit board.
[0013] In the implementation manner of the present application, along the extension direction of the circuit board, the size of the circuit groove is smaller than or equal to the size of the circuit opening.
[0014] In the implementation manner of the present application, the circuit groove is formed by a plasma etching process.
[0015] In the implementation manner of the present application, the electroplating at least in the circuit opening specifically includes:
[0016] Electroplating is performed in the circuit opening and on the surface of the circuit pattern.
[0017] In an embodiment of the present application, along the thickness direction of the circuit board, the projection of the second circuit layer on the third circuit layer is partially located in the circuit gap of the third circuit layer, and the second circuit layer is electrically connected to the third circuit layer; or, along the thickness direction of the circuit board, the projection of the second circuit layer on the third circuit layer is entirely located in the circuit gap of the third circuit layer, and the second circuit layer is not conductive with the third circuit layer.
[0018] In the embodiment of the present application, the line width of the second circuit layer is 10 μm, and the line spacing is 10 μm. The line width of the third circuit layer is 30 μm, and the line spacing is 30 μm.
[0019] In the implementation manner of the present application, along the thickness direction of the circuit board, the circuit groove penetrates the insulating layer, and the second circuit layer contacts and is electrically connected to the first circuit layer.
[0020] The present invention also provides a circuit board, which includes: a circuit substrate, an insulating layer, a circuit groove, a second circuit layer and a third circuit layer. The circuit substrate includes a base layer and a first circuit layer provided on at least one surface of the base layer; the insulating layer is provided on the surface of the first circuit layer and in the circuit gap of the first circuit layer; the circuit groove is provided in the insulating layer, and the opening of the circuit groove is located on the surface of the insulating layer away from the first circuit layer; the second circuit layer is provided in the circuit groove and exposed by the opening; the third circuit layer is provided at least on the surface of the insulating layer.
[0021] In the implementation manner of the present application, along the thickness direction of the circuit board, a projection of the second circuit layer on the third circuit layer is partially or entirely located within the circuit gap of the third circuit layer.
[0022] In the embodiment of the present application, the line width of the second circuit layer is 10 μm, and the line spacing is 10 μm. The line width of the third circuit layer is 30 μm, and the line spacing is 30 μm.
[0023] In the implementation manner of the present application, along the thickness direction of the circuit board, the circuit groove penetrates the insulating layer, and the second circuit layer contacts and is electrically connected to the first circuit layer.
[0024] Compared with the prior art, the circuit board manufacturing method provided by the present invention produces two types of circuits, namely a buried second circuit layer and a third circuit layer located on the surface of the insulating layer, in the same insulating layer, and avoids adding another insulating layer between the two circuit layers. The manufacturing process is simpler, the efficiency of circuit board circuit manufacturing is improved, the cost is lower, and it is beneficial to reduce the overall thickness of the circuit board, making the circuit board thinner. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of a copper clad laminate provided in accordance with one embodiment of the present invention.
[0026] Figure 2 For Figure 1 A schematic diagram of forming a first circuit layer on a copper clad laminate is shown.
[0027] Figure 3 For Figure 2 The schematic diagram of the first circuit layer surface being laminated with an insulating layer and a first metal layer is shown.
[0028] Figure 4 For the general Figure 3 A schematic diagram of a circuit pattern formed in the first metal layer is shown.
[0029] Figure 5 For Figure 4 A schematic diagram of forming a circuit groove in an insulating layer is shown.
[0030] Figure 6 For Figure 5 A schematic diagram of forming a second circuit layer and a second metal layer in the circuit groove is shown.
[0031] Figure 7 In another embodiment, Figure 5 A schematic diagram of forming a second circuit layer and a second metal layer in the circuit groove is shown.
[0032] Figure 8 For the general Figure 6 The schematic diagram shows that the second metal layer is etched into the third circuit layer.
[0033] Main component symbols
[0034] Circuit board 100
[0035] Copper clad laminate 10
[0036] Circuit board 20
[0037] Base 11
[0038] Copper foil layer 12
[0039] First circuit layer 13
[0040] Single-sided copper clad laminate 30
[0041] Insulation layer 2
[0042] Line slot 21
[0043] Opening 22
[0044] First metal layer 3
[0045] Line Graphic 31
[0046] Line opening 32
[0047] Second circuit layer 4
[0048] Electroplating layer 5
[0049] Second metal layer 6
[0050] The third circuit layer 7
[0051] Dimensions a, b
[0052] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0053] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0055] An embodiment of the present invention provides a method for manufacturing a circuit board 100, the method specifically comprising the following steps:
[0056] Step S11, see Figure 1 , a copper clad laminate 10 is provided, wherein the copper clad laminate 10 includes a base layer 11 and a copper foil layer 12 disposed on at least one surface of the base layer 11.
[0057] In this embodiment, the copper clad laminate 10 can be a single-sided copper clad laminate or a double-sided copper clad laminate. Specifically, the copper clad laminate 10 is a double-sided copper clad laminate, and a copper foil layer 12 is provided on both opposite surfaces of the base layer 11 .
[0058] In this embodiment, the material of the base layer 11 is an insulating resin. Specifically, the material of the base layer 11 can be selected from one of the resins such as epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).
[0059] Step S12, see Figure 2 , the copper foil layer 12 is etched to form a first circuit layer 13 , thereby obtaining a circuit substrate 20 .
[0060] In this embodiment, the first circuit layer 13 is manufactured through processes such as lamination, exposure, development, etching, and film stripping.
[0061] Step S13, see Figure 3 , an insulating layer 2 and a first metal layer 3 are formed on the surface of the first circuit layer 13 .
[0062] In this embodiment, a single-sided copper clad laminate 30 is laminated on the surface of the first circuit layer 13, and the single-sided copper clad laminate includes the insulating layer 2 and the first metal layer 3, and the insulating layer 2 is arranged between the first metal layer 3 and the first circuit layer 13. The insulating layer 2 is also filled in the circuit gap of the first circuit layer 13 after lamination.
[0063] In this embodiment, the thickness of the first metal layer 3 is approximately 3 μm.
[0064] In this embodiment, the material of the insulating layer 2 is insulating resin. Specifically, the material of the insulating layer 2 can be selected from one of resins such as epoxy resin, prepreg (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).
[0065] Step S14, see Figure 4 , etching the first metal layer 3 to form a circuit pattern 31 , wherein the circuit pattern 31 is provided with a circuit opening 32 for exposing a portion of the insulating layer 2 .
[0066] In this embodiment, the first metal layer 3 is made into the circuit pattern 31 by a chemical etching process.
[0067] Step S15, see Figure 5 , a circuit groove 21 is opened in the insulating layer 2 exposed to the circuit opening 32 .
[0068] In this embodiment, along the extension direction of the circuit board 100 , the dimension a of the circuit groove 21 is equal to the dimension b of the circuit opening 32 . In other embodiments, the dimension a of the circuit groove 21 may also be smaller than the dimension b of the circuit opening 32 .
[0069] In this embodiment, the insulating layer 2 is etched by a plasma etching process to form the line groove 21. The plasma etching process is to achieve the purpose of etching the insulating layer 2 by exciting active components so that the active components react chemically with the surface of the insulating layer 2 and form volatile reaction products. By selecting active components, only active components that react chemically with the insulating layer 2 can be selected, so that the insulating layer 2 corresponding to the line opening 32 can be etched quickly and accurately, and the size a of the line groove 21 formed by etching is easier to control.
[0070] Step S16, see Figure 6 , electroplating is performed in the circuit groove 21 to form a second circuit layer 4, and electroplating is performed at least in the circuit opening 32 to form a plating layer 5, and the plating layer 5 and the circuit pattern 31 together form a second metal layer 6.
[0071] In this embodiment, the second circuit layer 4 and the second metal layer 6 are formed by one-time electroplating. That is, the second circuit layer 4 and the second metal layer 6 are an integral structure. The line width of the second circuit layer 4 is 10μm, and the line spacing of the second circuit layer 4 is 10μm. The second circuit layer 4 is made by an embedded trace process (ET). The ET process completes the embedded trace process of the second circuit layer 4 by electroplating copper in the circuit groove 21. The single-layer line width is about 8μm and the line spacing is about 8μm. The embedded second circuit layer 4 made by the embedded trace process has better circuit conductivity, no copper teeth, and the circuit is close to a square, without side corrosion or residual feet.
[0072] See also Figure 7 In another embodiment, when electroplating is performed in the circuit opening 32, the electroplated layer 5 extends to the surface of the circuit pattern 31, thereby forming the second metal layer 6 together with the circuit pattern 31. Therefore, the thickening of the circuit pattern 31 by electroplating is beneficial to improving the surface flatness of the copper layer, and is also beneficial to the bonding strength and integration of the electroplated layer 5 and the circuit pattern 31.
[0073] In this embodiment, whether the second circuit layer 4 and the first circuit layer 13 are conductive can be designed according to actual needs. If conductiveness is required, the circuit groove 21 can be set through the insulating layer 2 to enable the second circuit layer 4 and the first circuit layer 13 to be electrically connected.
[0074] Step S17, see Figure 8 , etching the second metal layer 6 to form a third circuit layer 7.
[0075] In this embodiment, the line width of the third circuit layer 7 is 30 μm and the line spacing of the third circuit layer 7 is 30 μm.
[0076] In this embodiment, the third circuit layer 7 is made by a modified semi-additive process (MSAP), and the third circuit layer 7 is made by lamination, exposure, development, etching, de-filming and other processes. The advantages of the MSAP process are: the circuit thickness is reduced, the line type is easy to control, the top width and bottom width of the line of the entire production board are almost the same, the crosstalk is low, the signal-to-noise ratio is high, and the signal integrity is improved. Moreover, the MSAP process can make circuits on a 3μm copper layer, so after the second circuit layer 4 is made, copper can be directly plated on the basis of the circuit pattern 31 to further realize the production of the third circuit layer 7. Therefore, the second circuit layer 4 (i.e., ET circuit) made by the ET process and the third circuit layer 7 (i.e., MSAP circuit) made by the MSAP process can be made on the insulating layer 2 at the same time, avoiding the cumbersome process in the traditional layer-adding process that requires another insulating layer and copper foil layer to be stacked and the copper foil layer to be etched to make another circuit layer (i.e., an insulating layer is also provided between different circuit layers). This helps to simplify the process and reduce costs, and because an insulating layer is omitted, it helps to reduce the overall thickness of the circuit board.
[0077] In this embodiment, the second circuit layer 4 and the third circuit layer 7 can be made into a conductive or non-conductive structure according to actual needs. If the second circuit layer 4 and the third circuit layer 7 need to be electrically connected, when manufacturing the third circuit layer 7, along the thickness direction of the circuit substrate 20, the projection of the second circuit layer 4 on the third circuit layer 7 is located within the circuit gap of the third circuit layer 7, so that part of the third circuit layer 7 overlaps with the second circuit layer 4 to achieve electrical connection between the two. In this case, there is no need to use a blind hole alone to achieve conduction, the manufacturing process is simpler, the efficiency of circuit manufacturing is improved, and the cost is lower.
[0078] In another embodiment, if the second circuit layer 4 does not need to be connected to the third circuit layer 7, the third circuit layer 7 can be formed on the surface of the insulating layer 2 and not in contact with the second circuit layer 4 when the third circuit layer 7 is manufactured. In this case, along the thickness direction of the circuit substrate 20, the projection of the second circuit layer 4 on the third circuit layer 7 is completely located within the circuit gap of the third circuit layer 7.
[0079] Step S18 , performing surface treatment on the third circuit layer 7 , thereby obtaining the circuit board 100 .
[0080] In this embodiment, the surface treatment includes but is not limited to solder mask treatment and chemical nickel plating or chemical gold plating in the welding area.
[0081] The present application combines the ET process with the MSAP process, and can be simultaneously produced on the insulating layer 2, avoiding the cumbersome process in the traditional layer-building process that requires stacking another insulating layer and a copper foil layer and etching the copper foil layer to produce another circuit layer (i.e., an insulating layer is provided between different circuit layers). This is conducive to simplifying the process and reducing costs, and because an insulating layer is omitted, it is conducive to reducing the overall thickness of the circuit board.
[0082] See also Figure 8 The present invention also provides a circuit board 100 manufactured by the above manufacturing method, wherein the circuit board 100 comprises the circuit substrate 20, an insulating layer 2, a circuit groove 21, a second circuit layer 4 and a third circuit layer 7. The circuit substrate 20 comprises a base layer 11 and a first circuit layer 13 disposed on at least one surface of the base layer 11; the insulating layer 2 is disposed on the surface of the first circuit layer 13 and the circuit gap of the first circuit layer 13; the circuit groove 21 is opened in the insulating layer 2, and the opening 22 of the circuit groove 21 is located on the surface of the insulating layer 2 away from the first circuit layer 13; the second circuit layer 4 is disposed in the circuit groove 21 and exposed by the opening 22; the third circuit layer 7 is disposed at least on the surface of the insulating layer 2.
[0083] In this embodiment, along the thickness direction of the circuit board 100, the projection of the second circuit layer 4 on the third circuit layer 7 is partially or completely located in the circuit gap of the third circuit layer 7. The second circuit layer 4 and the third circuit layer 7 can be made into a conductive or non-conductive structure according to actual needs. If the second circuit layer 4 and the third circuit layer 7 need to be electrically connected, when making the third circuit layer 7, the electrical connection between the two can be achieved by making part of the third circuit layer 7 overlap with the second circuit layer 4. In this case, there is no need to use a blind hole method to achieve conduction, the production process is simpler, the efficiency of circuit production is improved, and the cost is lower.
[0084] In another embodiment, if the second circuit layer 4 does not need to be connected to the third circuit layer 7, when the third circuit layer 7 is manufactured, the third circuit layer 7 can be formed only on the surface of the insulating layer 2 and not in contact with the second circuit layer 4. At this time, along the thickness direction of the circuit board 100, the projection of the second circuit layer 4 on the third circuit layer 7 is all located in the circuit gap of the third circuit layer 7.
[0085] In this embodiment, the line width of the second circuit layer 4 is 10 μm, and the line spacing of the second circuit layer 4 is 10 μm.
[0086] In this embodiment, the line width of the third circuit layer 7 is 30 μm, and the line spacing of the third circuit layer 7 is 30 μm.
[0087] In this embodiment, along the thickness direction of the circuit board 100 , the circuit groove 21 penetrates the insulating layer 2 , and the second circuit layer 4 is in contact with and electrically connected to the first circuit layer 13 .
[0088] In summary, the circuit board manufacturing method provided by the present invention produces two types of circuits, namely, a buried second circuit layer and a third circuit layer located on the surface of the insulating layer, in the same insulating layer, and avoids adding another insulating layer between the two circuit layers. The manufacturing process is simpler, the efficiency of circuit board circuit manufacturing is improved, the cost is lowered, and it is beneficial to reduce the overall thickness of the circuit board, making the circuit board thinner.
Claims
1. A method for manufacturing a circuit board, characterized in that: Includes steps: Providing a circuit substrate, comprising a base layer and a first circuit layer disposed on at least one surface of the base layer; forming an insulating layer and a first metal layer on a surface of the first circuit layer; Etching the first metal layer to form a circuit pattern, wherein the circuit pattern is provided with a circuit opening for exposing a portion of the insulating layer; Opening a circuit groove in the insulating layer exposed to the circuit opening; Electroplating in the circuit groove to form a second circuit layer; Electroplating at least in the circuit opening to form a second metal layer together with the circuit pattern; as well as etching the second metal layer to form a third circuit layer, thereby obtaining the circuit board, Wherein, along the thickness direction of the circuit board, the projections of the second circuit layer on the third circuit layer are all located within the circuit gaps of the third circuit layer, and the second circuit layer is not conductive with the third circuit layer.
2. The method for manufacturing a circuit board according to claim 1, wherein: Along the extension direction of the circuit board, the size of the circuit opening is greater than or equal to the size of the circuit groove.
3. The method for manufacturing a circuit board according to claim 1, wherein: The circuit groove is formed by a plasma etching process.
4. The method for manufacturing a circuit board according to claim 1, wherein: The electroplating at least in the circuit opening specifically includes: Electroplating is performed in the circuit opening and on the surface of the circuit pattern.
5. The method for manufacturing a circuit board according to claim 1, wherein: The line width of the second circuit layer is 10 μm, and the line spacing is 10 μm; The line width of the third circuit layer is 30 μm, and the line spacing is 30 μm.
6. The method for manufacturing a circuit board according to claim 1, wherein: Along the thickness direction of the circuit board, the circuit groove penetrates the insulating layer, and the second circuit layer contacts and is electrically connected to the first circuit layer.
7. A circuit board manufactured by the method for manufacturing a circuit board according to claim 1, characterized in that: include: A circuit substrate comprises a base layer and a first circuit layer disposed on at least one surface of the base layer; An insulating layer, provided on the surface of the first circuit layer and between circuit gaps of the first circuit layer; A circuit groove is provided in the insulating layer, wherein the opening of the circuit groove is located on a surface of the insulating layer away from the first circuit layer; A second circuit layer is disposed in the circuit groove and exposed from the opening; The third circuit layer is arranged on the surface of the insulating layer, and along the thickness direction of the circuit board, the projections of the second circuit layer on the third circuit layer are all located within the circuit gaps of the third circuit layer.
8. The circuit board according to claim 7, characterized in that: The line width of the second circuit layer is 10 μm, and the line spacing is 10 μm; The line width of the third circuit layer is 30 μm, and the line spacing is 30 μm.
9. The circuit board according to claim 7, characterized in that: Along the thickness direction of the circuit board, the circuit groove penetrates the insulating layer, and the second circuit layer contacts and is electrically connected to the first circuit layer.