Display panel and display device

Abstract

The present application provides a display panel and a display device, the display panel includes a display area and a frame area arranged on one side of the display area, the display panel includes: a substrate; a light-shielding metal layer, arranged on one side of the substrate, the light-shielding metal layer includes: a first wiring arranged in the frame area; a driving circuit layer, arranged on the side of the light-shielding metal layer away from the substrate, the driving circuit layer includes: a pixel driving circuit arranged in the display area, and a gate driving circuit arranged in the frame area; a first electrode, arranged on the side of the driving circuit layer away from the substrate; a light-emitting layer, arranged on the side of the first electrode away from the substrate; a second electrode, arranged on the side of the light-emitting layer away from the substrate, the second electrode and the first wiring are electrically connected through a via; wherein the first wiring and the gate driving circuit are at least partially overlapped. The display panel and the display device provided by the present application can narrow the frame width of the display panel and improve the screen-to-body ratio while maintaining a better signal transmission capability of the first wiring.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Compared with liquid crystal displays, organic light-emitting diode (OLED) display panels have the advantages of being lighter, thinner, having better display effects, higher resolution, wider color gamut, lower power consumption, and being able to achieve flexible displays. As a result, they have developed rapidly in recent years and have become the preferred display panel type for mobile terminals.

[0003] Existing OLED display panels generally include a display area for performing display functions and a frame area located on one side of the display area. The frame area needs to be provided with various types of drive circuits and various types of signal wiring, such as a gate drive circuit and a cathode wiring (VSS wiring). At present, in order to reduce the number of masking times and save production costs, when designing the display panel architecture, the cathode wiring that transmits the VSS signal and the gate drive circuit are formed in a film layer-sharing manner. At the same time, in order to ensure the signal transmission quality of the VSS signal in the cathode wiring, the width of the cathode wiring needs to meet certain design requirements. This makes the cathode wiring with a wider width occupy the space of the frame area together with the gate drive circuit, which leads to the problem of a larger width of the frame area of ​​the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device, which can ensure the signal transmission quality of a VSS signal and effectively solve the problem of a large border area width in an existing OLED display panel.

[0005] In one aspect, the present application provides a display panel, the display panel comprising: a display area and a frame area arranged on one side of the display area,

[0006] The display panel comprises:

[0007] substrate;

[0008] A light-shielding metal layer is arranged on one side of the substrate, and the light-shielding metal layer includes: a first wiring arranged in the frame area;

[0009] A driving circuit layer is arranged on a side of the light-shielding metal layer away from the substrate, the driving circuit layer comprising: a pixel driving circuit arranged in the display area, and a gate driving circuit arranged in the frame area, the gate driving circuit being electrically connected to the pixel driving circuit;

[0010] A first electrode is arranged on a side of the driving circuit layer away from the substrate;

[0011] A light-emitting layer is arranged on a side of the first electrode away from the substrate;

[0012] A second electrode is arranged on a side of the light-emitting layer away from the substrate, and the second electrode is electrically connected to the first wiring through a via hole;

[0013] Wherein, the first wiring and the gate driving circuit are at least partially overlapped.

[0014] Optionally, the driving circuit layer includes:

[0015] A semiconductor layer, arranged on a side of the light-shielding metal layer away from the substrate, the semiconductor layer comprising: a first semiconductor corresponding to the pixel driving circuit and a second semiconductor corresponding to the gate driving circuit;

[0016] A first metal layer is arranged on a side of the semiconductor layer away from the substrate, the first metal layer comprising: a first source and a first drain corresponding to the pixel driving circuit, and a second wiring arranged in the frame area;

[0017] The second wiring and the gate driving circuit are arranged without overlapping, and the second wiring is connected in parallel with the first wiring through a via.

[0018] Optionally, the width of the second routing line is smaller than the width of the first routing line.

[0019] Optionally, a vertical projection of the second routing line on the substrate is located within a vertical projection of the first routing line on the substrate.

[0020] Optionally, an edge of the first wiring away from the gate driving circuit is a first edge, an edge of the second wiring away from the gate driving circuit is a second edge, and the first edge is flush with the second edge.

[0021] Optionally, the first routing line includes a first part and a second part, the first part is arranged to overlap with the second routing line, and the second part is arranged to not overlap with the second routing line, wherein the width of the first part is smaller than the width of the second part.

[0022] Optionally, the width of the first part is a first width, the width of the second part is a second width, and the first width is more than 7 times the second width.

[0023] Optionally, the sum of the first width and the second width is greater than 150 μm, and the first width is 10 μm-20 μm.

[0024] Optionally, a vertical projection of the second semiconductor on the substrate is located within a vertical projection of the first routing line on the substrate, wherein the first routing line further includes a plurality of hollow portions, and the hollow portions are arranged non-overlappingly with the second semiconductor.

[0025] On the other hand, the display device comprises a housing and any one of the display panels described above, the housing has a containing space, and the display panel is disposed in the containing space.

[0026] The present application provides a display panel and a display device. The display panel provided by the present application forms a first wiring electrically connected to a second electrode in a border area, and by at least partially overlapping the first wiring with the gate driving circuit, the first wiring can use the space occupied by the gate driving circuit to widen the width, thereby reducing the resistance of the first wiring and improving the signal transmission quality, while allowing the display panel to still maintain a relatively narrow border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic plan view of a first wiring, a second wiring and a gate driving circuit in a display panel provided in an embodiment of the present application;

[0029] Figure 2 The first wiring, the second wiring and the gate driving circuit in the display panel provided in the embodiment of the present application are Figure 1 The enlarged schematic diagram of point B in the middle;

[0030] Figure 3 The display panel of the border area provided in the embodiment of the present application is along the Figure 1 Schematic diagram of the section cut along line AA;

[0031] Figure 4 A cross-sectional schematic diagram of a display panel of a display area provided in an embodiment of the present application;

[0032] Figure 5 A schematic plan view of the first metal layer in the border area provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0034] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the present application provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following is described in detail respectively, and it should be noted that the description order of the following embodiments is not used as a limitation to the preferred order of the embodiments.

[0035] Figure 1 A schematic plan view of a first wiring, a second wiring and a gate driving circuit in a display panel provided in an embodiment of the present application; Figure 2 The first wiring, the second wiring and the gate driving circuit in the display panel provided in the embodiment of the present application are Figure 1 The enlarged schematic diagram of point B in the middle; Figure 3 The display panel of the border area provided in the embodiment of the present application is along the Figure 1 Schematic diagram of the section cut along line AA; Figure 4 This is a cross-sectional schematic diagram of a display panel of a display area provided in an embodiment of the present application. Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, the embodiment of the present application provides a display panel, the display panel includes: a display area 100 and a frame area 201 arranged on one side of the display area 100, the display panel includes: a substrate 10; a light shielding metal layer 105, arranged on one side of the substrate 10, the light shielding metal layer 105 includes: a first wiring 31 arranged in the frame area 201; a driving circuit layer, arranged on a side of the light shielding metal layer 105 away from the substrate 10, the driving circuit layer includes: a pixel driving circuit 01 arranged in the display area 100, and a pixel driving circuit 02 arranged in the frame area 201; a pixel driving circuit 03 arranged in the display area 100, and a pixel driving circuit 04 arranged in the frame area 201; a pixel driving circuit 05 arranged on the display area 100, and a pixel driving circuit 05 arranged in the frame area 201; a pixel driving circuit 06 arranged in the display area 100, and a pixel driving circuit 07 arranged in the frame area 201; a pixel driving circuit 08 arranged in the display area 100, and a pixel driving circuit 09 arranged in the frame area 201; a pixel driving circuit 09 arranged in the display area 100, and a pixel driving circuit 01 arranged in the frame area 201; a pixel driving circuit 08 arranged in the display area 100, and a pixel driving circuit 09 arranged in the frame area 201; a pixel driving circuit 09 arranged in the display area 100, and a pixel driving circuit 09 arranged in the frame area 201; a pixel driving circuit 08 ... The gate driving circuit 02 of the area 201 is electrically connected to the pixel driving circuit 01; the first electrode 1191 is arranged on the side of the driving circuit layer away from the substrate 10; the light-emitting layer 121 is arranged on the side of the first electrode 1191 away from the substrate 10; the second electrode 1221 is arranged on the side of the light-emitting layer 121 away from the substrate 10, and the second electrode 1221 is electrically connected to the first wiring 31 through a via; wherein the first wiring 31 and the gate driving circuit 02 are at least partially overlapped.

[0036] In the display panel provided by the present application, the present application forms a first wiring 31 electrically connected to the second electrode 1221 in the border area 201, and the first wiring 31 is at least partially overlapped with the gate drive circuit 02, so that the first wiring 31 can use the space in the lateral direction x occupied by the gate drive circuit 02 to widen the width, thereby reducing the resistance of the first wiring 31 and allowing the display panel to maintain a relatively narrow border width, thereby improving the screen-to-body ratio of the display panel.

[0037] Specifically, the cathode wiring 30 of the display panel includes the first wiring 31, and the first wiring 31 is used to transmit the VSS signal to the second electrode. By arranging the first wiring 31 to at least partially overlap with the gate drive circuit 02, the width of the first wiring 31 can be greatly increased, and the VSS signal transmission capacity of the cathode wiring 30 can be improved, thereby ensuring the uniformity of the display panel and avoiding uneven display during the display process of the display panel.

[0038] Furthermore, the pixel driving circuit 01 includes: a first thin film transistor arranged on a side of the light-shielding metal layer 105 away from the substrate 10, and the first thin film transistor includes a channel. The light-shielding metal layer 105 also includes: a light-shielding portion 1051 arranged in the display area 100, and the light-shielding portion 1051 is arranged to overlap with the channel of the first thin film transistor, so as to avoid the problem of device performance deterioration caused by ambient light located on a side of the substrate 10 away from the first thin film transistor irradiating the channel. That is, the first wiring 31 and the light-shielding portion 1051 are arranged in the same layer, and due to the need to set the light-shielding portion 1051, the light-shielding metal layer 105 cannot be omitted, so the setting of the first wiring 31 does not increase the film layer structure and the number of masking times of the display panel.

[0039] In some embodiments of the present application, the driving circuit layer includes: a semiconductor layer 108, which is arranged on a side of the shading metal layer 105 away from the substrate 10, and the semiconductor layer 108 includes: a first semiconductor 1081 corresponding to the pixel driving circuit 01 and a second semiconductor 1082 corresponding to the gate driving circuit 02; a first metal layer 114, which is arranged on a side of the semiconductor layer 108 away from the substrate 10, and the first metal layer 114 includes: a first source 1141 and a first drain 1142 corresponding to the pixel driving circuit 01, and a second routing line 32 arranged in the border area 201; wherein the second routing line 32 is not overlapped with the gate driving circuit 02, and the second routing line 32 is connected in parallel with the first routing line 31 through a via.

[0040] For details, please refer to Figure 1 , in the frame area 201, the gate drive circuit 02, the first wiring 31, and the second wiring 32 all extend along the longitudinal direction y, and the first wiring 31 and the second wiring 32 have a continuous wiring structure. Among them, the second wiring 32 is located on the side of the gate drive circuit 02 away from the display area 100, and is at least partially overlapped with the first wiring 31, and the first wiring 31 is connected in parallel with the second wiring 32 through a plurality of vias (not shown in the figure) spaced apart in the longitudinal direction y. That is, the cathode wiring 30 includes the first wiring 31 and the second wiring 32, and because the second wiring 32 is connected in parallel with the first wiring 31, the impedance of the cathode wiring 30 can be further reduced, and the VSS signal transmission capability of the cathode wiring 30 can be further enhanced.

[0041] In some embodiments of the present application, the width of the second wiring 32 is smaller than the width of the first wiring 31 .

[0042] It should be noted that, in the border area 201, the width of the first routing line 31 and the second routing line 32 refers to the extension length of the first routing line 31 and the second routing line 32 in the lateral direction x. Since the second routing line 32 and the gate drive circuit 02 are not arranged to overlap, the second routing line 32 and the gate drive circuit 02 will jointly occupy the space of the border area 201. By making the width of the second routing line 32 smaller than the width of the first routing line 31, the problem of increased border width caused by the arrangement of the second routing line 32 can be reduced or avoided.

[0043] In some embodiments of the present application, a vertical projection of the second wiring 32 on the substrate 10 is located within a vertical projection of the first wiring 31 on the substrate 10 .

[0044] Since the first wiring 31 needs to be electrically connected to the second electrode 1221 by via connection, the first wiring 31 includes a portion that does not overlap with the gate drive circuit 02. The present application makes full use of the space in the lateral direction x occupied by the portion of the first wiring 31 that does not overlap with the gate drive circuit 02 by placing the vertical projection of the second wiring 32 on the substrate 10 within the vertical projection of the first wiring 31 on the substrate 10, thereby avoiding the problem of increased border width caused by the provision of the second wiring 32.

[0045] In some embodiments of the present application, the edge of the first routing line 31 away from the gate driving circuit 02 is a first edge 31A, the edge of the second routing line 32 away from the gate driving circuit 02 is a second edge 32A, and the first edge 31A is flush with the second edge 32A.

[0046] That is, the orthographic projection of the first edge 31A on the substrate 10 and the orthographic projection of the second edge 32A on the substrate 10 are arranged to overlap, and the contour shape of the first edge 31A is consistent with the contour shape of the second edge 32A, so that the second wiring 32 can make full use of the space in the lateral direction x occupied by the non-overlapping part of the first wiring 31 and the gate drive circuit 02, while avoiding the increase in the border width caused by the setting of the second wiring 32, and maximizing the width of the second wiring 32 to further reduce the resistance of the cathode wiring 30.

[0047] In some embodiments of the present application, in the lateral direction x, the width of the second trace 32 is the same as the width of the via connecting the first trace 31 and the second trace 32 , and the first edge 31A is flush with the second edge 32A.

[0048] Since the via connecting the first routing line 31 and the second routing line 32 is a necessary structure for realizing the electrical connection between the first routing line 31 and the second routing line 32, the present application sets the width of the second routing line 32 in the lateral direction x to be the same as the width of the via connecting the first routing line 31 and the second routing line 32, so that the second routing line 32 can maximize the narrowing of the width of the second routing line 32 while utilizing the space in the lateral direction x occupied by the non-overlapping portion of the first routing line 31 and the gate drive circuit 02. In addition, since the first edge 31A is flush with the second edge 32A, the width of the non-overlapping portion of the first routing line 31 and the gate drive circuit 02 can be minimized, thereby further narrowing the width of the border area 201, realizing an ultra-narrow border, and further improving the screen-to-body ratio. As an example, the width of the second routing line 32 is 10μm-20μm, such as 10μm, 13μm, 15μm, 18μm, 20μm, etc.

[0049] Further, continue to refer to Figure 3 The first routing line 31 includes a first portion 311 and a second portion 312, the first portion 311 is overlapped with the second routing line 32, and the second portion 312 is not overlapped with the second routing line 32, wherein the width of the first portion 311 is smaller than the width of the second portion 312.

[0050] Specifically, the second portion 312 is located on the side of the first portion 311 facing the gate drive circuit 02, that is, the portion where the first wiring 31 overlaps with the gate drive circuit 02 belongs to the second portion 312. In the prior art, the gate drive pattern in the gate drive circuit generally includes a wiring pattern and some component patterns in the thin film transistor, and its width in the lateral direction x is generally large. The present application arranges the second portion 312, which accounts for a larger proportion of the first wiring 31, on the side of the first portion 311 facing the gate drive circuit 02, so that the width of the first wiring 31 can be widened as much as possible on the basis of fully utilizing the space occupied by the gate drive circuit 02 in the lateral direction x, thereby further reducing the resistance of the cathode wiring 30 and improving the signal transmission capability of the cathode wiring 30.

[0051] Further, the width of the first portion 311 is a first width, the width of the second portion 312 is a second width, the first width is more than 7 times the second width, and the sum of the first width and the second width is more than 150 μm, and the first width is 10 μm-20 μm.

[0052] In some embodiments of the present application, a vertical projection of the second semiconductor 1082 on the substrate 10 is located within a vertical projection of the first trace 31 on the substrate 10 .

[0053] Specifically, the gate drive circuit 02 includes a second thin film transistor, and the second thin film transistor includes the second semiconductor 1082. The inventor of the present application has found that the charge on the substrate 10 is likely to affect the performance of the second semiconductor 1082, which is likely to cause the characteristics of the second thin film transistor to drift, affecting the working stability of the device. The present application can avoid the charge on the substrate 10 from affecting the performance of the second semiconductor 1082 by overlapping the first wiring 31 with the second semiconductor 1082, thereby improving the working stability of the device. Figure 3 The second thin film transistor shown in the figure is a single-gate thin film transistor. In other embodiments of the present application, the second thin film transistor may also be a dual-gate thin film transistor.

[0054] Furthermore, the first wiring 31 further includes a plurality of hollow portions 310 , and the hollow portions 310 and the second semiconductor 1082 are not overlapped.

[0055] Specifically, the inventors of the present application further discovered that, in circuit design, large-area wiring structures are prone to electrostatic damage or film peeling. In order to avoid the above problems, the present application solves the possible electrostatic damage or film peeling problems by providing a hollow portion 310 on the first wiring 31. In addition, since the hollow portion 310 and the second semiconductor 1082 are not overlapped, the provision of the hollow portion 310 does not affect the performance of the second semiconductor 1082.

[0056] In some embodiments of the present application, the driving circuit layer further includes: a second metal layer 117, which is disposed on a side of the first metal layer 114 away from the substrate 10. The second metal layer 117 includes: a third routing line 33 disposed in the border area 201. The third routing line 33 is not overlapped with the gate driving circuit 02, and the third routing line 33 is connected in parallel with the first routing line 31 through a via.

[0057] In some embodiments of the present application, the cathode wiring 30 includes the first wiring 31, the second wiring 32 and the third wiring 33, wherein the third wiring 33 is arranged in a similar manner to the second wiring 32, and the present application will not repeat it here.

[0058] Combination Figure 3 and Figure 4As shown, in the display panel provided in the present application, the substrate 10 includes: a first substrate layer 101; a substrate barrier layer 102, arranged on the side of the first substrate layer 101 facing the light-shielding metal layer 105; and a second substrate layer 103, arranged on the side of the substrate barrier layer 102 facing the light-shielding metal layer 105.

[0059] The display panel provided in the present application further includes: a first barrier layer 104 disposed on a side of the second substrate layer 103 facing the light shielding metal layer 105. The light shielding metal layer 105 is disposed on a side of the first barrier layer 104 away from the substrate 10.

[0060] The display panel provided in the present application further includes: a second barrier layer 106, which is disposed on the side of the light shielding metal layer 105 facing the driving circuit layer; and a buffer layer 107, which is disposed on the side of the second barrier layer 106 facing the driving circuit layer. The driving circuit layer is disposed on the side of the buffer layer 107 away from the substrate 10.

[0061] In the display panel provided in the present application, the driving circuit layer includes: a semiconductor layer 108, which is arranged on a side of the buffer layer 107 away from the substrate 10; a first gate insulating layer 109, which is arranged on a side of the semiconductor layer 108 away from the substrate 10; a third metal layer 110, which is arranged on a side of the first gate insulating layer 109 away from the substrate 10; a second gate insulating layer 111, which is arranged on a side of the third metal layer 110 away from the substrate 10; a fourth metal layer 112, which is arranged on a side of the second gate insulating layer 111 away from the substrate 10; an interlayer dielectric The fourth metal layer 112 is provided at a side of the substrate 10 away from the first metal layer 113; the first metal layer 114 is provided at a side of the interlayer dielectric layer 113 away from the substrate 10; the passivation layer 115 is provided at a side of the first metal layer 114 away from the substrate 10; the first planarization layer 116 is provided at a side of the passivation layer 115 away from the substrate 10; the second metal layer 117 is provided at a side of the first planarization layer 116 away from the substrate 10; and the second planarization layer 118 is provided at a side of the second metal layer 117 away from the substrate 10.

[0062] In the display panel provided in the present application, the display panel further includes: a first electrode layer 119, which is arranged on a side of the driving circuit layer away from the substrate 10 and includes the first electrode 1191, wherein the first electrode 1191 is, for example, an anode.

[0063] In the display panel provided in the present application, the display panel also includes: a pixel definition layer 120 and the light-emitting layer 121, both of which are arranged on the side of the first electrode layer 119 away from the substrate 10, wherein the pixel definition layer 120 is formed with a pixel definition opening, and the light-emitting layer 121 is accommodated in the pixel definition opening.

[0064] In the display panel provided in the present application, the display panel further includes: a second electrode layer 122, which is arranged on a side of the light-emitting layer 121 away from the substrate 10 and includes the second electrode 1221, wherein the second electrode 1221 is, for example, a cathode.

[0065] Figure 5 This is a schematic plan view of the first metal layer 114 of the border area 201 provided in an embodiment of the present application. Figure 5 The display panel includes a non-display area 200 surrounding the display area 100 , wherein the non-display area 200 includes four frame areas 201 , and the second wiring 32 spans across two adjacent frame areas 201 .

[0066] Specifically, refer to Figure 4 and Figure 5 The second wiring 32 in the non-display area 200 has two different widths, wherein in the direction perpendicular to the substrate 10 , the second wiring 32 with a narrower width is correspondingly provided with a first wiring 31 on one side facing the substrate 10 .

[0067] On the other hand, the present application further provides a display device, the display device comprising a housing and a display panel as described in any one of the above items, the housing having a housing space, the display panel being arranged in the housing space, wherein the display panel comprises: a display area 100 and a frame area 201 arranged on one side of the display area 100, the display panel comprising: a substrate 10; a light-shielding metal layer 105 arranged on one side of the substrate 10, the light-shielding metal layer 105 comprising: a first wiring 31 arranged in the frame area 201; a driving circuit layer arranged on a side of the light-shielding metal layer 105 away from the substrate 10, the driving circuit layer The dynamic circuit layer includes: a pixel driving circuit 01 arranged in the display area 100, and a gate driving circuit 02 arranged in the border area 201, the gate driving circuit 02 is electrically connected to the pixel driving circuit 01; a first electrode, arranged on a side of the driving circuit layer away from the substrate 10; a light-emitting layer 121, arranged on a side of the first electrode away from the substrate 10; a second electrode, arranged on a side of the light-emitting layer 121 away from the substrate 10, the second electrode is electrically connected to the first wiring 31 through a via; wherein the first wiring 31 and the gate driving circuit 02 are at least partially overlapped.

[0068] In summary, the present application provides a display panel and a display device, wherein the display panel includes a display area and a frame area arranged on one side of the display area, and the display panel includes: a substrate; a light-shielding metal layer, arranged on one side of the substrate, the light-shielding metal layer includes: a first wiring arranged in the frame area; a driving circuit layer, arranged on a side of the light-shielding metal layer away from the substrate, the driving circuit layer includes: a pixel driving circuit arranged in the display area, and a gate driving circuit arranged in the frame area; a first electrode, arranged on a side of the driving circuit layer away from the substrate; a light-emitting layer, arranged on a side of the first electrode away from the substrate; a second electrode, arranged on a side of the light-emitting layer away from the substrate, the second electrode and the first wiring are electrically connected through a via; wherein the first wiring and the gate driving circuit are at least partially overlapped. The display panel and the display device provided by the present application can narrow the frame width of the display panel and improve the screen-to-body ratio while maintaining a better signal transmission capability of the first wiring.

[0069] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: a display area and a frame area arranged on one side of the display area. The display panel comprises: substrate; A light-shielding metal layer is arranged on one side of the substrate, and the light-shielding metal layer includes: a first wiring arranged in the frame area; A driving circuit layer is arranged on a side of the light-shielding metal layer away from the substrate, the driving circuit layer comprising: a pixel driving circuit arranged in the display area, and a gate driving circuit arranged in the frame area, the gate driving circuit being electrically connected to the pixel driving circuit; A first electrode is arranged on a side of the driving circuit layer away from the substrate; A light-emitting layer is arranged on a side of the first electrode away from the substrate; A second electrode is arranged on a side of the light-emitting layer away from the substrate, and the second electrode is electrically connected to the first wiring through a via hole; Wherein, the first wiring and the gate driving circuit are at least partially overlapped.

2. The display panel according to claim 1, characterized in that: The driving circuit layer comprises: A semiconductor layer, arranged on a side of the light-shielding metal layer away from the substrate, the semiconductor layer comprising: a first semiconductor corresponding to the pixel driving circuit and a second semiconductor corresponding to the gate driving circuit; A first metal layer is arranged on a side of the semiconductor layer away from the substrate, the first metal layer comprising: a first source and a first drain corresponding to the pixel driving circuit, and a second wiring arranged in the frame area; The second wiring and the gate driving circuit are arranged without overlapping, and the second wiring is connected in parallel with the first wiring through a via.

3. The display panel according to claim 2, characterized in that: The width of the second routing line is smaller than the width of the first routing line.

4. The display panel according to claim 3, characterized in that: A vertical projection of the second routing line on the substrate is located within a vertical projection of the first routing line on the substrate.

5. The display panel according to claim 4, characterized in that: An edge of the first wiring away from the gate driving circuit is a first edge, an edge of the second wiring away from the gate driving circuit is a second edge, and the first edge is flush with the second edge.

6. The display panel according to claim 5, characterized in that: The first routing line includes a first portion and a second portion, the first portion is overlapped with the second routing line, and the second portion is not overlapped with the second routing line, wherein a width of the first portion is smaller than a width of the second portion.

7. The display panel according to claim 6, characterized in that: The width of the first portion is a first width, the width of the second portion is a second width, and the first width is greater than or equal to 7 times the second width.

8. The display panel according to claim 7, characterized in that: The sum of the first width and the second width is greater than 150 μm, and the first width is 10 μm-20 μm.

9. The display panel according to claim 2, characterized in that: A vertical projection of the second semiconductor on the substrate is located within a vertical projection of the first routing line on the substrate, wherein the first routing line further includes a plurality of hollow portions, and the hollow portions are arranged without overlapping with the second semiconductor.

10. A display device, characterized in that: The display device comprises a housing and a display panel as claimed in any one of claims 1 to 9, wherein the housing has an accommodating space, and the display panel is arranged in the accommodating space.

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