A method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device

Abstract

The invention relates to a method for preparing a VCSEL device, in particular to a method for preparing a VCSEL device with a non-oxidized tunnel junction series multi-quantum well structure, which solves the technical problems of low optical power density and electro-optical efficiency, large light output aperture, low modulation rate, inability to be integrated at high density and low brightness in VCSEL devices prepared by the prior art. The invention provides a method for preparing a VCSEL device with a non-oxidized tunnel junction series multi-quantum well structure, comprising the steps of epitaxially growing an N-type DBR structure, epitaxially growing a first quantum well and a first phase adjustment layer to form a first intermediate terrace, preparing a first ion implantation layer, epitaxially growing a first tunnel junction, epitaxially growing a second quantum well, a second phase adjustment layer, a second intermediate platform, a second ion implantation layer and a second tunnel junction, epitaxially growing a third quantum well, a third phase adjustment layer, a third intermediate platform and a third ion implantation layer, epitaxially growing a P-type DBR structure, preparing an ohmic contact electrode and performing wafer cleavage.

Description

Technical Field

[0001] The invention relates to a method for preparing a VCSELs device, and in particular to a method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device. Background Art

[0002] Vertical Cavity Surface Emitting Semiconductor Lasers, abbreviated as VCSELs, are optoelectronic devices based on semiconductor materials such as AlGaAs / GaAs. Compared with traditional emitting semiconductor lasers, VCSELs have many advantages such as emitting light perpendicular to the epitaxial surface, circular symmetry of the output light spot, high fiber coupling efficiency, no optical catastrophic damage to the laser cavity surface, narrow spectral linewidth, and high-density two-dimensional integration. Therefore, they are widely used in important livelihood fields such as optical communications, optical interconnection, laser lighting, medical equipment, 3D sensing, laser ranging, and laser pumping.

[0003] Currently, mainstream VCSELs devices are developed using the technical solution of oxidation confinement structure. Its main feature is to set one or more epitaxial layers of high aluminum components in the epitaxial direction, and use wet oxidation technology to cause chemical changes in the epitaxial materials of high aluminum components, turning the area near the active area into a ring-shaped high-resistance area, thereby achieving effective control of the injection current path and light field. This technology has been well developed and has been commercialized.

[0004] However, this type of VCSEL device with an oxidation-confined structure has disadvantages such as large thermal resistance, large series resistance, high junction temperature, and easy thermal rollover. The main reason is that the aluminum component in the oxidation-confined structure is oxidized to form a barrier to heat flow, which makes it impossible for the heat generated by the p-DBR to diffuse effectively. It can only diffuse through the quantum well active area, causing the temperature superposition of the quantum well active area, resulting in the device being prone to thermal rollover, which restricts the further improvement of the device's output optical power and electro-optical conversion efficiency. As a result, the electro-optical conversion efficiency of the current oxidation-confined single-junction VCSELs is maintained at around 40%, and there is little room for further improvement. At the same time, since VCSELs devices with oxidation confinement structures require wet oxidation of the oxidation confinement layer of the high aluminum component after etching the ridge waveguide, the light output aperture is difficult to achieve below 3μm, limiting the number of devices integrated in the VCSELs two-dimensional array. The inherent shortcomings of VCSELs with oxidation confinement structures restrict the VCSELs unit devices from having room for further improvement in technical indicators such as integration, modulation rate, brightness, optical power density and electro-optical efficiency, and are unable to meet the growing application needs. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problems that the vertical cavity surface emitting semiconductor laser device prepared by the existing method has low optical power density and electro-optical efficiency, large light output aperture, modulation rate, inability to high-density integration, and low brightness due to the shortcomings of the existing preparation method of the device having large thermal resistance, large series resistance, high junction temperature, and easy thermal reversal, and to provide a preparation method for a non-oxidized tunnel junction series multi-quantum well structure VCSELs device.

[0006] In order to achieve the above purpose, the technical solution provided by the present invention is:

[0007] A method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device is special in that it comprises the following steps:

[0008] Step 1: Epitaxial growth of N-type DBR structure

[0009] Epitaxially growing an N-type GaAs buffer layer on an N-type GaAs substrate, and then epitaxially growing an N-type DBR structure on an upper surface of the N-type GaAs buffer layer;

[0010] Step 2: Epitaxially grow the first quantum well and the first phase adjustment layer to form the first intermediate mesa

[0011] After the epitaxial growth of the N-type DBR structure is completed, a first quantum well is epitaxially grown on the upper surface of the N-type DBR structure, and a first phase adjustment layer is epitaxially grown on the upper surface of the first quantum well; the first quantum well includes a potential well and a potential barrier, and the potential well is sandwiched between the upper and lower potential barriers;

[0012] Performing a mesa photolithography process on the first phase adjustment layer to form a first intermediate mesa;

[0013] Step 3: Preparation of the first ion implantation layer

[0014] Ions are implanted on the upper surface of the first quantum well, material modification is performed on the region other than the first intermediate mesa, and annealing is performed at a controlled annealing temperature to form a first ion implantation layer;

[0015] Step 4: Epitaxial growth of the first tunnel junction

[0016] Perform epitaxial growth on the first intermediate mesa and the upper surface of the first ion implantation layer to obtain a first tunnel junction;

[0017] Step 5: Epitaxially grow the second quantum well, the second phase adjustment layer, the second intermediate platform, the second ion implantation layer and the second tunnel junction

[0018] Epitaxially grow a first gradual transition layer on the upper surface of the first tunnel junction, and sequentially grow a second quantum well, a second phase adjustment layer, a second intermediate platform, a second ion implantation layer and a second tunnel junction according to the method of steps 2 to 4;

[0019] Step 6: Epitaxially grow the third quantum well, the third phase adjustment layer, the third intermediate platform and the third ion implantation layer

[0020] Epitaxially growing a second gradient transition layer on the upper surface of the second tunnel junction, and then sequentially obtaining a third quantum well, a third phase adjustment layer, a third intermediate platform, and a third ion implantation layer according to the methods of steps 2 to 5;

[0021] Step 7: Epitaxial growth of P-type DBR structure

[0022] Epitaxially growing a P-type DBR structure on the upper surface of the third ion implantation layer to obtain a VCSELs wafer material with a non-oxidized tunnel junction series multi-quantum well structure;

[0023] Step 8: Prepare ohmic contact electrodes and perform wafer cleavage

[0024] The obtained VCSELs wafer material is subjected to ohmic contact electrode preparation to obtain a P-type annular metal electrode and an N-type annular metal electrode, and then the wafer is cleaved to obtain a VCSELs device with a non-oxidized tunnel junction series multi-quantum well structure.

[0025] Furthermore, in step 4, before epitaxial growth is performed on the upper surface of the first intermediate mesa and the first ion implantation layer, the first intermediate mesa and the first ion implantation layer need to be cleaned of residual surface elements, and Ar is used as an etching gas to remove the residual surface elements, thereby providing excellent material surface morphology for the next epitaxial process.

[0026] Furthermore, in step 1, the N-type GaAs buffer layer is doped with Si at a doping concentration of 1.9x10 18 ~2.1x10 18 cm -3 , thickness is 450~550nm;

[0027] The N-type DBR structure is formed by alternating growth of Al with a mass fraction of 80% to 90% and Ga with a mass fraction of 10% to 20% and Al with a mass fraction of 10% to 20% and Ga. Due to the different refractive indices of the two materials, a reflectivity greater than 99% is generated after 38 pairs of alternating growth. The thickness of each layer of Al with a mass fraction of 80% to 90% and Ga with a mass fraction of 10% to 20% is 19 to 21 nm, and the thickness of each layer of Al with a mass fraction of 10% to 20% and Ga with a mass fraction of 80% to 90% is 48 to 52 nm.

[0028] In step 8, the surface of the prepared non-oxidized tunnel junction series multi-quantum well structure VCSELs device has P-type annular metal electrodes distributed in an array, the middle of the P-type annular metal electrode is a light exit window, and the light exit window has the same axis as the first intermediate platform, the second intermediate platform and the third intermediate platform, and the sizes are the same, thus ensuring that the light exit window has a higher brightness.

[0029] Further, in step 2, the composition and mass fraction of the potential well are: In 8% to 9%, Ga 91% to 92%; the composition and mass fraction of the potential barrier are: Al 20% to 30%, Ga 70% to 80%; the thickness of the N-type DBR structure is 7 to 8 nm;

[0030] The mesa photolithography process for the first phase adjustment layer is specifically as follows: using photoresist to protect the middle part of the first phase adjustment layer, using etching technology to etch the first phase adjustment layer to form a first intermediate mesa, wherein the height of the first intermediate mesa is 10 to 20 nm; at this time, only the first intermediate mesa exists on the upper surface of the first quantum well.

[0031] Furthermore, in step 3, ions are implanted on the upper surface of the first quantum well, and the implanted ions are oxygen, aluminum or silicon, and the implantation dose is 1x10 13 ~1x10 16 ions / cm 2 , the injection energy is 35~400keV;

[0032] The annealing temperature is 100-800° C., which is helpful to evenly distribute the injected ions, obtain an excellent current blocking layer structure, and form a first ion injection layer; the ion injection layer mainly achieves effective restriction on the injected current by changing the conductive properties of the AlGaAs material.

[0033] Furthermore, in step 4, the first tunnel junction is a Te-doped N-type GaAs structure with a thickness of 13-15 nm and a Te doping concentration of 2.8 x 10 19 ~3.2x10 19 cm -3 The growth method of the first tunnel junction is a conventional epitaxial growth process.

[0034] Furthermore, in step 5 and step 6, the first gradient transition layer and the second gradient transition layer are both 500 nm thick and are made of AlGaAs material.

[0035] Further, in step 7, the P-type DBR structure is formed by alternating the growth of Al with a mass fraction of 80% to 90%, Ga with a mass fraction of 10% to 20%, Al with a mass fraction of 10% to 20%, 80% to 90% Ga, 23 pairs of which are grown alternately, and the thickness of each layer of Al with a mass fraction of 80% to 90%, 10% to 20% Ga is 19 to 21 nm, and the thickness of each layer of Al with a mass fraction of 10% to 20%, 80% to 90% Ga is 48 to 52 nm.

[0036] Further, in step 8, the P-type annular metal electrode is an alloy of Ti, Pt and Au, and the ratio of Ti, Pt and Au is 14:9:40;

[0037] The N-type annular metal electrode is an alloy of Au, Ni and Au, and the ratio of Au, Ni and Au is 48:1:1.

[0038] Furthermore, in step 1, the Si doping concentration in the N-type GaAs buffer layer is 2×10 18 cm -3 , thickness is 500nm;

[0039] The N-type DBR structure is formed by alternating growth of 90% Al, 10% Ga and 10% Al, 90% Ga, each layer of 90% Al, 10% Ga has a thickness of 20nm, and each layer of 10% Al, 90% Ga has a thickness of 50nm;

[0040] In step 2, the composition and mass fraction of the potential well are: In 8.5%, Ga 91.5%; the composition and mass fraction of the potential barrier are: Al 25%, Ga 75%; the thickness of the first quantum well is 7.5 nm;

[0041] The height of the first intermediate terrace is 15 nm;

[0042] In step 3, the dose of implanted ions is 1x10 14 ions / cm 2 , the injection energy is 100keV;

[0043] The annealing temperature is 300° C.

[0044] In step 4, the thickness of the first tunnel junction is 14 nm, and the Te doping concentration is 3x10 19 cm -3 ;

[0045] In step 5 and step 6, the thickness of the first gradient transition layer and the second gradient transition layer are both 500 nm;

[0046] In step 7, the P-type DBR structure is formed by alternating growth of 90% Al, 10% Ga and 10% Al, 90% Ga, each layer of 90% Al, 10% Ga has a thickness of 20 nm, and each layer of 10% Al, 90% Ga has a thickness of 50 nm;

[0047] In step 8, the P-type annular metal electrodes on the surface of the prepared non-oxidized tunnel junction series multi-quantum well structure VCSELs device are distributed in a regular hexagonal array; the prepared non-oxidized tunnel junction series multi-quantum well structure VCSELs device is based on a regular hexagonal array integration of multiple non-oxidized tunnel junction series multi-quantum well structure VCSELs unit devices, and each non-oxidized tunnel junction series multi-quantum well structure VCSELs unit device includes a P-type annular metal electrode, a light exit window, a first intermediate table, a second intermediate platform and a third intermediate platform.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] 1. The present invention combines the advantages of planar lithography technology, tunnel junction technology and multiple epitaxial growth technology, and uses tunnel junctions to connect multiple quantum well light-emitting areas in series. It has the characteristics of low loss and high slope efficiency, and can achieve a multiple increase in slope efficiency. It also has good mode characteristics and realizes effective control of light field and current through the ion injection layer near the quantum well.

[0050] 2. The present invention adopts a method in which the first tunnel junction is connected in series with the first quantum well and the second quantum well, and the second tunnel junction is connected in series with the second quantum well and the third quantum well, so that multiple radiation recombination of electron-hole pairs can be achieved in the active region, generating multiple photons, greatly improving the quantum efficiency, and emitting a stronger output optical power when injecting less current, breaking through the theoretical limit of the traditional vertical cavity surface emitting laser quantum efficiency of less than 1, and achieving a doubling of the output optical power;

[0051] 3. The present invention utilizes ion implantation technology to achieve effective regulation of the injected current and light field, does not require an epitaxial layer with a high aluminum component and a wet oxidation process, and the prepared non-oxidized VCSELs device has a light output window aperture of 2 μm, has the advantages of small light output aperture, single-mode lasing, high modulation rate, and high-density integration, and the two-dimensional array based on the integration of non-oxidized VCSELs devices has high optical power density, high brightness, high modulation rate, and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a flow chart of an embodiment of the present invention;

[0053] Figure 2A schematic diagram of the structure of a non-oxidized tunnel junction series multi-quantum well structure VCSELs unit device prepared in an embodiment of the present invention;

[0054] Figure 3 A front view of a non-oxidized tunnel junction series multi-quantum well structure VCSELs device prepared in an embodiment of the present invention;

[0055] Figure 4 This is a top view of a non-oxidized tunnel junction series multi-quantum well structure VCSELs device prepared in an embodiment of the present invention.

[0056] The reference numerals are as follows:

[0057] 1-N-type GaAs substrate, 2-N-type GaAs buffer layer, 3-N-type DBR structure, 4-first quantum well, 401-potential well, 402-potential barrier, 5-first intermediate terrace, 6-first ion implantation layer, 7-first tunnel junction, 8-first gradual transition layer, 9-second quantum well, 10-second intermediate terrace, 11-second ion implantation layer, 12-second tunnel junction, 13-second gradual transition layer, 14-third quantum well, 15-third intermediate terrace, 16-third ion implantation layer, 17-P-type DBR structure, 18-P-type annular metal electrode, 19-N-type annular metal electrode, 20-light exit window. DETAILED DESCRIPTION

[0058] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0059] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device, and the preparation method comprises the following steps:

[0060] Step 1: Epitaxial growth of N-type DBR structure 3

[0061] An N-type GaAs buffer layer 2 is epitaxially grown on an N-type GaAs substrate 1. The N-type GaAs buffer layer 2 is doped with Si, and the Si doping concentration is 2x10 18 cm -3, with a thickness of 500nm; then, an N-type DBR structure 3 is epitaxially grown on the upper surface of the N-type GaAs buffer layer 2, wherein the N-type DBR structure 3 is formed by alternating growth of 90% Al, 10% Ga and 10% Al, 90% Ga, 38 pairs of which are grown alternately, each pair comprising a layer of 90% Al, 10% Ga and a layer of 10% Al, 90% Ga, each layer of 90% Al, 10% Ga has a thickness of 20nm, and each layer of 10% Al, 90% Ga has a thickness of 50nm;

[0062] Step 2: epitaxially grow the first quantum well 4 and the first phase adjustment layer to form the first intermediate mesa 5

[0063] After the epitaxial growth of the N-type DBR structure 3 is completed, a first quantum well 4 with a thickness of 7.5 nm is epitaxially grown on the upper surface of the N-type DBR structure 3. The first quantum well 4 includes a potential well 401 and a potential barrier 402. The components and mass fractions of the potential well 401 are: In 8.5%, Ga 91.5%; the components and mass fractions of the potential barrier 402 are: Al 25%, Ga 75%. A first phase adjustment layer is epitaxially grown on the upper surface of the first quantum well 4.

[0064] Performing a mesa photolithography process on the first phase adjustment layer, using photoresist to protect the middle part of the first phase adjustment layer, and using an etching technique to etch the first phase adjustment layer to form a first middle mesa 5 with a height of 15 nm;

[0065] Step 3: Preparation of the first ion implantation layer 6

[0066] Oxygen ions are implanted on the upper surface of the first quantum well 4, and the dose of the implanted oxygen ions is 1x10 14 ions / cm 2 , the implantation energy is 100 keV, the material is modified in the area outside the first intermediate table 5, and the annealing temperature is controlled to be 300° C. for annealing, which helps to achieve uniform distribution of the implanted ions to form a first ion implantation layer 6;

[0067] Step 4: Cleaning the first intermediate mesa 5 and the first ion implantation layer 6

[0068] Cleaning residual elements on the upper surface of the first intermediate mesa 5 and the first ion implantation layer 6, using Ar as etching gas to remove residual carbon and oxygen elements on the surface, so as to provide excellent material surface morphology for the next epitaxial process;

[0069] Step 5: Epitaxial growth of the first tunnel junction 7

[0070] The Te doping concentration is 3x10 19cm -3 The GaAs material is epitaxially grown on the upper surface of the first intermediate table 5 and the first ion implantation layer 6 to obtain a first tunnel junction 7 with a thickness of 14 nm. The first tunnel junction 7 is an N-type GaAs structure, and the epitaxial growth method is a conventional method;

[0071] Step 6: epitaxially grow the second quantum well 9, the second phase adjustment layer, the second intermediate platform 10, the second ion implantation layer 11 and the second tunnel junction 12

[0072] A first gradient transition layer 8 with a thickness of 500 nm is obtained by epitaxially growing an AlGaAs material on the upper surface of the first tunnel junction 7, and then a second quantum well 9, a second phase adjustment layer, a second intermediate platform 10, a second ion implantation layer 11 and a second tunnel junction 12 are obtained in sequence according to the method of steps 2 to 4;

[0073] Step 7: epitaxially grow the third quantum well 14, the third phase adjustment layer, the third intermediate platform 15 and the third ion implantation layer 16

[0074] A second gradient transition layer 13 with a thickness of 500 nm is obtained by epitaxially growing AlGaAs material on the upper surface of the second tunnel junction 12, and then a third quantum well 14, a third phase adjustment layer, a third intermediate platform 15 and a third ion implantation layer 16 are obtained in sequence according to the method of steps 2 to 4;

[0075] Step 8: Epitaxial growth of P-type DBR structure 17

[0076] 23 pairs of Al and 10% Ga with a mass fraction of 90% and Al and 90% Ga with a mass fraction of 10% are alternately grown on the upper surface of the third ion implantation layer 16 to obtain a P-type DBR structure 17, each layer of Al and 10% Ga with a mass fraction of 90% has a thickness of 20nm, and each layer of Al and 90% Ga with a mass fraction of 10% has a thickness of 50nm, to obtain a VCSELs wafer material with a non-oxidized tunnel junction series multi-quantum well structure;

[0077] Step 9: Prepare ohmic contact electrodes and perform wafer cleavage

[0078] The obtained VCSELs wafer material is subjected to ohmic contact electrode preparation, and a P-type annular metal electrode 18 is prepared by using Ti, Pt and Au in a ratio of 14:9:40, and an N-type annular metal electrode 19 is prepared by using Au, Ni and Au in a ratio of 48:1:1. Finally, the wafer is cleaved as needed to obtain a VCSELs device with a non-oxidized tunnel junction series multi-quantum well structure integrated in a regular hexagonal array of VCSELs unit devices with a non-oxidized tunnel junction series multi-quantum well structure. The aperture of the light exit window 20 of the VCSELs device with a non-oxidized tunnel junction series multi-quantum well structure is 2 μm, and the spacing between adjacent P-type annular metal electrodes 18 is 10 μm, which greatly increases the number of devices integrated in the VCSELs two-dimensional array.

[0079] Figure 2 The present invention is a schematic structural diagram of a non-oxidized tunnel junction series multi-quantum well structure VCSELs unit device prepared by the present invention. Each non-oxidized tunnel junction series multi-quantum well structure VCSELs unit device comprises a P-type annular metal electrode 18, a light exit window 20, a first intermediate table 5, a second intermediate platform 10 and a third intermediate platform 15. The light exit window 20, the first intermediate table 5, the second intermediate platform 10 and the third intermediate platform 15 of each non-oxidized tunnel junction series multi-quantum well structure VCSELs unit device are coaxially distributed and have the same size.

[0080] like Figure 3 , Figure 4 As shown, a regular hexagonal two-dimensional array of multiple non-oxidized tunnel junction series multi-quantum well structure VCSELs unit devices constitutes the final prepared non-oxidized tunnel junction series multi-quantum well structure VCSELs device. Figure 3 This is the front view of the non-oxidized tunnel junction tandem multi-quantum well structure VCSELs device. Figure 4 This is a top view of the non-oxidized tunnel junction tandem multi-quantum well structure VCSELs device. Figure 4 It can be seen that the P-type annular metal electrodes 18 are distributed in a regular hexagonal array.

[0081] By testing the non-oxidized tunnel junction series multi-quantum well structure VCSELs device prepared by the present invention, it is found that the present invention adopts the method of simultaneously connecting the first tunnel junction 7 in series with the first quantum well 4 and the second quantum well 9, and simultaneously connecting the second tunnel junction 12 in series with the second quantum well 9 and the third quantum well 14, so that multiple radiation recombination of electron-hole pairs in the active region can be achieved to generate multiple photons, the quantum efficiency is greatly improved, and a stronger output light power is emitted when less current is injected, breaking through the theoretical limit of the traditional vertical cavity surface emitting laser quantum efficiency being less than 1, and achieving a doubling of the output light power. The non-oxidized tunnel junction series multi-quantum well structure VCSELs device prepared by the present invention consists of multiple quantum well light-emitting areas including a first quantum well 4, a second quantum well 9 and a third quantum well 14. These quantum well light-emitting areas share a pair of DBR structures to provide light feedback. DBR is a distributed Bragg reflector. Under the same injection current, the output light power, slope efficiency and electro-optical conversion efficiency of the VCSELs device are greatly improved with the increase of the number of quantum wells. This new device structure is particularly suitable for working under pulse conditions and is a new light source in application fields such as the new generation of 3D perception and lidar.

[0082] The above disclosure is only a specific embodiment of the present invention, but the embodiments of the present invention are not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device, characterized in that: The following steps are involved: Step 1: epitaxially growing an N-type GaAs buffer layer (2) on an N-type GaAs substrate (1), and then epitaxially growing an N-type DBR structure (3) on the upper surface of the N-type GaAs buffer layer (2); The N-type GaAs buffer layer (2) is doped with Si at a doping concentration of 1.9×10 18 ~2.1x10 18 cm -3 , thickness is 450~550nm; The N-type DBR structure (3) is formed by alternating growth of 90% Al, 10% Ga and 10% Al, 90% Ga, 38 pairs of which are grown alternately, the thickness of each layer of 90% Al, 10% Ga is 19-21 nm, and the thickness of each layer of 10% Al, 90% Ga is 48-52 nm. Step 2: epitaxially growing a first quantum well (4) on the upper surface of the N-type DBR structure (3), and epitaxially growing a first phase adjustment layer on the upper surface of the first quantum well (4); the first quantum well (4) comprises a potential well (401) and a potential barrier (402); Performing a mesa photolithography process on the first phase adjustment layer to form a first intermediate mesa (5); Step 3: injecting ions into the upper surface of the first quantum well (4), modifying the material of the area outside the first intermediate mesa (5), and performing annealing at a controlled annealing temperature to obtain a first ion implantation layer (6); Step 4: epitaxial growth is performed on the upper surface of the first intermediate mesa (5) and the first ion implantation layer (6) to obtain a first tunnel junction (7); Step 5: epitaxially growing a first gradient transition layer (8) on the upper surface of the first tunnel junction (7), and then sequentially obtaining a second quantum well (9), a second phase adjustment layer, a second intermediate platform (10), a second ion implantation layer (11) and a second tunnel junction (12) according to the methods of steps 2 to 4; Step 6: epitaxially growing a second gradient transition layer (13) on the upper surface of the second tunnel junction (12), and then sequentially obtaining a third quantum well (14), a third phase adjustment layer, a third intermediate platform (15), and a third ion implantation layer (16) according to the methods of steps 2 to 4; Step 7: epitaxially growing a P-type DBR structure (17) on the upper surface of the third ion implantation layer (16) to obtain a VCSELs wafer material with a non-oxidized tunnel junction series multi-quantum well structure; Step 8: preparing ohmic contact electrodes on the obtained VCSELs wafer material, respectively preparing a P-type annular metal electrode (18) and an N-type annular metal electrode (19), and then cleaving the wafer to obtain a VCSELs device with a non-oxidized tunnel junction series multi-quantum well structure; the surface of the obtained VCSELs device with a non-oxidized tunnel junction series multi-quantum well structure has P-type annular metal electrodes (18) distributed in an array, the middle of the P-type annular metal electrode (18) is a light exit window (20), and the light exit window (20) is coaxially distributed with the first intermediate platform (5), the second intermediate platform (10) and the third intermediate platform (15), and the sizes are the same.

2. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 1, characterized in that: In step 4, before epitaxial growth is performed on the upper surface of the first intermediate mesa (5) and the first ion implantation layer (6), the first intermediate mesa (5) and the first ion implantation layer (6) need to be cleaned of residual elements on the surface, and Ar is used as an etching gas to remove the residual elements on the surface.

3. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 2, characterized in that: In step 2, the components and mass fractions of the potential well (401) are: In 8% to 9%, Ga 91% to 92%; the components and mass fractions of the potential barrier (402) are: Al 20% to 30%, Ga 70% to 80%; the thickness of the first quantum well (4) is 7.5 nm; The mesa photolithography process for the first phase adjustment layer is specifically as follows: using photoresist to protect the middle part of the first phase adjustment layer, etching the first phase adjustment layer using etching technology to form a first middle mesa (5), wherein the height of the first middle mesa (5) is 10-20 nm.

4. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 3, characterized in that: In step 3, ions are implanted on the upper surface of the first quantum well (4), and the implanted ions are oxygen, aluminum or silicon, and the implantation dose is 1x10 13 ~1x10 16 ions / cm 2 , the injection energy is 100keV; The annealing temperature is 300°C.

5. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 4, characterized in that: In step 4, the first tunnel junction (7) is a Te-doped N-type GaAs structure with a thickness of 13-15 nm and a Te doping concentration of 2.8 x 10 19 ~3.2x10 19 cm -3 .

6. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to any one of claims 3 to 5, characterized in that: In step 5 and step 6, the first gradient transition layer (8) and the second gradient transition layer (13) both have a thickness of 450-550 nm and are made of AlGaAs material.

7. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 6, characterized in that: In step 7, the P-type DBR structure (17) is formed by alternating growth of 90% Al, 10% Ga and 10% Al, 90% Ga, 23 pairs of which are grown alternately, and the thickness of each layer of 90% Al, 10% Ga is 19-21 nm, and the thickness of each layer of 10% Al, 90% Ga is 48-52 nm.

8. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 7, characterized in that: In step 8, the P-type annular metal electrode (18) is an alloy of Ti, Pt and Au, and the ratio of Ti, Pt and Au is 14:9:40; The N-type annular metal electrode (19) is an alloy of Au, Ni and Au, and the ratio of Au, Ni and Au is 48:1:

1.

9. The method for preparing a non-oxidized tunnel junction series multi-quantum well structure VCSELs device according to claim 8, characterized in that: In step 1, the Si doping concentration in the N-type GaAs buffer layer (2) is 2×10 18 cm -3 , thickness is 500nm; In the N-type DBR structure (3), each layer of Al with a mass fraction of 90% and Ga with a mass fraction of 10% has a thickness of 20 nm, and each layer of Al with a mass fraction of 10% and Ga with a mass fraction of 90% has a thickness of 50 nm; In step 2, the composition and mass fraction of the potential well (401) are: In 8.5%, Ga 91.5%; the composition and mass fraction of the potential barrier (402) are: Al 25%, Ga 75%; The height of the first intermediate terrace (5) is 15 nm; In step 3, the implanted ions are oxygen, and the implanted dose is 1x10 14 ions / cm 2 ; In step 4, the thickness of the first tunnel junction (7) is 14 nm, and the Te doping concentration is 3x10 19 cm -3 ; In step 5 and step 6, the thickness of the first gradient transition layer (8) and the second gradient transition layer (13) are both 500 nm; In step 7, in the P-type DBR structure (17), each layer of Al with a mass fraction of 90% and Ga with a thickness of 20 nm, and each layer of Al with a mass fraction of 10% and Ga with a thickness of 50 nm; In step 8, the P-type annular metal electrodes (18) on the surface of the prepared non-oxidized tunnel junction series multi-quantum well structure VCSELs device are distributed in a regular hexagonal array.

Images