Ceramic copper circuit substrate and semiconductor device using the same

Abstract

The ceramic-copper circuit board according to the embodiment includes a ceramic substrate and a copper circuit board disposed on one side of the ceramic substrate. Its characteristic is that the ratio of the thickness of the copper circuit board to the thickness of the ceramic substrate is 1.25 or more, and the number of grain boundaries on any 10mm straight line drawn on the surface of the copper circuit board is 5 or more and 250 or less.

Description

[0001] The present application is a divisional application of the application numbered 201880008419.8 and filed on March 23, 2018, and entitled “CERAMIC COPPER CIRCUIT SUBSTRATE AND SEMICONDUCTOR DEVICE USING THE SAME”. Technical Field

[0002] The embodiments generally relate to a ceramic copper circuit board and a semiconductor device using the same. Background Art

[0003] Ceramic copper circuit substrates have been used in semiconductor devices equipped with semiconductor elements such as power elements. The ceramic substrate and the copper circuit board are bonded together via a bonding layer. As a bonding layer, Ag solder containing active metals such as Ti is used. This improves the bonding strength and thermal cycle characteristics. By improving the reliability of the ceramic copper circuit substrate, it is suitable for use in converters for automobiles (including electric vehicles), electric railway vehicles, solar power generation equipment, and industrial machinery.

[0004] In semiconductor devices such as power modules, semiconductor elements are mounted on copper circuit boards. Bonding wires or metal terminals are sometimes bonded to the copper circuit board for the conduction of the semiconductor element. To complete the semiconductor device, the semiconductor element, bonding wires, metal terminals, etc. are bonded to the copper circuit board.

[0005] As a ceramic copper circuit board with improved reliability, there is International Publication No. WO2013-094213 (Patent Document 1). Patent Document 1 improves reliability by optimizing the side shape of the copper circuit board. The ceramic copper circuit board of Patent Document 1 improves bonding strength and thermal cycling properties.

[0006] On the other hand, there is still room for improvement in terms of improving the reliability of the assembly process for bonding semiconductor elements, bonding wires, metal terminals, etc. to a copper circuit board.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: International Publication No. 2013-094213 Summary of the invention

[0010] Problems to be solved by the invention

[0011] In recent years, with the improvement of the performance of semiconductor elements, the junction temperature of semiconductor devices during operation has reached more than 170°C. In order to improve the heat dissipation, the copper circuit board is also being studied to be thicker. By thinning the ceramic substrate and thickening the copper circuit board, the heat dissipation is improved. On the other hand, the thermal expansion of the copper plate affects the reliability of the bonding of semiconductor elements, etc.

[0012] The embodiment is made to solve such a problem and relates to a ceramic copper circuit board that achieves both reliability and bonding properties with semiconductor elements and the like.

[0013] Means for solving problems

[0014] The ceramic copper circuit substrate of the embodiment comprises a ceramic substrate and a copper circuit board provided on one surface of the ceramic substrate, wherein the ratio of the thickness of the copper circuit board to the thickness of the ceramic substrate is 1.25 or more, and the number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is 5 or more and 250 or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram showing an example of a ceramic copper circuit board according to an embodiment.

[0016] Figure 2 This is a diagram showing an example of the surface of a copper circuit board.

[0017] Figure 3 It is a diagram showing another example of the ceramic copper circuit board according to the embodiment.

[0018] Figure 4 FIG. 1 is a diagram showing an example of a semiconductor device according to an embodiment.

[0019] Figure 5 This is a diagram showing still another example of the ceramic copper circuit board according to the embodiment. DETAILED DESCRIPTION

[0020] The ceramic copper circuit substrate involved in the embodiment is a ceramic copper circuit substrate having a copper circuit board on at least one surface of the ceramic substrate, characterized in that the ratio of the thickness of the copper circuit board to the thickness of the ceramic substrate is greater than 1.25, and the number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is greater than 5 and less than 250.

[0021] Figure 1 An example of a ceramic copper circuit substrate is shown in FIG. 1 is a ceramic copper circuit substrate. 2 is a ceramic substrate. 3 is a copper circuit board (surface copper board). 4 is a bonding layer. 5 is a back copper board. T1 is the thickness of the ceramic substrate. T2 is the thickness of the copper circuit board. Figure 1 The example in which two copper circuit boards 3 are bonded to the ceramic substrate 2 is shown. The embodiment is not limited to this form, and one or three or more copper circuit boards 3 may be bonded to the ceramic substrate 2. Figure 1 In the example of , in addition, the back copper plate 5 can also be bonded to the ceramic substrate 2. The back copper plate 5 does not function as a circuit but as a heat sink. The back copper plate 5 can be provided as needed.

[0022] The ratio (T2 / T1) of the thickness T1 of the ceramic substrate 2 to the thickness T2 of the copper circuit board 3 is 1.25 or more. The thickness T2 of the copper circuit board 3 is defined as the thickness of the thickest copper plate among the copper plates used as the circuit board in the ceramic copper circuit board 1. Therefore, the thickness of the back copper plate 5 is not treated as T2.

[0023] T2 / T1≥1.25 indicates that the copper circuit board 3 is thicker than the ceramic substrate 2. By thickening the copper circuit board 3 and thinning the ceramic substrate 2, the thermal resistance of the ceramic copper circuit board 1 can be reduced. Therefore, it is preferred that T2 / T1 is 1.25 or more. It is more preferred that T2 / T1 is 2.40 or more.

[0024] The ceramic substrate 2 is preferably any one of an aluminum oxide substrate, an aluminum nitride substrate, and a silicon nitride substrate. In addition, the ceramic substrate 2 may also be an alusil high silicon heat-resistant aluminum alloy substrate. The alusil high silicon heat-resistant aluminum alloy substrate is formed by a sintered body mixed with aluminum oxide and zirconium oxide.

[0025] The three-point bending strength of aluminum nitride substrates or alumina substrates is in the range of 300 to 450 MPa. The strength of Alusil high-silicon heat-resistant aluminum alloy substrates is about 550 MPa. For ceramic substrates with a strength of less than 550 MPa, if the thickness of the substrate is reduced to less than 0.4 mm, there is a concern that the ceramic substrate may crack during a thermal cycle test (TCT test).

[0026] The 3-point bending strength of a silicon nitride substrate is, for example, 600 MPa or more. The strength can be further improved to a 3-point bending strength of 700 MPa or more. The thermal conductivity of a silicon nitride substrate is, for example, 50 W / m·K or more. The thermal conductivity can also be made to be 80 W / m·K or more. In particular, in recent years, there is a silicon nitride substrate that has both high strength and high thermal conductivity. As long as the 3-point bending strength of a silicon nitride substrate is 600 MPa or more and the thermal conductivity is 80 W / m·K or more, the thickness of the substrate can be, for example, 0.40 mm or less. It can also be further thinned to a thickness of 0.30 mm or less. By thinning the ceramic substrate, T2 / T1 can be set to 1.25 or more, and further to 2.40 or more.

[0027] Furthermore, the ceramic substrate may be a single plate or may have a three-dimensional structure such as a multi-layer structure.

[0028] On any 10 mm straight line drawn on the surface of the copper circuit board, the number of grain boundaries is 5 or more and 250 or less. Figure 2 An example of a copper plate surface is shown. Figure 2In the figure, 3 is a copper circuit board, 6 is a copper grain, and 7 is a grain boundary. The copper circuit board is formed of a copper polycrystal. Take an enlarged photo of the surface of the copper circuit board. Enlarge the enlarged photo to the extent that the grain boundary can be confirmed. When a 10 mm straight line portion cannot be photographed in one field of view, split it into multiple portions for photography. When processing the copper circuit board into a pattern shape, photograph the portion with a length of more than 10 mm in any direction.

[0029] In the embodiment, whenever any straight line of 10 mm is drawn on the enlarged photograph, the number of grain boundaries on the straight line is 5 or more and 250 or less.

[0030] Semiconductor elements, bonding leads, metal terminals, etc. are bonded to the copper circuit board 3. At this time, they are bonded to each other via a bonding layer such as solder. If the surface of the copper circuit board 3 has grain boundaries, an anchoring effect can be obtained relative to the bonding layer. The wettability with the bonding layer can also be improved. When the number of grain boundaries on a 10mm straight line is less than 5, the number of grain boundaries is small and insufficient. If the number of grain boundaries is small, the copper grains are large, and the contact ratio between the bonding layer and the copper grain surface is high. If the junction temperature of the semiconductor element increases, the thermal expansion of the copper plate increases. If there are few grain boundaries, the anchoring effect is insufficient, so it is easy to produce peeling between the surface of the copper circuit board and the bonding layer. If the number of grain boundaries on a 10mm straight line exceeds 250, the number of grain boundaries is too large. If the number of grain boundaries increases, although the anchoring effect can be obtained, the heat dissipation is reduced due to too many grain boundaries. Therefore, regardless of any 10mm straight line, the number of grain boundaries is preferably greater than 5 and less than 250, and more preferably greater than 20 and less than 150. It is more preferred that the number of grain boundaries is greater than 80 and less than 150 regardless of any 10mm straight line. The number of grain boundaries is within the above range wherever a 10 mm straight line is drawn on the surface of the copper circuit board 3, so that excellent reliability can be obtained wherever a semiconductor element is bonded to the copper circuit board 3. In other words, a circuit board with excellent assemblability of a semiconductor device can be obtained.

[0031] The number of grain boundaries can also be adjusted by adjusting the crystal size through a rolling process that adjusts the thickness of the copper plate. The number of grain boundaries can also be adjusted by utilizing a heat treatment process in the manufacturing process of a ceramic copper circuit substrate. The recrystallization temperature of copper is approximately 220°C. As described later, the ceramic substrate and the copper plate can be joined, for example, using an active metal bonding method. In the active metal bonding method, the ceramic substrate and the copper plate are heated at 700 to 900°C. The copper plate is recrystallized by this process. If recrystallized, the copper grains become larger. By utilizing this phenomenon, the number of grain boundaries can also be adjusted.

[0032] The copper circuit board surface preferably has an arithmetic mean roughness Ra of 0.4 μm or less, a ten-point mean roughness Rzjis of 4 μm or less, and a maximum height Rz of 5 μm or less. The surface roughness parameters Ra, Rzjis, and Rz are based on the provisions of JIS-B-0601 (2001).

[0033] JIS-B-0601 (2001) corresponds to ISO4287 (1997, Amd.1:2009). Ra, Rzjis, and Rz can also be measured using ISO4287. For differences between JIS-B-0601 and ISO4287, JIS takes precedence.

[0034] The arithmetic mean roughness Ra is the average value of the roughness curve. The maximum height Rz is the maximum value in the longitudinal direction of the top and bottom of the roughness curve. The ten-point average roughness Rzjis is the sum of the average of the top five peaks and the average of the top five valleys in the roughness curve.

[0035] By setting Ra, Rzjis and Rz to the above values, a copper circuit board surface with small surface unevenness can be obtained. If the anchoring effect of the copper circuit board on the bonding layer such as solder is taken into consideration, it is considered that the surface is preferably rough. On the other hand, if the thickness of the copper circuit board increases, the junction temperature of the semiconductor element increases, and the thermal expansion of the copper circuit board increases. If the thermal expansion of the copper circuit board increases, the side with large surface unevenness is prone to stress on the bonding layer, and cracks and other undesirable conditions are prone to occur.

[0036] Therefore, the copper circuit board surface preferably has an arithmetic mean roughness Ra of 0.4 μm or less, a ten-point average roughness Rzjis of 4 μm or less, and a maximum height Rz of 5 μm or less. Even if the surface irregularities are reduced, the reliability of the copper circuit board can be improved by controlling the number of grain boundaries.

[0037] The arithmetic mean roughness Ra of the copper circuit board surface is preferably 0.1 μm or more and 0.4 μm or less. The ten-point average roughness Rzjis of the copper circuit board surface is preferably 1.5 μm or more and 4 μm or less. The maximum height Rz of the copper circuit board surface is preferably 1 μm or more and 5 μm or less. Flattening the surface above this may increase the manufacturing cost.

[0038] The skewness Rsk of the roughness curve in the surface of the copper circuit board is preferably less than 0. Rsk less than 0 means that Rsk is negative. If Rsk is negative, it means that there are many valleys in the roughness curve. The grain boundary portion of the copper circuit board becomes a valley. By forming the valley portion in the grain boundary portion, the anchoring effect of the copper circuit board on the solder (or brazing material) can be improved when joining semiconductor elements. Therefore, it is preferred that the skewness Rsk of the roughness curve on the surface of the copper circuit board is less than 0. More preferably, the skewness Rsk of the roughness curve is less than -0.01 and greater than -0.10. By making the skewness Rsk within this range, the anchoring effect can also be improved for the joining of lead frames and bonding leads other than semiconductor elements.

[0039] The skewness Rsk of the roughness curve is measured in accordance with ISO 4287 (1997, Amd. 1: 2009).

[0040] When the copper back plate 5 is provided, it is preferable that the copper back plate 5 has the following structure.

[0041] The ratio (T3 / T1) of the thickness T1 of the ceramic substrate 2 to the thickness T3 of the copper back plate 5 is 1.25 or more, and more preferably T3 / T1 is 2.40 or more.

[0042] Regardless of any 10 mm straight line drawn on the surface of the back copper plate, the number of grain boundaries is greater than 5 and less than 250. Preferably, the number of grain boundaries is greater than 20 and less than 150. More preferably, the number of grain boundaries is greater than 80 and less than 150. The method for calculating the number of grain boundaries is the same as the method for calculating the number of grain boundaries on the surface of the copper circuit board. The so-called surface of the back copper plate refers to the surface of the back copper plate 5 on the opposite side of the ceramic substrate 2.

[0043] On the surface of the back copper plate, the arithmetic mean roughness Ra is preferably less than 0.4μm, the ten-point average roughness Rzjis is less than 4μm, and the maximum height Rz is less than 5μm. The arithmetic mean roughness Ra of the back copper plate surface is preferably greater than 0.1μm and less than 0.4μm. The ten-point average roughness Rzjis of the back copper plate surface is preferably greater than 1.5μm and less than 4μm. The maximum height Rz of the back copper plate surface is preferably greater than 1μm and less than 5μm. The skewness Rsk of the roughness curve in the back copper plate surface is preferably less than 0. More preferably, the skewness Rsk of the roughness curve is less than -0.01 and greater than -0.10.

[0044] It is preferred that the ceramic substrate 2 and the copper circuit board 3 are joined via a joining layer 4. When the back copper plate 5 is joined to the ceramic substrate 2, it is also preferred that the back copper plate 5 and the ceramic substrate 2 are joined via a joining layer. It is preferred that a joining layer 4 containing Ag and Ti is provided between the ceramic substrate 2 and the copper circuit board 3. The joining layer 4 containing Ag (silver) and Ti (titanium) is made of an active metal brazing filler metal. Ti is an active metal. In addition to Ti, Zr and Hf can also be listed as active metal brazing fillers. A mixture of Ti, Ag (silver), and Cu (copper) can be listed. In the active metal brazing filler metal, the content of Ti is greater than 0.1wt% and less than 10wt%, the content of Cu is greater than 10wt% and less than 60wt%, and the remainder is Ag. It is also possible to add one or two selected from In (indium) or Sn (tin) to the active metal brazing filler metal in an amount of greater than 1wt% and less than 15wt% as needed. In the active metal bonding method using active metal brazing filler metal, an active metal brazing filler metal paste is applied to the surface of a ceramic substrate, and a copper plate is placed thereon. The bonding is performed by heating the ceramic substrate at 700 to 900°C. According to the active metal bonding method, the bonding strength between the ceramic substrate and the copper circuit board can be set to 16 kN / m or more.

[0045] The thickness of the copper circuit board is preferably 0.6 mm or more. As described above, in order to make the ratio of the thickness T2 of the copper circuit board to the thickness T1 of the ceramic substrate (T2 / T1) be above 1.25, it is effective to thin the ceramic substrate and thicken the copper circuit board. By thickening the copper circuit board, the heat dissipation is improved. As described above, as long as the surface roughness of the copper circuit board is well controlled, the poor bonding between the semiconductor element and the copper circuit board caused by thermal expansion can be reduced. If the heat dissipation is taken into consideration, the thickness of the copper circuit board is preferably 0.6 mm or more. The thickness of the copper circuit board is more preferably 0.8 mm or more. There is no particular upper limit to the thickness of the copper circuit board, but it is preferably 5 mm or less. If the thickness of the copper circuit board exceeds 5 mm, there is a concern that the warping will increase when bonding using the active metal bonding method.

[0046] When the copper circuit board is divided into three equal parts in the thickness direction, Ag preferably exists in 15% or more and 60% or less of the area of ​​the copper circuit board in the region on the bonding layer side of the copper circuit board. Figure 5 An example of a cross section of a copper circuit board is shown. Figure 5 2 is a ceramic substrate, 3 is a copper circuit board, 4 is a bonding layer, and T2 is the thickness of the copper circuit board 3. The copper circuit board 3 is divided into three equal parts in the thickness direction. This is to divide the thickness T2 of the copper circuit board 3 into three equal parts. When the copper circuit board 3 is divided into three equal parts, the area on the bonding layer 4 side is set as area 3a, the area in the middle is set as area 3b, and the area on the surface side is set as area 3c.

[0047] The dispersion state of Ag in any cross section of the copper circuit board 3 is color mapped by EDX (energy dispersive x-ray spectroscopy). In the cross section of region 3a, when observing a randomly selected unit area of ​​100 μm×100 μm, the ratio of the area of ​​Ag dispersion to the unit area is 15% or more and 60% or less. The observed cross section is polished to a surface roughness Ra of 1 μm or less. SEM (scanning electron microscope)-EDX is used for observation.

[0048] The boundary between the copper circuit board 3 and the bonding layer 4 can be determined by the SEM image. If it is difficult to determine by the SEM image, a straight line can be drawn from one end of the surface of the copper circuit board 3 on the bonding layer 4 side to the other end on the opposite side. Alternatively, the straight line can be regarded as the boundary between the copper circuit board 3 and the bonding layer 4. For example, Figure 1 As shown, if the bonding layer 4 is exposed from the end of the copper circuit board 3, it is easy to use the method of drawing a straight line.

[0049] If the thickness T2 of the copper circuit board is greater than 0.6 mm, and then further thickened to greater than 0.8 mm, the stress of the copper plate increases. When thermal stress is applied, cracks are likely to occur in the ceramic substrate and the bonding layer due to the difference in thermal expansion between the ceramic substrate and the copper plate. By diffusing Ag more, the thermal expansion of the copper circuit board can be made close to the thermal expansion of the ceramic substrate. Ag mainly diffuses along the grain boundaries. By diffusing along the grain boundaries, Ag easily diffuses to the inside of the copper plate. In the implementation mode, since the number of grain boundaries of the copper circuit board is controlled, the ease of diffusion of Ag can also be controlled.

[0050] When the unit area of ​​the observation region 3a is 100 μm×100 μm, the ratio of the area of ​​Ag dispersion to the observed area is preferably 15% or more and 60% or less. More preferably, the ratio is 25% or more and 50% or less. In the embodiment, regardless of which unit area of ​​100 μm×100 μm in the observation region 3a is, the ratio of the area of ​​Ag dispersion to the observed area is 15% or more and 60% or less.

[0051] When the unit area of ​​the observation region 3b is 100 μm×100 μm, the ratio of the area of ​​Ag dispersion to the observed area is preferably 0% or more and 40% or less. The so-called 0% ratio means that no Ag is detected by EDX. In addition, the dispersion area of ​​Ag in the region 3b is smaller than the dispersion area of ​​Ag in the region 3a.

[0052] When the unit area of ​​the observation region 3c is 100 μm×100 μm, the ratio of the Ag dispersed area to the observation area is preferably 0. The ratio of Ag in the region 3b is preferably set to 40% or less (including 0%), and the ratio of Ag in the region 3c is preferably set to 0%.

[0053] By preventing Ag from diffusing into the surface side region 3a of the copper circuit board 3, it is easy to control the surface roughness and the number of grain boundaries on the surface of the copper circuit board. Therefore, when mounting the semiconductor element, the adhesion between the semiconductor element and the solder (or solder) can be maintained. In other words, both the durability against thermal stress and the adhesion with the solder can be taken into account.

[0054] It is preferable that the diffusion state of Ag into the back copper plate 5 or the back copper circuit board 8 is also the same as that of the copper circuit board 3 .

[0055] That is, when the back copper plate 5 is divided into three equal parts, the area on the side of the bonding layer 4 is set as the first area, the area in the middle is set as the second area, and the area on the surface side is set as the third area. The unit area of ​​each observed area is 100μm×100μm. In the first area, the ratio of the area of ​​Ag dispersion to the observed area is preferably greater than 15% and less than 60%. More preferably, the ratio is greater than 25% and less than 50%. In the second area, the ratio of the area of ​​Ag dispersion to the observed area is preferably greater than 0% and less than 40%. In the third area, the ratio of the area of ​​Ag dispersion to the observed area is preferably 0%.

[0056] In the ceramic copper circuit substrate 1, the warpage of the ceramic substrate 2 is preferably less than 0.1 mm. The warpage of the ceramic substrate 2 can be measured by the following method. Draw an imaginary straight line from one end to the other end of the long side of the ceramic substrate 2. The distance between the straight line and the point of the ceramic substrate 2 farthest from the straight line is taken as the warpage. By controlling the diffusion state of Ag as described above, the warpage of the ceramic substrate 2 can be made less than 0.1 mm.

[0057] In particular, even when a silicon nitride substrate with a three-point bending strength of more than 600 MPa is used and a copper plate with a thickness of more than 0.6 mm is joined, the warping of the silicon nitride substrate can be reduced to less than 0.1 mm without performing a warping correction process. The so-called warping correction process is a process of heating the ceramic copper circuit substrate while applying pressure. If the copper plate is thickened or the strength of the ceramic substrate is low, the warping is likely to increase during joining. By performing the warping correction process, the warping of the ceramic substrate can be reduced. On the other hand, the warping correction process causes the grain growth of the copper plate due to the heat load. If the grains grow, there is a concern that the number of grain boundaries per 10 mm on the surface of the copper plate will be less than 5. If the warping correction process is not performed, it is easy to control the number of grain boundaries per 10 mm on the surface of the copper plate to more than 80.

[0058] By setting the number of grain boundaries per 10 mm on the copper plate surface to be greater than 80 and less than 150, the warpage of the silicon nitride substrate can be reduced to less than 0.1 mm even if the volume ratios of the front and back copper plates are different. The total volume of the copper circuit board 3 is set to A (mm 3), the total volume of the back copper plate 5 is set to B (mm 3 Even in the range of 0.5≤A / B≤0.8, the warpage of the silicon nitride substrate can be reduced to less than 0.1 mm. The total volume A (mm 3 ) is the total volume of each of the one or more copper circuit boards 3 bonded to the front side. The total volume B (mm) of the back copper plate 5 3 ) is the total volume of each of the one or more back copper plates 5 bonded to the back side. When one or more back copper circuit boards are bonded to the ceramic substrate 2 as described later, the total volume of each back copper circuit board is set as the total volume B (mm 3 ).

[0059] In a ceramic copper circuit board in which a silicon nitride substrate having a three-point bending strength of 600 MPa or more and a copper plate having a thickness of 0.6 mm or more are bonded, it is preferred that the number of grain boundaries per 10 mm on the surface of the copper plate be controlled to be 80 or more and 150 or less, and the diffusion state of Ag be controlled. Thus, even in the range of 0.5≤A / B≤0.8, the warpage of the silicon nitride substrate can be reduced to less than 0.1 mm, and further to less than 0.05 mm, without performing a warpage correction process.

[0060] A through hole may be provided in the ceramic substrate. Preferably, the ceramic copper circuit substrate has a structure in which the front copper circuit board and the back copper circuit board are electrically connected via the through hole. Figure 3 An example of a ceramic circuit substrate having through holes is shown in FIG. Figure 3 It is a cross-sectional view of a portion having a through hole. Figure 3 1 is a ceramic copper circuit substrate, 2 is a ceramic substrate, 3 is a copper circuit board (surface copper board), 4 is a bonding layer, 8 is a back copper circuit board, and 9 is a through hole. Figure 3 In the embodiment, the copper circuit board 3 (front copper circuit board) and the back copper circuit board 8 are connected to each other via the through hole 9. Figure 3 In the embodiment, through holes 9 are provided on each copper circuit board 3. The embodiment is not limited to such a structure. In the ceramic copper circuit substrate 1, through holes 9 may be provided only on a part of the plurality of copper circuit boards 3. The thickness T2 of the copper circuit board is set to the thickest of the thickness of the copper circuit board 3 and the thickness of the back copper circuit board 8.

[0061] It is preferred that the inside of the through hole 9 is filled with the same material as the bonding layer 4. The structure inside the through hole 9 is not particularly limited as long as the surface copper plate and the back copper plate can be connected. Therefore, a metal film may be provided only on the inner wall of the through hole 9. On the other hand, by filling the same material as the bonding layer 4, the bonding strength can be improved. It is preferred that the back copper circuit board 8 has the same structure as the back copper plate 5 described above.

[0062] A metal film may also be provided on the surface of the copper circuit board. The main component of the metal film is one selected from Ni (nickel), Ag (silver) and Au (gold). The metal film is, for example, a plated film or a sputtered film. By providing the metal film, the corrosion resistance can be improved.

[0063] Such a ceramic copper circuit substrate is suitable for a semiconductor device. In the semiconductor device, a semiconductor element is mounted on a copper circuit board of the ceramic copper circuit substrate via a bonding layer.

[0064] Figure 4 An example of a semiconductor device is shown in FIG. Figure 4 In the figure, 1 is a ceramic copper circuit substrate, 10 is a semiconductor device, 11 is a semiconductor element, 12 is a bonding layer, 13 is a bonding wire, and 14 is a metal terminal. Figure 4 In the embodiment, a semiconductor element 11 is bonded to a copper circuit board of a ceramic copper circuit substrate 1 via a bonding layer 12. Similarly, a metal terminal 14 is bonded via the bonding layer 12. Adjacent copper circuit boards are electrically connected to each other via bonding wires 13. Figure 4 In addition to the semiconductor element 11, a bonding lead 13 and a metal terminal 14 are also bonded. The semiconductor device involved in the embodiment is not limited to such a structure. For example, only one of the bonding lead 13 and the metal terminal 14 may be provided. A plurality of semiconductor elements 11, bonding leads 13 and metal terminals 14 may be provided on the copper circuit board 3, respectively. On the back copper circuit board 8, the semiconductor element 11, the bonding lead 13 and the metal terminal 14 are bonded as needed. As the metal terminal 14, various shapes such as a lead frame shape and a convex shape can be adopted.

[0065] As the bonding layer 12 for bonding the semiconductor element 11 or the metal terminal 14, a solder, a brazing material, etc. can be cited. As the solder, a lead-free solder is preferred. The melting point of the solder is preferably 450°C or less. The melting point of the brazing material is preferably 450°C or less. A brazing material having a melting point of 500°C or more is called a high-temperature brazing material. As the high-temperature brazing material, a high-temperature brazing material having Ag as a main component can be cited.

[0066] In the ceramic copper circuit substrate involved in the embodiment, the heat dissipation is excellent because T2 / T1 is 1.25 or more. Since the number of grain boundaries on the surface of the copper circuit board is controlled, the reliability of the bonding layer used to bond semiconductor elements and the like can be improved. In particular, even if the junction temperature of the semiconductor element reaches a high temperature of more than 170°C, the reliability of the bonding between the semiconductor element and the copper circuit board can be maintained. The number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is controlled in a prescribed range. Therefore, high reliability can be obtained regardless of where the semiconductor element, bonding lead or metal terminal is bonded on the surface of the copper circuit board. By improving the reliability of the bonding of semiconductor elements, bonding leads and metal terminals, a semiconductor device with excellent assembly properties can be provided.

[0067] The mounting position of the semiconductor element or the like on the copper circuit board can be detected by image analysis using a CCD camera or the like. The thicker the copper plate becomes, the more difficult it is to detect the position based on the ceramic substrate. Therefore, by making the number of grain boundaries on the surface of the copper circuit board within a prescribed range, it is easy to detect the position of the copper plate surface. That is, according to the embodiment, a ceramic copper circuit board with excellent assemblability can be provided.

[0068] In recent years, semiconductor elements have been developing high performance and miniaturization, and the heat generated from the chip has increased. Therefore, in the ceramic copper circuit substrate equipped with semiconductor elements, it is important to improve the heat dissipation. In order to improve the high performance of the semiconductor device (semiconductor module), it is preferred to install multiple semiconductor elements on the ceramic copper circuit substrate. If any semiconductor element exceeds the intrinsic temperature, the resistance is negative and the temperature coefficient changes to the negative side. Along with this, a thermal runaway occurs in which electricity flows intensively in the semiconductor element, and the semiconductor element is instantly destroyed. Therefore, it is very effective to improve the reliability of the connection between the semiconductor element and the copper circuit board. The semiconductor device involved in the embodiment can be used as a PCU, IGBT or IPM module. PCU, IGBT or IPM modules can be used in converters for automobiles (including electric vehicles), electric railway vehicles, industrial machinery or air conditioners. Regarding automobiles, research on electric vehicles is being devoted to. The higher the reliability of the semiconductor device, the higher the safety of the automobile. The same is true for electric railway vehicles, industrial equipment, etc.

[0069] The manufacturing method of the ceramic copper circuit board according to the embodiment will be described. As long as the ceramic copper circuit board has the above-mentioned structure, the manufacturing method thereof is not particularly limited. As a manufacturing method with a high yield, the following method can be cited.

[0070] First, a ceramic substrate and a copper plate are prepared. The relationship between the thickness T1 of the ceramic substrate and the thickness T2 of the copper plate is T2 / T1≥1.25.

[0071] The ceramic substrate is preferably one selected from an alumina substrate, an aluminum nitride substrate, a silicon nitride substrate, and an Alusil high silicon heat-resistant aluminum alloy substrate. In particular, the ceramic substrate is preferably a silicon nitride substrate having a thermal conductivity of 50 W / m·K or more and a three-point bending strength of 600 MPa or more. As long as it is such a silicon nitride substrate, the substrate thickness can be made less than 0.40 mm. For the copper plate, a copper plate with a thickness of 0.6 mm or more can be used.

[0072] When the copper plate on the front side and the copper plate on the back side are connected through the through hole, a ceramic substrate with a through hole is prepared. When the through hole is provided on the ceramic substrate, the through hole can also be provided in advance at the stage of the formed body. A process of providing the through hole on the ceramic substrate (ceramic sintered body) can also be performed. As the process of providing the through hole, laser processing or cutting processing can be listed. As the cutting processing, a hole opening processing using a drill bit can be listed.

[0073] On the surface of the copper plate, the number of grain boundaries is preferably greater than 10 and less than 300 on any 10 mm straight line. On the surface of the copper plate, the number of grain boundaries is more preferably greater than 50 and less than 120 on any 10 mm straight line. When the ceramic substrate and the copper plate are bonded by the active metal bonding method, the bonding temperature is in the range of 700 to 900°C. If the copper plate is exposed to this temperature, the copper recrystallizes. As a result, the grains grow and the number of grain boundaries decreases. Accordingly, it is preferred to use a copper plate with a number of grain boundaries within the above-specified range.

[0074] It is preferred to join the ceramic substrate and the copper plate using an active metal joining method. In the active metal joining method, an active metal brazing filler metal obtained by mixing an active metal such as Ti and Ag is used. As active metal brazing fillers, mixtures of Ti, Ag (silver), and Cu (copper) can be cited. The content of Ti in the active metal brazing filler metal is greater than 0.1wt% and less than 10wt%, the content of Cu is greater than 10wt% and less than 60wt%, and the remainder is Ag. As required, one or two selected from In (indium) or Sn (tin) may be added to the active metal brazing filler metal at a rate of greater than 1wt% and less than 15wt%.

[0075] The active metal brazing material is paste-formed. The paste can be obtained by mixing the brazing material components and organic matter. The active metal brazing material paste is applied to a ceramic substrate. A copper plate is placed on it. Next, the ceramic substrate and the copper plate are heated at 700 to 900°C to join them. The heating process can be carried out in a vacuum or a non-oxidizing atmosphere as required. When carried out in a vacuum, the preferred pressure is 1×10 -2 Pa or less. As a non-oxidizing atmosphere, a nitrogen atmosphere or an argon atmosphere can be cited. By setting it in a vacuum or a non-oxidizing atmosphere, oxidation of the bonding layer can be suppressed. Thus, the bonding strength can be improved. By adjusting the bonding temperature and time, the number of grain boundaries on the copper plate surface can be adjusted.

[0076] By controlling the number of grain boundaries of the copper plate, Ag is diffused along the grain boundaries. In order to control the diffusion state of Ag, it is preferred that the heating and joining process includes a degreasing process of the active metal solder paste. In the heating and joining process, the temperature range is maintained at 700 to 900°C for joining. Before reaching this temperature, the organic matter in the paste is degreased. In this way, the diffusion amount of Ag can be controlled. This is because if the organic matter in the solder paste is degreased at the joining temperature, the solder connected to the copper plate can be homogenized.

[0077] In the degreasing process of the solder paste, the temperature is maintained in the range of 250 to 450° C. The holding time in this temperature range is preferably in the range of 5 to 60 minutes. As another method, it is also effective to set the heating rate to 10° C. / min or less.

[0078] The copper plate to be joined may be processed into a pattern shape in advance or may not be processed. When an unprocessed copper plate is adopted, it may be processed into a pattern shape by etching the copper plate after joining. When etching is performed, the exposed part of the side shape of the copper plate shown in Patent Document 1 and the solder shown in Patent Document 1 is preferably provided.

[0079] The ceramic copper circuit board can be manufactured through the above process. It is effective to implement chemical polishing treatment for adjusting the surface roughness of the copper circuit board of the obtained ceramic copper circuit substrate. In the chemical polishing treatment, an acidic liquid or an alkaline liquid is used. Through chemical polishing treatment, the surface of the copper circuit board can be evenly polished. Therefore, it is easy to control the arithmetic mean roughness Ra to below 0.4μm, the ten-point average roughness Rzjis to below 4μm, and the maximum height Rz to below 5μm. By adjusting the chemical polishing time, Ra can be made above 0.1μm and below 0.4μm, Rzjis can be made above 1.5μm and below 4μm, and Rz can be made above 1μm and below 5μm. When the above-mentioned surface roughness can be obtained even without implementing chemical polishing treatment, chemical polishing treatment can also be omitted. Chemical polishing treatment can be performed only on the surface of the copper plate used as a circuit. Mask the areas where chemical polishing treatment is not performed.

[0080] Next, a process of bonding the semiconductor element and the like is performed. A bonding layer is provided at the place where the semiconductor element is bonded. Preferably, the bonding layer is a solder or brazing material. A bonding layer is provided, and a semiconductor element is provided thereon. Metal terminals are bonded via the bonding layer as required. Bonding wires are provided as required. The number of semiconductor elements, metal terminals, and bonding wires can be adjusted appropriately.

[0081] In the ceramic copper circuit substrate of the embodiment, the number of grain boundaries on the surface of the copper circuit board is controlled. As a result, excellent reliability can be obtained regardless of where the semiconductor element, metal terminal, and bonding wire are bonded on the surface of the copper circuit board. Therefore, there is no restriction on where the semiconductor element, etc. are mounted on the surface of the copper circuit board. The assembly performance when manufacturing the semiconductor device can be improved.

[0082] It is also easy to detect the position based on the surface of the copper circuit board. Therefore, even when multiple semiconductor elements, metal terminals, bonding leads, etc. are provided, it is difficult for their positions to shift. In other words, the ceramic copper circuit substrate involved in the embodiment is suitable for a semiconductor device in which multiple semiconductor elements, metal terminals, and bonding leads are provided.

[0083] In order to improve the visibility for alignment, identification display may also be performed. As a method for identification display, laser processing or etching processing of the copper circuit board surface, setting a resin layer on the copper circuit board surface, etc. can be listed. When the resin layer is set, a barcode display may also be performed.

[0084] (Example)

[0085] (Examples 1 to 7, Comparative Examples 1 to 2)

[0086] As ceramic substrates, first to third silicon nitride substrates shown in Table 1 were prepared. The size of each ceramic substrate was 50 mm in length×40 mm in width. The third silicon nitride substrate was provided with two through holes with a diameter of 2 mm.

[0087] Table 1

[0088]

[0089] Next, prepare copper plates. Prepare two types of copper plates with a thickness of 0.6 mm and 0.8 mm. Use the active metal bonding method to bond the ceramic substrate and the copper plate. The active metal brazing material used in the active metal bonding method contains 2 wt% Ti, 10 wt% In, 30 wt% Cu, and the remainder is Ag. Apply active metal paste to both sides of the ceramic substrate, place the copper plates, and perform the heating bonding process. Keep the bonding temperature in the range of 780 to 850°C, and set the pressure to 1×10 - 2 Pa or less. The number of grain boundaries on the copper plate surface was adjusted by changing the bonding time. The substrate involved in the embodiment was subjected to a solder paste degreasing process at a temperature maintained in the range of 250 to 450°C. A third silicon nitride substrate was used as a ceramic substrate, and the copper plates were bonded by filling the through holes with active metal solder.

[0090] The front copper plate is etched to form a circuit shape. The front copper plate is formed into 2 to 4 circuit shapes. When the third silicon nitride substrate is used, the back copper plate is also etched to form a circuit shape. The total volume of the copper circuit board (front copper plate) is set to A (mm 3 ), the total volume of the back copper plate is set to B (mm 3 ).

[0091] Table 2 shows the obtained ceramic copper circuit boards.

[0092] Table 2

[0093] Ceramic Substrate Copper plate (thickness T2) T1 / T2 A / B Example 1 First silicon nitride substrate 0.6 1.88 0.8 Example 2 Second silicon nitride substrate 0.6 2.4 0.7 Example 3 Silicon nitride substrate No. 3 0.6 1.88 0.8 Example 4 First silicon nitride substrate 0.8 1.33 0.8 Example 5 Second silicon nitride substrate 0.8 2.4 0.5 Example 6 First silicon nitride substrate 1.2 3.75 0.6 Example 7 Second silicon nitride substrate 1.2 4.8 0.7 Comparative Example 1 First silicon nitride substrate 0.6 1.88 0.8 Comparative Example 2 First silicon nitride substrate 0.6 1.88 0.8

[0094] Next, the surface roughness of the copper circuit board was adjusted by chemical polishing for Examples 1 to 7. No chemical polishing was performed for Comparative Examples 1 and 2. The number of grain boundaries and the surface roughness of the copper circuit board surface of each ceramic copper circuit board were measured.

[0095] When calculating the number of grain boundaries, an enlarged photograph of the copper plate surface was taken. In the enlarged photograph, a 10 mm straight line was drawn at random, and the number of grain boundaries on the straight line was investigated. This operation was measured at 5 locations (5 random 10 mm straight lines), and the maximum and minimum values ​​were shown. In addition, the surface roughness Ra, Rzjis, and Rz were measured based on the provisions of JIS-B-0601 (2001). The results are shown in Table 3.

[0096] Table 3

[0097]

[0098] As can be seen from Table 3, the surface of the copper circuit board of the ceramic copper circuit board according to the example is within the range of the preferred embodiment. On the other hand, the number of grain boundaries in Comparative Example 1 is too small. The number of grain boundaries in Comparative Example 2 is too large.

[0099] Next, the warpage and the diffusion state of Ag in the ceramic copper circuit boards of the examples and comparative examples were investigated. The warpage was measured by drawing a straight line from one end to the other end of the long side of the silicon nitride substrate and taking the distance between the straight line and the silicon nitride substrate as the warpage.

[0100] Regarding the measurement of the diffusion state of Ag, an arbitrary cross section of the copper circuit board is measured by EDX. The dispersion state of Ag in the copper circuit board is depicted by color distribution. The thickness T2 of the copper circuit board is divided into three equal parts, and set as area 3a, area 3b, and area 3c from the side close to the bonding layer. For each area, the unit area of ​​100μm×100μm is measured, and the proportion of Ag in the unit area (diffusion area ratio) is measured. This operation is performed 3 times in each area to calculate the diffusion area ratio of Ag. The results are shown in Table 4.

[0101] Table 4

[0102]

[0103] The warpage of the ceramic copper circuit board according to the example is less than 0.1 mm. Although no warpage correction process is performed, the warpage is small.

[0104] In the ceramic copper circuit board according to the embodiment, the diffusion area ratio of Ag in the region 3a close to the bonding layer is 20% or more and 80% or less. In the region 3b which is the middle region, the diffusion area ratio of Ag is 20% or less (including 0). In the region 3c which is the surface side region, the diffusion area ratio of Ag is 0%.

[0105] In contrast, the warpage amount of the ceramic copper circuit board of Comparative Example 1 was large. The diffusion area ratio of Ag was large in the ceramic copper circuit board of Comparative Example 2. It was found that the number of grain boundaries of the copper plate affects the diffusion state of Ag.

[0106] Next, the ceramic copper circuit boards according to the examples and comparative examples were evaluated for their assemblability. As the evaluation of assemblability, the bonding property and alignment performance of the semiconductor element were evaluated.

[0107] First, the semiconductor element and the metal terminal are joined using lead-free solder. In addition, a joining lead is provided to seek conduction. Thus, a semiconductor device is manufactured. Then, a TCT test is performed on the semiconductor device as a test of bonding, and the incidence of poor conduction is investigated. Two types of TCT (Temperature Cycle Testing) tests were performed. In the first condition, -30℃×30 minutes→room temperature×10 minutes→125℃×30 minutes→room temperature×10 minutes is taken as one cycle, and the incidence of poor conduction after 2000 cycles is investigated. In the second condition, -40℃×30 minutes→room temperature×10 minutes→175℃×30 minutes→room temperature×10 minutes is taken as one cycle, and the incidence of poor conduction after 2000 cycles is investigated.

[0108] Regarding the alignment performance, position detection was performed using a CCD camera, and lead-free solder was applied to target locations on the surface of the copper circuit board. At this time, the proportion of locations where positional deviation of 0.5 mm or more occurred was investigated.

[0109] Table 5 shows the results.

[0110] Table 5

[0111]

[0112] It can be seen from the table that under the first condition (125°C on the high temperature side), poor conduction did not occur in the examples and comparative examples. In contrast, under the second condition (175°C on the high temperature side), there was a difference in the incidence of poor conduction. This is because the wettability and bonding strength of the solder are improved by controlling the number of grain boundaries on the surface of the copper plate. The alignment performance is also improved in the examples. This result shows that the number of grain boundaries on the surface of the copper plate affects the position detectability based on the CCD camera. As in Example 4, when the number of grain boundaries is less than 20 per 10 mm straight line, position offset occurs. When a CCD camera is used for position detection, it is found that the side with a specified number of grain boundaries is effective.

[0113] In contrast, if there are few grain boundaries as in Comparative Example 1, there are more poor conduction under the second condition. This is because the amount of distortion on the copper plate surface increases due to thermal expansion. If there are too many grain boundaries as in Comparative Example 2, the heat dissipation property decreases. If the heat dissipation property decreases, it is difficult to release heat. The poor conduction rate of Comparative Example 2 under the second condition is higher than that of the embodiment because it is difficult to release heat and thermal stress is generated in the bonding layer between the semiconductor element and the copper circuit board.

[0114] Several embodiments of the present invention are illustrated above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are also included in the invention recorded in the claims and their equivalents. In addition, the above-mentioned embodiments can also be implemented by combining with each other.

Claims

1. A ceramic copper circuit substrate, characterized in that: It has: Ceramic substrates, a copper circuit board provided on one surface of the ceramic substrate, A back copper plate provided on the other surface of the ceramic substrate, and A bonding layer is provided between the ceramic substrate and the copper circuit board; wherein, The ratio of the thickness of the copper circuit board to the thickness of the ceramic substrate is greater than 1.25; The number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is greater than 55 and less than 250; The thickness of the copper circuit board is greater than 0.6 mm; The warping amount of the ceramic substrate is less than 0.1 mm; When the total volume of the copper circuit board is set as A and the total volume of the back copper board is set as B, 0.5≤A / B≤0.8, and the units of A and B are mm. 3 .

2. The ceramic copper circuit substrate according to claim 1, characterized in that: The number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is 150 or less.

3. The ceramic copper circuit substrate according to claim 1 or 2, characterized in that: The number of grain boundaries on any 10 mm straight line drawn on the surface of the copper circuit board is 80 or more and 150 or less.

4. The ceramic copper circuit substrate according to claim 1 or 2, characterized in that: The arithmetic mean roughness Ra of the surface of the copper circuit board is greater than or equal to 0.1 μm and less than or equal to 0.4 μm; The ten-point average roughness Rzjis of the surface is greater than or equal to 1.5 μm and less than or equal to 4 μm; The maximum height Rz of the surface is greater than or equal to 1 μm and less than or equal to 5 μm.

5. The ceramic copper circuit substrate according to claim 1 or 2, characterized in that: The skewness Rsk of the roughness curve of the surface of the copper circuit board is lower than 0.

6. The ceramic copper circuit substrate according to claim 1 or 2, characterized in that: The ceramic substrate is any one of an aluminum oxide substrate, an aluminum nitride substrate and a silicon nitride substrate.

7. The ceramic copper circuit substrate according to claim 1 or 2, characterized in that: The bonding layer contains Ag and Ti.

8. The ceramic copper circuit substrate according to claim 7, characterized in that: When the copper circuit board is divided into three equal parts in the thickness direction, a ratio of an area where Ag exists in a region on the bonding layer side of the copper circuit board is 20% or more and 80% or less.

9. A semiconductor device, characterized in that: It has: The ceramic copper circuit substrate according to claim 1 or 2, and A semiconductor element is mounted on the copper circuit board via a bonding layer.

10. The semiconductor device according to claim 9, wherein: The invention further comprises a bonding wire or a metal terminal bonded to the copper circuit board.

11. A semiconductor device, characterized in that: It has: The ceramic copper circuit substrate according to claim 6, and A semiconductor element is mounted on the copper circuit board via a bonding layer.

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