Layout design method, design device and computer readable storage medium

Abstract

The embodiments of the present disclosure disclose a layout design method, a design device, and a computer-readable storage medium, the design method comprising: obtaining an initial layout; generating a first unit layout according to the initial layout, the first unit layout comprising a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout; determining target parameters of a second capacitor layout to be added according to the first capacitor layout; adding the second capacitor layout to the first unit layout according to the target parameters, and connecting the second capacitor layout to the first capacitor layout.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuits, and in particular to a layout design method, a design device, and a computer-readable storage medium. Background Art

[0002] In the layout design of dynamic random access memory (DRAM), designers hope to add more capacitors in a specific area to increase the capacitance value.

[0003] However, layout engineers face many problems such as huge workload, high difficulty and high maintenance cost when adding capacitors manually. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a layout design method is provided, comprising:

[0005] Get the initial layout;

[0006] generating a first unit layout according to the initial layout, wherein the first unit layout includes a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout;

[0007] Determining target parameters of a second capacitor layout to be added according to the first capacitor layout;

[0008] The second capacitor layout is added to the first unit layout according to the target parameters, and the second capacitor layout is connected to the first capacitor layout.

[0009] In some embodiments, the target parameter includes: a target position; the target parameter of the second capacitor layout to be added is determined according to the first capacitor layout, including:

[0010] Determining a first position parameter of the first capacitor layout;

[0011] Determining a second position parameter of the second capacitor layout according to the first position parameter;

[0012] The target position is determined according to the second position parameter.

[0013] In some embodiments, the first capacitor layout includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the first power layout, and the second electrode plate is connected to the second power layout;

[0014] The determining of the first position parameter of the first capacitor layout includes:

[0015] determining a first coordinate parameter of the first electrode plate;

[0016] determining second coordinate parameters of the second electrode plate;

[0017] Determine the first position parameter according to the first coordinate parameter and the second coordinate parameter;

[0018] The design method further comprises:

[0019] Determine a first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter;

[0020] A second placement direction of the second capacitor layout is determined according to the first placement direction, and the second placement direction is the same as the first placement direction.

[0021] In some embodiments, the first coordinate parameters include: a first horizontal coordinate and a first vertical coordinate; the second coordinate parameters include: a second horizontal coordinate and a second vertical coordinate;

[0022] The determining a first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter includes:

[0023] When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate and the second vertical coordinate are different, the first placement direction is determined to be horizontal placement.

[0024] In some embodiments, the second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power layout, and the fourth electrode plate is connected to the second power layout;

[0025] The determining the second position parameter of the second capacitor layout according to the first position parameter includes:

[0026] When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is greater than the second vertical coordinate, it is determined that the vertical coordinate of the third electrode plate is greater than the vertical coordinate of the fourth electrode plate.

[0027] In some embodiments, determining the second position parameter of the second capacitor layout according to the first position parameter further includes:

[0028] When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is smaller than the second vertical coordinate, it is determined that the vertical coordinate of the third electrode plate is smaller than the vertical coordinate of the fourth electrode plate.

[0029] In some embodiments, determining the first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter further includes:

[0030] When the first horizontal coordinate and the second horizontal coordinate are different and the first vertical coordinate and the second vertical coordinate are the same, the first placement direction is determined to be vertical placement.

[0031] In some embodiments, the second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power layout, and the fourth electrode plate is connected to the second power layout;

[0032] The determining the second position parameter of the second capacitor layout according to the first position parameter includes:

[0033] When the first horizontal coordinate is smaller than the second horizontal coordinate and the first vertical coordinate is the same as the second vertical coordinate, it is determined that the horizontal coordinate of the third electrode plate is smaller than the horizontal coordinate of the fourth electrode plate.

[0034] In some embodiments, determining the second position parameter of the second capacitor layout according to the first position parameter further includes:

[0035] When the first horizontal coordinate is greater than the second horizontal coordinate and the first vertical coordinate is the same as the second vertical coordinate, it is determined that the horizontal coordinate of the third electrode plate is greater than the horizontal coordinate of the fourth electrode plate.

[0036] In some embodiments, the target parameter further includes: a target size; and the target parameter of the second capacitor layout to be added is determined according to the first capacitor layout, including:

[0037] Determining a first size parameter of the first capacitor layout;

[0038] Determine a second size parameter of the second capacitor layout according to the first size parameter;

[0039] The target size is determined according to the second size parameter.

[0040] In some embodiments, the first unit layout and the second capacitor layout constitute a second unit layout; and the design method further includes:

[0041] The first unit layout is replaced by the second unit layout.

[0042] In some embodiments, the design method further includes:

[0043] On the initial layout, the first unit layout is replaced by the second unit layout.

[0044] In some embodiments, the first capacitor layout includes: a columnar capacitor layout;

[0045] The second capacitor layout includes: a metal-oxide-semiconductor capacitor layout.

[0046] According to a second aspect of an embodiment of the present disclosure, there is provided a design device for a layout, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the design method as described in any embodiment of the first aspect of the present disclosure is implemented.

[0047] According to a third aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the design method as described in any embodiment of the first aspect of the present disclosure is implemented.

[0048] In the disclosed embodiment, by acquiring an initial layout and generating a first unit layout based on the initial layout, a first capacitor layout between the first power layout and the second power layout can be determined, and target parameters of the second capacitor layout to be added can be determined based on the first capacitor layout. A second capacitor layout connected to the first capacitor layout can be added to a specific area of ​​the first unit layout, which not only increases the capacitance value but also saves manual processing time, which is conducive to improving layout design efficiency.

[0049] Compared with manual processing, the design method provided by the embodiment of the present disclosure reduces the risk of errors in manual addition, which is beneficial to improving the accuracy of layout design and reducing the number of reworks, thereby reducing manpower and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a flow chart of a method for designing an integrated circuit according to an embodiment of the present disclosure;

[0051] Figure 2 A schematic diagram of a design process of an integrated circuit according to an embodiment of the present disclosure is shown. Figure 1 ;

[0052] Figure 3 A schematic diagram of a design process of an integrated circuit according to an embodiment of the present disclosure is shown. Figure 2 ;

[0053] Figure 4 is an equivalent circuit diagram of a first capacitor layout and a second capacitor layout according to an embodiment of the present disclosure;

[0054] Figure 5 is a schematic diagram of a second unit layout according to an embodiment of the present disclosure;

[0055] Figure 6a is an initial layout without adding a second capacitor layout according to an embodiment of the present disclosure;

[0056] Figure 6b It is a new layout with a second capacitor layout added according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0058] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0059] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0060] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0061] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0062] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0063] In the layout design of DRAM, designers hope to add more capacitors under specific capacitance to achieve the purpose of increasing the capacitance value. However, there are many problems for layout engineers to add capacitors manually: 1) The workload is huge; there are thousands of areas in the top-level cell (CELL) that need to manually add capacitors, and the length, width and other dimensions of the capacitors are different, which leads to a huge workload for layout engineers and places high demands on the ability of layout engineers. 2) The work is difficult; due to manual processing, it is difficult to avoid the problem of accidentally connecting capacitors in reverse, and it is not discovered until the physical verification stage, which affects the project progress, and the cost of manpower and time is increased due to rework. 3) The maintenance cost is high; if there is a need for revision in the later stage, the position of the capacitor needs to be repeatedly confirmed, which increases the maintenance cost exponentially.

[0064] In view of this, an embodiment of the present disclosure provides a layout design method.

[0065] Figure 1 is a flow chart of a layout design method according to an embodiment of the present disclosure. Figure 1 As shown, the design method includes at least the following steps:

[0066] S100: Get the initial layout;

[0067] S200: generating a first unit layout according to the initial layout, wherein the first unit layout includes a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout;

[0068] S300: Determine target parameters of a second capacitor layout to be added according to the first capacitor layout;

[0069] S400: Adding a second capacitor layout to the first unit layout according to target parameters, and connecting the second capacitor layout to the first capacitor layout.

[0070] In the disclosed embodiment, by acquiring an initial layout and generating a first unit layout based on the initial layout, a first capacitor layout between the first power layout and the second power layout can be determined, and target parameters of the second capacitor layout to be added can be determined based on the first capacitor layout. A second capacitor layout connected to the first capacitor layout can be added to a specific area of ​​the first unit layout, which not only increases the capacitance value but also saves manual processing time, which is conducive to improving layout design efficiency.

[0071] Compared with manual processing, the design method provided by the embodiment of the present disclosure reduces the risk of errors in manual addition, which is beneficial to improving the accuracy of layout design and reducing the number of reworks, thereby reducing manpower and time costs.

[0072] Figures 2 to 5 is a schematic diagram of a design method of an integrated circuit according to an embodiment of the present disclosure; wherein, Figure 2 This is a schematic diagram of the integrated circuit design process Figure 1 , Figure 3 This is a schematic diagram of the integrated circuit design process. Figure 2 , Figure 4 is the equivalent circuit diagram of the first capacitor layout and the second capacitor layout, Figure 5 This is a schematic diagram of the second unit layout. Figures 2 to 5 The design method of the integrated circuit provided by the embodiment of the present disclosure is further described in detail.

[0073] First, execute step S100: obtain the initial layout. For example, use electronic design automation (EDA) software to obtain the initial layout of the integrated circuit, such as Figure 2 The initial layout includes: various information of the integrated circuit, such as the shape, area, size and position information of each hardware unit.

[0074] Then, step S200 is performed: a first unit layout is generated according to the initial layout, wherein the first unit layout includes a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout.

[0075] The initial layout of the integrated circuit usually includes multiple power layouts, and the multiple power layouts are used to provide multiple power supplies in the integrated circuit. For example, the first power layout is used to provide a first power supply in the integrated circuit, and the second power layout is used to provide a second power supply in the integrated circuit. When the first power supply and the second power supply are used to supply power, the levels provided by the first power supply and the second power supply are different. For example, the first power supply is used to provide a high level or a low level, and the second power supply is used to provide a low level or a high level; for another example, the first power supply is used to provide a high level or a ground level, and the second power supply is used to provide a ground level or a high level.

[0076] In a specific example, the layout engineer can determine a specific first capacitor layout according to the power / ground list in the initial layout, and use EDA software to extract the power layout, the first capacitor layout, and the ground layout in the initial layout to automatically generate the first unit layout, such as Figure 2 shown.

[0077] Still refer to Figure 2 As shown, after the first unit layout is generated, a design rule check (DRC) is performed on the first unit layout. The design rule check is to perform a design rule check on each layer of physical graphics in the generated first unit layout.

[0078] In one example, performing a design rule check on the first unit layout includes: obtaining relevant parameters of all physical graphics on the first unit layout; and checking whether the relevant parameters of these physical graphics meet the process production requirements. Here, the relevant parameters include: the position of the physical graphics and the size of the physical graphics (such as length, width, area, etc.).

[0079] Still refer to Figure 2 As shown, after running the design rule check, a parameter file related to the first capacitor layout is generated, and the parameter file related to the first capacitor layout at least includes: a position parameter of the first capacitor layout and a size parameter of the first capacitor layout.

[0080] Next, step S300 is performed: determining target parameters of the second capacitor layout to be added according to the first capacitor layout. For example, the target parameters can be determined according to the position parameters of the first capacitor layout and the size parameters of the first capacitor layout.

[0081] In some embodiments, the target parameters include: a target position; the step S300 includes: determining a first position parameter of the first capacitor layout; determining a second position parameter of the second capacitor layout according to the first position parameter; and determining the target position according to the second position parameter.

[0082] The first position parameter is used to determine the placement position of the first capacitor layout in the first unit layout, and the second position parameter is used to determine the placement position of the second capacitor layout in the first unit layout. Here, the first position parameter can be determined according to the position parameter of the first capacitor layout, and the second position parameter can be calculated according to the first position parameter to determine the target position.

[0083] In the disclosed embodiment, the second position parameter of the second capacitor layout is determined according to the first position parameter of the first capacitor layout, and then the target position is determined, which is beneficial to improving the accuracy of integrated circuit layout design and reducing the number of rework times.

[0084] In order to convey the present disclosure more clearly, the following description will be made by taking the plate connected to the first power supply layout as a high-level plate and the plate connected to the second power supply layout as a low-level plate as an example, but the present disclosure is not limited to this.

[0085] In some embodiments, the first capacitor layout includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the first power layout, and the second electrode plate is connected to the second power layout;

[0086] The above-mentioned determination of the first position parameter of the first capacitor layout includes:

[0087] determining a first coordinate parameter of the first electrode plate;

[0088] determining a second coordinate parameter of the second electrode plate;

[0089] A first position parameter is determined according to the first coordinate parameter and the second coordinate parameter.

[0090] The first electrode plate is a high-level electrode plate, and the second electrode plate is a low-level electrode plate. According to the above-mentioned related parameter file for generating the first capacitor layout, the first coordinate parameter of the high-level electrode plate and the second coordinate parameter of the low-level electrode plate can be determined respectively, and the placement position of the first capacitor layout in the first unit layout, that is, the first position parameter, can be determined according to the first coordinate parameter and the second coordinate parameter.

[0091] The first coordinate parameter or the second coordinate parameter is composed of a set of one or more coordinate parameters. For example, the first coordinate parameter includes the coordinate parameters of each vertex of the physical figure of the high-level electrode, and the second coordinate parameter includes the coordinate parameters of each vertex of the physical figure of the low-level electrode.

[0092] In some embodiments, the design method further includes: determining a first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter; determining a second placement direction of the second capacitor layout according to the first placement direction, the second placement direction being the same as the first placement direction. For example, the first placement direction may be determined according to the size of the coordinate parameters of the high-level plate and the low-level plate, and the first placement direction may include horizontal placement, vertical placement, or inclined placement, etc.

[0093] In the disclosed embodiment, the first placement direction of the first capacitor layout is determined according to the coordinate parameters of the high-level electrode and the low-level electrode, and then the second placement direction of the second capacitor layout is determined. Since the second placement direction is the same as the first placement direction, it is beneficial to reduce the design area of ​​the layout, thereby reducing the area of ​​the integrated circuit.

[0094] In some embodiments, the first coordinate parameter includes: a first horizontal coordinate and a first vertical coordinate; the second coordinate parameter includes: a second horizontal coordinate and a second vertical coordinate; the above-mentioned determining the first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter includes: when the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate and the second vertical coordinate are different, determining the first placement direction as horizontal placement.

[0095] In one example, the first horizontal coordinate of the high-level plate can be marked as high_x, the first vertical coordinate of the high-level plate can be marked as high_y, and the first coordinate parameter can be (high_x, high_y); the second horizontal coordinate of the low-level plate can be marked as low_x, the second vertical coordinate of the low-level plate can be marked as low_y, and the second coordinate parameter can be (low_x, low_y).

[0096] In one example, refer to Figure 3As shown, when high_x is the same as low_x and high_y is different from low_y, it can be determined that the first capacitor layout is horizontally placed, such as Figure 3 (a) or Figure 3 Here, horizontal placement means that the high-level plate and the low-level plate are parallel to the plane where the layout is located, the high-level plate and the low-level plate extend along a first direction parallel to the plane where the layout is located (for example, the x direction), and the dielectric layer is located between the high-level plate and the low-level plate.

[0097] In some embodiments, the second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power layout, and the fourth electrode plate is connected to the second power layout; the second position parameter of the second capacitor layout is determined according to the first position parameter, including: when the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is greater than the second vertical coordinate, determining that the vertical coordinate of the third electrode plate is greater than the vertical coordinate of the fourth electrode plate. The third electrode plate is a high-level electrode plate, and the fourth electrode plate is a low-level electrode plate.

[0098] When high_x=low_x、high_y>low_y, the first capacitor layout is Figure 3 (a) When the second capacitor layout is placed horizontally, the second capacitor layout is also placed horizontally. For example, the second capacitor layout is located directly below the first capacitor layout, and the ordinate of the third electrode plate is greater than the ordinate of the fourth electrode plate, that is, the third electrode plate is relatively close to Figure 3 (a) The low level plate, the fourth electrode plate is relatively far away Figure 3 The low-level plate in the first capacitor layout and the low-level plate in the second capacitor layout can be electrically connected to the second power layout through metal wiring, and the high-level plate in the first capacitor layout and the high-level plate in the second capacitor layout can be electrically connected to the first power layout.

[0099] Figure 4 The equivalent circuit diagram of the first capacitor layout and the second capacitor layout is shown. Figure 4 As shown, the first electrode plate of the first capacitor C1 and the third electrode plate of the second capacitor C2 are electrically connected to the power supply terminal, and the second electrode plate of the first capacitor C1 and the fourth electrode plate of the second capacitor C2 are electrically connected to the ground terminal. In this way, the first capacitor C1 and the second capacitor C2 can be connected in parallel, which can not only increase the capacitance value, but also help to simplify the design difficulty of metal wiring in the integrated circuit layout.

[0100] In some embodiments, determining the second position parameter of the second capacitor layout according to the first position parameter further includes: when the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is smaller than the second vertical coordinate, determining that the vertical coordinate of the third electrode plate is smaller than the vertical coordinate of the fourth electrode plate.

[0101] When high_x=low_x、high_y<low_y, the first capacitor layout is Figure 3 (b) When the second capacitor layout is placed horizontally, the second capacitor layout is also placed horizontally. For example, the second capacitor layout is located directly below the first capacitor layout, and the vertical coordinate of the third electrode plate is smaller than the vertical coordinate of the fourth electrode plate, that is, the fourth electrode plate is relatively close to Figure 3 (b) The high level plate, the third electrode plate is relatively far away Figure 3 (b) The high level plate.

[0102] In some embodiments, determining the first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter further includes: when the first horizontal coordinate and the second horizontal coordinate are different and the first vertical coordinate and the second vertical coordinate are the same, determining the first placement direction as vertical placement.

[0103] Still refer to Figure 3 As shown, when high_x is different from low_x and high_y is the same as low_y, it can be determined that the first capacitor layout is placed vertically, such as Figure 3 (c) or Figure 3 Here, vertical placement means that the high-level plate and the low-level plate are parallel to the plane where the layout is located, the high-level plate and the low-level plate extend along a second direction parallel to the plane where the layout is located (for example, the y direction), and the dielectric layer is located between the high-level plate and the low-level plate.

[0104] It should be noted that the first direction and the second direction are parallel to the plane where the layout is located, and the first direction and the second direction are perpendicular, and the angle between the first direction and the second direction is 90°. In other embodiments, the first direction and the second direction intersect, and the angle between the first direction and the second direction is an acute angle or an obtuse angle.

[0105] In some embodiments, the second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power supply layout, and the fourth electrode plate is connected to the second power supply layout; the above-mentioned determination of the second position parameter of the second capacitor layout according to the first position parameter includes: when the first horizontal coordinate is smaller than the second horizontal coordinate and the first vertical coordinate and the second vertical coordinate are the same, determining that the horizontal coordinate of the third electrode plate is smaller than the horizontal coordinate of the fourth electrode plate.

[0106] When high_x<low_x、high_y=low_y, the first capacitor layout is Figure 3 (c) When the second capacitor layout is placed vertically, the second capacitor layout is also placed vertically. For example, the second capacitor layout is located directly below the first capacitor layout, and the horizontal coordinate of the third electrode plate is smaller than the horizontal coordinate of the fourth electrode plate, that is, the third electrode plate is relatively close to Figure 3(c) The high level plate, the fourth electrode plate is relatively close to Figure 3 The low level plate in (c), i.e., the third electrode plate, is relatively far away Figure 3 (c) The low level plate, the fourth electrode plate is relatively far away Figure 3 (c) The high level plate.

[0107] In some embodiments, determining the second position parameter of the second capacitor layout according to the first position parameter further includes: when the first horizontal coordinate is greater than the second horizontal coordinate and the first vertical coordinate is the same as the second vertical coordinate, determining that the horizontal coordinate of the third electrode plate is greater than the horizontal coordinate of the fourth electrode plate.

[0108] When high_x>low_x, high_y=low_y, the first capacitor layout is Figure 3 (d) When the second capacitor layout is placed vertically, the second capacitor layout is also placed vertically. For example, the second capacitor layout is located directly below the first capacitor layout, and the horizontal coordinate of the third electrode plate is greater than the horizontal coordinate of the fourth electrode plate, that is, the third electrode plate is relatively close to Figure 3 (d) The high level plate, the fourth electrode plate is relatively close to Figure 3 The low level plate in (d), i.e., the third electrode plate, is relatively far away Figure 3 (d) The low level plate, the fourth electrode plate is relatively far away Figure 3 (d) The high level plate in.

[0109] In some embodiments, the target parameter further includes: target size; the step S300 includes:

[0110] Determining a first size parameter of a first capacitor layout;

[0111] Determine a second size parameter of the second capacitor layout according to the first size parameter;

[0112] The target size is determined according to the second size parameter.

[0113] The first size parameter is used to determine the size of the first capacitor layout in the first unit layout, and the second size parameter is used to determine the size of the second capacitor layout in the first unit layout. Here, the first size parameter can be determined according to the size parameter of the first capacitor layout, and the second size parameter can be calculated according to the first size parameter to determine the target size.

[0114] Next, step S400 is performed: adding a second capacitor layout to the first unit layout according to the target parameters, and connecting the second capacitor layout to the first capacitor layout. Figure 3As shown, the position information of the first capacitor layout can be determined according to the first coordinate parameter and the second coordinate parameter, the vertex coordinates of the second capacitor layout can be calculated according to the position information of the first capacitor layout, and the coordinate parameter information of the second capacitor layout can be generated; the arrangement information of the high and low levels in the first capacitor layout can also be determined according to the first coordinate parameter and the second coordinate parameter, that is, the placement direction of the first capacitor layout, for example, the first capacitor layout is Figure 3 (a) to Figure 3 (d) is placed in any way, the placement direction of the second capacitor layout is determined according to the placement direction of the first capacitor layout, and the steering parameter information of the second capacitor layout is generated. The coordinates and steering parameter information of the generated second capacitor layout are imported into the parameterized cell (Parameterized cell, Pcell) to complete the automatic placement of the second capacitor layout, that is, the second capacitor layout is added to the first unit layout. Then the second capacitor layout is connected to the first capacitor layout, for example, the second capacitor layout is connected in parallel with the first capacitor layout.

[0115] In some embodiments, the first unit layout and the second capacitor layout constitute a second unit layout; the above design method further includes: replacing the first unit layout with the second unit layout. For example, after adding the second capacitor layout, the second unit layout can be generated using EDA software, such as Figure 5 When drawing the integrated circuit layout, the second unit layout can be used as a new parameterized unit, and there is no need to manually add capacitors.

[0116] It should be noted that according to Figure 3 The four exemplary arrangements of the first capacitor layout can generate at least four second unit layouts. During actual drawing, a specific second unit layout can be called according to the arrangement of a specific first capacitor layout, thereby completing the arrangement of capacitors in the integrated circuit.

[0117] In some embodiments, the design method further includes: replacing the first unit layout with the second unit layout on the initial layout. By replacing the first unit layout with the second unit layout on the initial layout, a new integrated circuit layout can be generated, in which the second capacitor layout is added below the first capacitor layout to increase the capacitance value.

[0118] In some embodiments, the first capacitor layout includes: a columnar capacitor layout; the second capacitor layout includes: a metal-oxide-semiconductor capacitor (MOS cap) layout. When the second capacitor layout is a metal-oxide-semiconductor capacitor (MOS cap) layout, the gate in the second capacitor layout is the third electrode plate, and part of the substrate in the second capacitor layout is the fourth electrode plate.

[0119] In some embodiments, the above layout design method is used to make a layout of an integrated circuit, for example, a layout of a dynamic random access memory.

[0120] Figure 6a and Figure 6b are two integrated circuit layouts shown according to the embodiments of the present disclosure; wherein, Figure 6a is the initial layout without adding the second capacitor layout, Figure 6b In order to add a new layout with a second capacitor layout, the layout design method provided by the embodiment of the present disclosure determines the target parameters of the second capacitor layout to be added through the first capacitor layout, and adds the second capacitor layout in the first unit layout according to the target parameters, so as to complete the automatic placement of the second capacitor layout, use the new second unit layout as a parameterized unit, and automatically add capacitors to thousands of areas of the top unit, such as Figure 6b As shown in the dotted box, the workload is greatly reduced and the accuracy of the layout design is high. In addition, all the second capacitor layouts in the new integrated circuit layout are at the same level, which is convenient for later processing and maintenance, thereby reducing the maintenance cost.

[0121] It should be noted that those skilled in the art can change the order of the above steps without departing from the protection scope of the present disclosure.

[0122] An embodiment of the present disclosure provides a design device for a layout, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a design method in any of the above embodiments is implemented, for example: obtaining an initial layout; generating a first unit layout according to the initial layout, the first unit layout including a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout; determining target parameters of a second capacitor layout to be added according to the first capacitor layout; adding the second capacitor layout in the first unit layout according to the target parameters, and connecting the second capacitor layout to the first capacitor layout.

[0123] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the design method in any of the above embodiments is implemented, for example: obtaining an initial layout; generating a first unit layout according to the initial layout, the first unit layout including a first power layout, a second power layout and a first capacitor layout located between the first power layout and the second power layout; determining target parameters of a second capacitor layout to be added according to the first capacitor layout; adding the second capacitor layout in the first unit layout according to the target parameters, and connecting the second capacitor layout to the first capacitor layout.

[0124] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A layout design method, characterized in that: include: Get the initial layout; generating a first unit layout according to the initial layout, wherein the first unit layout includes a first power layout, a second power layout, and a first capacitor layout located between the first power layout and the second power layout; Determining target parameters of a second capacitor layout to be added according to the first capacitor layout; Adding the second capacitor layout to the first unit layout according to the target parameters, and connecting the second capacitor layout to the first capacitor layout; Wherein, the target parameters include: target position; the target parameters of the second capacitor layout to be added are determined according to the first capacitor layout, including: Determine a first position parameter of the first capacitor layout, where the first position parameter is used to determine a placement position of the first capacitor layout in the first unit layout; Determine a second position parameter of the second capacitor layout according to the first position parameter, wherein the second position parameter is used to determine a placement position of the second capacitor layout in the first unit layout; The target position is determined according to the second position parameter.

2. The design method according to claim 1, characterized in that: The first capacitor layout includes a first electrode plate and a second electrode plate, the first electrode plate is connected to the first power layout, and the second electrode plate is connected to the second power layout; The determining of the first position parameter of the first capacitor layout includes: determining a first coordinate parameter of the first electrode plate; determining second coordinate parameters of the second electrode plate; Determine the first position parameter according to the first coordinate parameter and the second coordinate parameter; The design method further comprises: Determine a first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter; A second placement direction of the second capacitor layout is determined according to the first placement direction, and the second placement direction is the same as the first placement direction.

3. The design method according to claim 2, characterized in that: The first coordinate parameters include: a first horizontal coordinate and a first vertical coordinate; the second coordinate parameters include: a second horizontal coordinate and a second vertical coordinate; The determining a first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter includes: When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate and the second vertical coordinate are different, the first placement direction is determined to be horizontal placement.

4. The design method according to claim 3, characterized in that: The second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power layout, and the fourth electrode plate is connected to the second power layout; The determining the second position parameter of the second capacitor layout according to the first position parameter includes: When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is greater than the second vertical coordinate, it is determined that the vertical coordinate of the third electrode plate is greater than the vertical coordinate of the fourth electrode plate.

5. The design method according to claim 4, characterized in that: The determining of the second position parameter of the second capacitor layout according to the first position parameter also includes: When the first horizontal coordinate and the second horizontal coordinate are the same and the first vertical coordinate is smaller than the second vertical coordinate, it is determined that the vertical coordinate of the third electrode plate is smaller than the vertical coordinate of the fourth electrode plate.

6. The design method according to claim 3, characterized in that: The determining the first placement direction of the first capacitor layout according to the first coordinate parameter and the second coordinate parameter also includes: When the first horizontal coordinate and the second horizontal coordinate are different and the first vertical coordinate and the second vertical coordinate are the same, the first placement direction is determined to be vertical placement.

7. The design method according to claim 6, characterized in that: The second capacitor layout includes: a third electrode plate and a fourth electrode plate, the third electrode plate is connected to the first power layout, and the fourth electrode plate is connected to the second power layout; The determining the second position parameter of the second capacitor layout according to the first position parameter includes: When the first horizontal coordinate is smaller than the second horizontal coordinate and the first vertical coordinate is the same as the second vertical coordinate, it is determined that the horizontal coordinate of the third electrode plate is smaller than the horizontal coordinate of the fourth electrode plate.

8. The design method according to claim 7, characterized in that: The determining of the second position parameter of the second capacitor layout according to the first position parameter also includes: When the first horizontal coordinate is greater than the second horizontal coordinate and the first vertical coordinate is the same as the second vertical coordinate, it is determined that the horizontal coordinate of the third electrode plate is greater than the horizontal coordinate of the fourth electrode plate.

9. The design method according to claim 1, characterized in that: The target parameters also include: target size; the target parameters of the second capacitor layout to be added are determined according to the first capacitor layout, including: Determining a first size parameter of the first capacitor layout; Determine a second size parameter of the second capacitor layout according to the first size parameter; The target size is determined according to the second size parameter.

10. The design method according to claim 1, characterized in that: The first unit layout and the second capacitor layout constitute a second unit layout; the design method further includes: The first unit layout is replaced by the second unit layout.

11. The design method according to claim 10, characterized in that: The design method further comprises: On the initial layout, the first unit layout is replaced by the second unit layout.

12. The design method according to claim 1, characterized in that: The first capacitor layout includes: a columnar capacitor layout; The second capacitor layout includes: a metal-oxide-semiconductor capacitor layout.

13. A layout design device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the design method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the design method according to any one of claims 1 to 12 is implemented.

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