Shift register, gate drive circuit and pixel drive method

Abstract

The present application provides a shift register, a gate drive circuit and a pixel drive method, wherein the shift register comprises: an input module, a first pull-down control module, a first pull-down module, a first output control module and an output module; the control end, the first end and the second end of the input module are electrically connected to the first clock signal end, the first level signal end and the first node respectively; the control end, the first end and the second end of the first pull-down control module are electrically connected to the first selection signal end, the first node and the second node respectively; the control end, the first end and the second end of the first pull-down module are electrically connected to the second node, the third node and the second level signal end respectively; the first control end, the second control end, the first end and the second end of the first output control module are electrically connected to the first clock signal end, the control signal end, the first level signal end and the third node respectively. The technical solution of the present application can randomly compensate a certain pixel row, and takes up less space, which is conducive to realizing a narrow frame.

Description

Technical Field

[0001] The present application relates to display driving technology, and in particular to a shift register, a gate driving circuit and a pixel driving method. Background Art

[0002] In some display products, light-emitting devices are required to emit light. The light-emitting current required by the light-emitting devices is provided by driving transistors. In order to ensure the uniformity of product light emission, it is necessary to increase the consistency of device characteristics. Usually, external compensation is performed through a GOA (GateDriver On Array, array substrate row drive) circuit to increase the consistency of the device. The existing external compensation method is prone to produce compensation horizontal stripes or increase the product border. Summary of the invention

[0003] The embodiments of the present application provide a shift register, a gate driving circuit and a pixel driving method to solve the problems existing in the related art. The technical solutions are as follows:

[0004] In a first aspect, an embodiment of the present application provides a shift register, comprising: an input module, a first pull-down control module, a first pull-down module, a first output control module, and an output module;

[0005] The control end, the first end, and the second end of the input module are electrically connected to the first clock signal end, the first level signal end, and the first node respectively;

[0006] The control end, the first end and the second end of the first pull-down control module are electrically connected to the first selection signal end, the first node and the second node respectively;

[0007] The control end, the first end and the second end of the first pull-down module are electrically connected to the second node, the third node and the second level signal end respectively;

[0008] The first control end, the second control end, the first end, and the second end of the first output control module are electrically connected to the first clock signal end, the control signal end, the first level signal end, and the third node respectively;

[0009] The control end and the first end of the output module are electrically connected to the third node and the second clock signal end respectively, and the second end of the output module is the output end of the shift register.

[0010] In a second aspect, an embodiment of the present application provides a pixel driving method, which is applied to the shift register provided in any embodiment of the present application, and the pixel driving method includes:

[0011] In the blanking phase, based on the first clock signal and the first selection signal, the potential of the second node is adjusted through the input module and the first pull-down control module;

[0012] Based on the first clock signal, the potential of the second node and the control signal, the output of the compensation driving signal is controlled by the first output control module and the output module.

[0013] In a third aspect, an embodiment of the present application provides a gate driving circuit, comprising: a plurality of shift register groups, each shift register group comprising a plurality of shift registers provided by any embodiment of the present application;

[0014] The same type of clock signal terminals in the same shift register group are used to respectively access m clock signal electrical connections; the same shift register group includes mn-m+1 shift registers to the mnth register, where n is a positive integer and m is an integer greater than 2;

[0015] The same type of selection signal terminals in the same shift register are used to access the same selection signal, different types of selection signal terminals are used to access different selection signal terminals for electrical connection, and some of the same type of selection signal terminals in different shift register groups are used to access different selection signal terminals for electrical connection.

[0016] In a fourth aspect, an embodiment of the present application provides a pixel driving method, which is applied to the gate driving circuit provided in an embodiment of the present application. The pixel driving method includes:

[0017] Based on multiple clock signals and multiple strobe signals, a shift register is randomly controlled to output a compensation driving signal during a blanking phase; and frequencies of some strobe signals in the multiple strobe signals are different.

[0018] The advantages or beneficial effects of the above technical solution include at least:

[0019] According to the technical solution provided by the embodiment of the present application, the input module and the first pull-down control module of the shift register can adjust the potential of the second node based on the signal of the first clock signal end and the signal of the first selection signal end, and then adjust the potential of the third node, so that based on the potential of the third node, a compensation drive signal can be output to the connected pixel row without being cascaded with other shift registers. When applied to the gate drive circuit, a certain pixel row can be compensated randomly, and less space is occupied, which is conducive to achieving a narrow border.

[0020] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0022] Figure 1 Schematic diagram of driving signals for the first three rows of pixels in the related art;

[0023] Figure 2 A schematic diagram of a circuit principle of a shift register in the related art;

[0024] Figure 3 A schematic diagram of the structural framework of a shift register provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a circuit principle of a shift register provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structural framework of another shift register provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of a structural framework of another shift register provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a process of a pixel driving method provided in an embodiment of the present application;

[0029] Figure 8 A timing diagram of signals corresponding to the shift register provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of the structural framework of a gate drive circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0032] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0033] The inventors of the present application discovered during their research that the pixel circuits of some display products in the related art usually adopt a 3T1C (three thin-film transistors and one capacitor) design. The normal display of the display product requires a light-emitting device to emit light, and the light-emitting current required by the light-emitting device is provided by a driving transistor. In order to increase the uniformity of the product's light emission, it is necessary to increase the consistency of the device characteristics. External compensation is usually performed through a GOA circuit (also called a shift register) to increase the consistency of the device.

[0034] In a related art, the driving signal of the external compensation is composed of a line shift signal and a frame shift signal. Figure 1 1 shows the driving signals of the first row of pixels, the second row of pixels and the third row of pixels, Figure 1 In the compensation method of sequential frame shift, the signal of the blanking stage (BlankingTime) of a frame is a frame shift signal. The frame shift is divided into sequential frame shift and random frame shift. In the compensation method of sequential frame shift, the gate drive circuit can output drive signals to pixels row by row to compensate the drive transistors of the pixels. In the compensation method of random frame shift, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the drive transistors of the pixels. Among them, the compensation method of sequential frame shift is prone to produce compensation horizontal stripes, resulting in poor display.

[0035] In another related technique, the Figure 2 The GOA circuit shown is used to realize random frame shifting instead of sequential frame shifting. The circuit needs to add the devices shown in the dotted box and needs to be cascaded with other GOA circuits. For example, for the current Nth row (N is an integer greater than 3) GOA circuit, it is necessary to access the output signal C[N-3] of the N-3th row to realize cascading. This circuit will take up more space and thus increase the border of the display product, reducing the product yield.

[0036] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The technical solution of the present application can be applied to display products including any one or more light-emitting devices, and the above-mentioned light-emitting devices can be organic light-emitting diodes (Organic Light-Emitting Diode, OLED), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLED) or micro light-emitting diodes (Micro Light Emitting Diodes, Micro LED), etc.

[0037] The present application embodiment provides a shift register, such as Figure 3 As shown, the shift register includes: an input module 310 , a first pull-down control module 320 , a first pull-down module 330 , a first output control module 340 and an output module 350 .

[0038] The control end, the first end and the second end of the input module 310 are electrically connected to the first clock signal end CLKA, the first level signal end VGH and the first node O respectively; the control end, the first end and the second end of the first pull-down control module 320 are electrically connected to the first selection signal end DA, the first node O and the second node QB respectively; the control end, the first end and the second end of the first pull-down module 330 are electrically connected to the second node QB, the third node Q and the second level signal end VGL respectively; the first control end, the second control end, the first end and the second end of the first output control module 340 are electrically connected to the first clock signal end CLKA, the control signal end P, the first level signal end VGH and the third node Q respectively; the control end and the first end of the output module 350 are electrically connected to the third node Q and the second clock signal end CLKB respectively, and the second end of the output module 350 is the output end Gout of the shift register.

[0039] The shift register provided in the embodiment of the present application, the input module 310 and the first pull-down control module 320 can adjust the potential of the second node QB based on the signal of the first clock signal terminal CLKA and the signal of the first selection signal terminal D, and then adjust the potential of the third node Q, so that based on the potential of the third node Q, a compensation drive signal can be output to the connected pixel row without cascading with other shift registers. When applied to the gate drive circuit, it is beneficial to realize the compensation of random frame shift, and it occupies less space, which is conducive to realizing a narrow border.

[0040] Optional, see Figure 4The input module 310 may include a first transistor T1, and the control electrode, the first electrode, and the second electrode of the first transistor T1 may respectively serve as the control terminal, the first terminal, and the second terminal of the input module 310, and are respectively electrically connected to the first clock signal terminal CLKA, the first level signal terminal VGH, and the first node O. When the clock signal provided by the first clock signal terminal CLKA is at a high potential, the first transistor T1 is turned on, and the potential of the first node O can be adjusted based on the signal provided by the first level signal terminal VGH. When the clock signal provided by the first clock signal terminal CLKA is at a low level, the first transistor T1 is turned off, and the potential of the first node O cannot be adjusted.

[0041] Optionally, the first pull-down control module 320 includes at least one first gating unit; the control end, the first end, and the second end of each first gating unit are electrically connected to the corresponding first gating signal end, the first node, and the second node QB, respectively. That is, when multiple first gating units are included, the multiple first gating units are connected in parallel.

[0042] Each first selection unit may include a transistor, and the control electrode, first electrode and second electrode of the transistor serve as the control end, first end and second end of the first selection unit respectively, and are electrically connected to the corresponding first selection signal end, first node O and second node QB respectively.

[0043] The number of first gating units in the first pull-down control module 320 can be determined according to the number of pixel rows that the gate drive circuit to which it belongs needs to drive. For a gate drive circuit, if the number of pixel rows that need to be driven is 4, the number of first gating units in a shift register of the gate drive circuit can be 1, and the first gating unit can be connected to a gating signal. If the gate drive circuit corresponds to 4 clock signals, and the clock connected to the first clock signal end of different shift registers changes between 4 clock signals, then the gate drive circuit can drive 4 pixel rows through the coordination of the gating signal and the 4 clock signals; if the number of pixel rows that need to be simultaneously gated is 16 rows, also taking 4 clock signals as an example, 2 parallel first gating units can be set in a shift register of the gate drive circuit, and 2 gating signals are connected. Through the coordination of the 2 gating signals and the 4 clock signals, the gate drive circuit can drive 16 pixel rows.

[0044] Optionally, the number of first gating units is less than or equal to 6.

[0045] On the basis of determining the number of first gating units according to the number of pixel rows that the gate driving circuit needs to drive simultaneously, the leakage of the second node QB needs to be considered. When the number of first gating units is too large, the second node QB is more likely to leak. The inventor of the present application has found through research that when the number of first gating units is less than or equal to 6, the gate driving circuit can drive more pixel rows, and the leakage of the second node QB can be reduced. At the same time, controlling the number of first gating units within a certain range can reduce the parasitic capacitance of the connection end of the input module and the first gating unit, thereby reducing the delay of the signal and improving the response speed of the second node QB.

[0046] Reference Figure 4 In the example of , the number of the first selection units can be 4, each of which includes a transistor, namely, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5, and the four transistors can be electrically connected to the four first selection signal terminals. Among them, the second transistor T2 can be electrically connected to the first first selection signal terminal ( Figure 4 The third transistor T3 can be electrically connected to the second first selection signal terminal ( Figure 4 The fourth transistor T4 can be electrically connected to the third first selection signal terminal ( Figure 4 The fifth transistor T5 can be electrically connected to the fourth first selection signal terminal ( Figure 4 The D3 terminal in the circuit is electrically connected.

[0047] Reference Figure 5 In the example of , the number of the first selection units can be 6, each of which includes a transistor, namely a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the six transistors can be electrically connected to the six first selection signal terminals. Among them, the second transistor T2 can be electrically connected to the first first selection signal terminal ( Figure 5 The third transistor T3 can be electrically connected to the second first selection signal terminal ( Figure 5 The fourth transistor T4 can be electrically connected to the third first selection signal terminal ( Figure 5 The fifth transistor T5 can be electrically connected to the fourth first selection signal terminal ( Figure 5 The sixth transistor T6 can be electrically connected to the fifth first selection signal terminal ( Figure 5 The seventh transistor T7 can be electrically connected to the sixth first selection signal terminal ( Figure 5 The D5 terminal in the circuit is electrically connected.

[0048] Optionally, the frequencies of the selection signals provided by the first selection signal terminals are successively reduced. Figure 4 Taking the four first selection signal terminals shown as examples, the frequency of the signal provided by the D1 terminal (hereinafter referred to as the D1 signal) can be smaller than the frequency of the signal provided by the D0 terminal (hereinafter referred to as the D0 signal), for example, it can be half of the frequency of the D0 signal. The frequency of the signal provided by the D2 terminal (hereinafter referred to as the D2 signal) can be smaller than the frequency of the signal provided by the D1 terminal (hereinafter referred to as the D1 signal), for example, it can be half of the frequency of the D1 signal. The frequency of the signal provided by the D3 terminal (hereinafter referred to as the D3 signal) can be smaller than the frequency of the signal provided by the D2 terminal (hereinafter referred to as the D2 signal), for example, it can be half of the frequency of the D2 signal.

[0049] Optionally, the pulse width of the selection signal provided by each first selection signal terminal increases sequentially. Figure 4 Taking the signals provided by the four first selection signal terminals as an example, the pulse width of the D1 signal can be greater than the pulse width of the D0 signal, for example, it can be twice the pulse width of the D0 signal, the pulse width of the D2 signal can be greater than the pulse width of the D1 signal, for example, it can be twice the pulse width of the D1 signal, and the pulse width of the D3 signal can be greater than the pulse width of the D2 signal, for example, it can be twice the pulse width of the D2 signal.

[0050] In an optional embodiment, referring to Figure 4 and Figure 5 , the first pull-down module 330 provided in the embodiment of the present application may include an eighth transistor T8 and a first capacitor C1. The control electrode of the eighth transistor T8 and the first end of the first capacitor C1 serve together as the control end of the first pull-down module 330, and are electrically connected to the second node QB; the first electrode of the eighth transistor T8 serves as the first end of the first pull-down module 330, and is electrically connected to the third node Q; the second electrode of the eighth transistor T8 and the second end of the first capacitor C1 serve together as the second end of the first pull-down module 330, and are electrically connected to the second level signal end VGL. When the potential of the second node QB is high, the eighth transistor T8 is turned on, and the potential of the third node Q is pulled down based on the low level signal provided by the second level signal end VGL, and the first capacitor C1 can be charged; when the potential of the second node QB is low, the eighth transistor T8 is turned off, and the potential of the third node Q cannot be pulled down.

[0051] In another optional implementation, the first pull-down module 330 in the embodiment of the present application may further include a third end, and the third end of the first pull-down module 330 may be electrically connected to the control signal end P.

[0052] Reference Figure 4 and Figure 5In the example of, on the basis of the eighth transistor T8 and the first capacitor C1, the first pull-down module 330 may further include: a ninth transistor T9. The control electrode of the ninth transistor T9, the control electrode of the eighth transistor T8 and the first end of the first capacitor C1 may be used together as the control end of the first pull-down module, electrically connected to the second node QB; the first electrode of the ninth transistor T9 and the third end of the first pull-down module 330 are electrically connected to the control signal end P; the second electrode of the ninth transistor T9, the second electrode of the eighth transistor T8 and the second end of the first capacitor C1 are used together as the second end of the first pull-down module 330, electrically connected to the second level signal end VGL. When the potential of the second node QB is high, the ninth transistor T9 is turned on, and the potential of the control signal end P is pulled down based on the low level signal provided by the second level signal end VGL; when the potential of the second node QB is low, the ninth transistor T9 is turned off, and the potential of the control signal end P cannot be pulled down.

[0053] In yet another optional implementation, the first pull-down module 330 in the embodiment of the present application may further include a fourth end, and the fourth end of the first pull-down module 330 may be electrically connected to the output end Gout.

[0054] Reference Figure 4 and Figure 5 In the example of, on the basis of the eighth transistor T8, the ninth transistor T9 and the first capacitor C1, the first pull-down module 330 may further include: a tenth transistor T10. The control electrode of the tenth transistor T10, the control electrode of the eighth transistor T8, the control electrode of the ninth transistor T9 and the first end of the first capacitor C1 may be used together as the control end of the first pull-down module, electrically connected to the second node QB; the first electrode of the tenth transistor T10 and the fourth end of the first pull-down module 330 are electrically connected to the output end Gout; the second electrode of the tenth transistor T10, the second electrode of the eighth transistor T8, the second electrode of the ninth transistor T9 and the second end of the first capacitor C1 are used together as the second end of the first pull-down module 330, electrically connected to the second level signal end VGL. When the potential of the second node QB is high, the tenth transistor T10 is turned on, and the potential of the output end Gout is pulled down based on the low level signal provided by the second level signal end VGL; when the potential of the second node QB is low, the tenth transistor T10 can be turned off, and the potential of the output end Gout cannot be pulled down.

[0055] Reference Figure 4 and Figure 5For example, the first output control module 340 in the embodiment of the present application may include: an eleventh transistor T11, a twelfth transistor T12, and a second capacitor C2. The control electrode of the eleventh transistor T11 serves as the first control terminal of the first output control module 340, and is electrically connected to the first clock signal terminal CLKA; the control electrode of the twelfth transistor T12 and the first end of the second capacitor C2 serve together as the second control terminal of the first output control module 340, and are electrically connected to the control signal terminal P; the first electrode of the eleventh transistor T11 and the second end of the second capacitor C2 may serve together as the first end of the first output control module 340, and be electrically connected to the first level signal terminal VGH; the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the twelfth transistor T12; the second electrode of the twelfth transistor T12 serves as the second end of the first output control module 340, and is electrically connected to the third node Q.

[0056] When the signal provided by the first clock signal terminal CLKA and the signal provided by the control signal terminal P are both at a high potential, the eleventh transistor T11 and the twelfth transistor T12 can be turned on, and the potential of the third node Q can be raised based on the high potential signal provided by the first level signal terminal VGH; when the signal provided by at least one port of the first clock signal terminal CLKA and the control signal terminal P is at a low level, at least one of the eleventh transistor T11 and the twelfth transistor T12 is turned off, and the potential of the third node Q cannot be raised, and the third node Q can maintain the potential before being turned off; the second capacitor C2 can be used to store charge.

[0057] Reference Figure 4 and Figure 5 For example, the output module 350 in the embodiment of the present application may include: a thirteenth transistor T13 and a third capacitor C3. The control electrode of the thirteenth transistor T13 and the first end of the third capacitor C3 serve together as the control end of the output module 350, and are electrically connected to the third node Q; the first electrode of the thirteenth transistor T13 serves as the first end of the output module 350, and is electrically connected to the second clock signal end CLKB; the second electrode of the thirteenth transistor T13 and the second end of the third capacitor C3 serve together as the second end of the output module 350, that is, the output end Gout of the shift register.

[0058] Optionally, the shift register may further include: a second output control module 360. The first control terminal, the second control terminal, and the first terminal of the second output control module 360 ​​are electrically connected to the third clock signal terminal CLKC, the second selection signal terminal, and the first level signal terminal VGH respectively; the second terminal of the second output control module 360, as the control signal terminal P, is electrically connected to the second control terminal of the first output control module 340.

[0059] The second output control module 360 ​​can adjust the potential of the control signal terminal P based on the clock signal provided by the third clock signal terminal CLKC and the selection signal provided by the second selection signal terminal, and then control the first output control module 340 to adjust the potential of the third node Q, thereby adjusting the output of the shift register.

[0060] Optional, such as Figure 4 and Figure 5 As shown, the second output control module 360 ​​includes: a pull-up unit and a second gating unit. The control end, the first end, and the second end of the pull-up unit are electrically connected to the third clock signal end CLKC, the first level signal end VGH, and the first end of the second gating unit respectively; the control end of the second gating unit is electrically connected to the second gating signal end, and the second end of the second gating unit is used as the control signal end P and is electrically connected to the second control end of the first output control module 340.

[0061] In the embodiment of the present application, based on the pull-up unit and the second selection unit, the potential of the control signal terminal P can be adjusted under the coordinated control of the clock provided by the third clock signal CLKC and the selection signal provided by the second selection signal terminal, and then combined with the on and off of the first pull-down control module 320, a row of pixels can be randomly selected for compensation to achieve random frame shift.

[0062] Reference Figure 4 and Figure 5 In the example of, the pull-up unit may include a fourteenth transistor T14, the control electrode, the first electrode, and the second electrode of the fourteenth transistor T14 respectively serve as the control end, the first end, and the second end of the pull-up unit, and are respectively electrically connected to the third clock signal end CLKC, the first level signal end VGH, and the first end of the second gating unit. When the clock signal provided by the third clock signal end CLKC is a high potential, the fourteenth transistor T14 is turned on, and the high potential provided by the first level signal end VGH is transmitted to the first end of the second gating unit.

[0063] Reference Figure 4 and Figure 5 In the example of , the second gating unit may include at least one transistor. When the second gating unit includes one transistor, the control electrode, the first electrode, and the second electrode of the transistor may be used as the control end, the first end, and the second end of the second gating unit, respectively; when the second gating unit includes multiple transistors, the control electrodes of the multiple transistors may be used together as the control end of the second gating unit, and the multiple transistors may be connected in series, for example, the second electrode of the first transistor is electrically connected to the first electrode of the second transistor, the second electrode of the second transistor is electrically connected to the first electrode of the third transistor, the first electrode of the first transistor connected in series may be used as the first end of the second gating unit, and the second electrode of the second transistor connected in series may be used as the second end of the second gating unit.

[0064] The sum of the number of transistors in the second gating unit and the number of the first gating units (total number) can be determined according to the number of pixel rows that the gate drive circuit needs to drive. For a gate drive circuit, if the number of pixel rows that need to be driven is 16, then in a shift register of the gate drive circuit, the sum of the number of first gating units and the number of transistors in the second gating unit can be 2, and 2 gating signals can be connected. If the gate drive circuit corresponds to 4 clock signals, and the clocks connected to the first clock signal terminals of different shift registers change between the 4 clock signals, then the gate drive circuit can drive 16 pixel rows through the coordination of the 2 gating signals and the 4 clock signals. The total number of transistors in the second gating unit and the first gating unit can be increased or decreased according to actual conditions, so that different resolutions can be achieved. The more the total number, the higher the achievable resolution.

[0065] After determining the sum of the number of transistors in the second gating unit and the number of the first gating unit, the number of transistors in the second gating unit and the number of the first gating unit can be arbitrarily allocated, or the number of the first gating unit can be first determined according to the number limit of the first gating unit, and then the number of the second gating unit can be determined based on the number of the first gating unit and the total number.

[0066] Reference Figure 4 In the example of , the number of transistors in the second selection unit can be 4, namely the 15th transistor T15, the 16th transistor T16, the 17th transistor T17 and the 18th transistor T18, and the 4 transistors can be electrically connected to the 4 second selection signal terminals respectively. Among them, the 15th transistor T15 can be electrically connected to the first second selection signal terminal ( Figure 4 The sixteenth transistor T16 can be electrically connected to the second second selection signal terminal ( Figure 4 The seventeenth transistor T17 can be electrically connected to the third second selection signal terminal ( Figure 4 The eighteenth transistor T18 can be electrically connected to the fourth second selection signal terminal ( Figure 4 The D9' end in the circuit is electrically connected.

[0067] Optionally, the frequencies of the selection signals provided by the second selection signal terminals are successively reduced. Figure 4Taking the four second selection signal terminals shown as examples, the frequency of the signal provided by the D5' terminal (hereinafter referred to as the D5 signal) can be smaller than the frequency of the signal provided by the D4' terminal (hereinafter referred to as the D4' signal), for example, it can be half of the frequency of the D4' signal. The frequency of the signal provided by the D6' terminal (hereinafter referred to as the D6' signal) can be smaller than the frequency of the signal provided by the D5' terminal (hereinafter referred to as the D5' signal), for example, it can be half of the frequency of the D5' signal. The frequency of the signal provided by the D7' terminal (hereinafter referred to as the D7' signal) can be smaller than the frequency of the signal provided by the D6' terminal (hereinafter referred to as the D6' signal), for example, it can be half of the frequency of the D6' signal.

[0068] Optionally, the pulse width of the selection signal provided by each second selection signal terminal increases sequentially. Figure 4 Taking the signals provided by the four second selection signal terminals shown as an example, the pulse width of the D5' signal can be greater than the pulse width of the D4' signal, for example, it can be twice the pulse width of the D4' signal, the pulse width of the D6' signal can be greater than the pulse width of the D5' signal, for example, it can be twice the pulse width of the D5' signal, and the pulse width of the D7' signal can be greater than the pulse width of the D6' signal, for example, it can be twice the pulse width of the D6' signal.

[0069] Optional, such as Figure 6 As shown, the shift register provided in the embodiment of the present application may further include a first anti-leakage module 370. The control end of the first anti-leakage module 370 is electrically connected to the second node QB, at least one end of the first anti-leakage module 370 is electrically connected to at least one end of the first pull-down module 330, and the other end of the first anti-leakage module 370 is electrically connected to the second level signal end VGL.

[0070] Reference Figure 6 In the example of FIG. 3 , the first leakage protection module 370 includes at least one transistor of the nineteenth transistor T19 and the twentieth transistor T20 .

[0071] In the case where the first anti-leakage module 370 includes the nineteenth transistor T19, the control electrode of the nineteenth transistor T19 can serve as the control terminal of the first anti-leakage module 370 and be electrically connected to the second node QB, the first electrode of the nineteenth transistor T19 can be electrically connected to the second electrode of the eighth transistor T8 in the first pull-down module 330, and the second electrode of the nineteenth transistor T19 can be electrically connected to the second level signal terminal VGL ( Figure 6 The connection is not directly shown in the figure), that is, the second electrode of the eighth transistor T8 can be electrically connected to the second level signal terminal VGL through the nineteenth transistor T19.

[0072] In the case where the first anti-leakage module 370 includes the twentieth transistor T20, the control electrode of the twentieth transistor T20 can serve as the control terminal of the first anti-leakage module 370, and is electrically connected to the second node QB, the first electrode of the twentieth transistor T20 is electrically connected to the second electrode of the ninth transistor T9 in the first pull-down module 330, and the second electrode of the twentieth transistor T20 is electrically connected to the second level signal terminal VGL ( Figure 6 The connection is not directly shown in the figure), that is, the second electrode of the ninth transistor T9 can be electrically connected to the second level signal terminal VGL through the twentieth transistor T20.

[0073] In the case where the first anti-leakage module 370 includes a nineteenth transistor T19 and a twentieth transistor T20, the control electrode of the nineteenth transistor T19 and the control electrode of the twentieth transistor T20 can be used together as the control end of the first anti-leakage module 370, and the second electrode of the nineteenth transistor T197 and the second electrode of the twentieth transistor T20 can be used together as a port of the first anti-leakage module 370 electrically connected to the second level signal end VGL.

[0074] Optional, such as Figure 6 As shown, the shift register provided in the embodiment of the present application may further include a second anti-leakage module 380. The control end, the first end, and the second end of the second anti-leakage module 380 are electrically connected to the control signal end P, the first level signal end VGH, and the first pull-down module 330 respectively.

[0075] Reference Figure 6 For example, the second anti-leakage module 380 may include a twenty-first transistor T21, and the control electrode, the first electrode, and the second electrode of the twenty-first transistor T21 are respectively used as the control terminal, the first terminal, and the second terminal of the second anti-leakage module 380, and are respectively electrically connected to the control signal terminal P, the first level signal terminal VGH, and the first pull-down module 330. Among them, the second end of the twenty-first transistor T21 can be electrically connected to the second electrode of the eighth transistor T8 in the first pull-down module 330, and can also be electrically connected to the second electrode of the ninth transistor T9 in the first pull-down module 330.

[0076] like Figure 6 The shift register provided with the anti-leakage module shown can be applied to an oxide backplane to reduce leakage.

[0077] Optional, such as Figures 4 to 6 As shown, the shift register provided in the embodiment of the present application may also include a second pull-down control module 390, at least one control end of the second pull-down control module 390 is electrically connected to the third clock signal end CLKC and at least one port in the third node Q, and the first end and the second end of the second pull-down control module 390 are electrically connected to the second node QB and the second level signal end VGL, respectively.

[0078] Reference Figures 4 to 6 In the example of FIG. 1 , the second pull-down control module 390 may include at least one transistor of the twenty-second transistor T22 and the twenty-third transistor T23 .

[0079] When the second pull-down control module 390 includes the twenty-second transistor T22, the control electrode of the twenty-second transistor T22 serves as a control terminal of the second pull-down control module 390 and is electrically connected to the third clock signal terminal CLKC, and the first electrode and the second electrode of the twenty-second transistor T22 serve as the first terminal and the second terminal of the second pull-down control module 390 and are electrically connected to the second node QB and the second level signal terminal VGL, respectively ( Figure 6 The connection of the VGL terminal is not directly shown). When the clock signal provided by the third clock signal terminal CLKC is a high potential, the twenty-second transistor T22 is turned on, and the potential of the second node QB is pulled down based on the low level signal provided by the second level signal terminal VGL, so that the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 cannot be turned on, and the potentials of the P point, the Q point and the output terminal Gout cannot be pulled down, and the normal output of the output terminal Gout can be guaranteed; when the clock signal provided by the third clock signal terminal CLKC is a low level, the twenty-second transistor T22 is turned off, and the potential of the second node QB cannot be pulled down. The high potential of the second node QB can turn on the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10, and pull down the potentials of the P point, the Q point and the output terminal Gout.

[0080] When the second pull-down control module 390 includes the twenty-third transistor T23, the control electrode of the twenty-third transistor T23 serves as a control terminal of the second pull-down control module 390 and is electrically connected to the third node Q. The first electrode and the second electrode of the twenty-third transistor T23 serve as the first terminal and the second terminal of the second pull-down control module 390 and are electrically connected to the second node QB and the second level signal terminal VGL, respectively. Figure 6 The connection of the VGL terminal is not directly shown in the figure). When the third node Q is at a high potential, the twenty-third transistor T23 can be turned on, and the potential of the second node QB is pulled down based on the low-level signal provided by the second level signal terminal VGL, so that the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 cannot be turned on, and the potentials of the P point, the Q point and the output terminal Gout cannot be pulled down, and the normal output of the output terminal Gout can be guaranteed; when the third node Q is at a low potential, the twenty-third transistor T23 is turned off, and the potential of the second node QB cannot be pulled down. The high potential of the second node QB can turn on the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10, and the potentials of the P point, the Q point and the output terminal Gout can be pulled down.

[0081] When the second pull-down control module 390 includes the twenty-second transistor T22 and the twenty-third transistor T23, the control electrode of the twenty-second transistor T22 and the control electrode of the twenty-third transistor T23 respectively serve as the two control terminals of the second pull-down control module 390, and are respectively electrically connected to the third clock signal terminal CLKC and the third node Q. The connection method of the remaining ports is the same as before and will not be repeated here.

[0082] In one example, referring to Figure 6 The second level signal terminal VGL connected to the nineteenth transistor T19, the twentieth transistor T20, the twenty-second transistor T22, the twenty-third transistor T23 and the first capacitor C1 can be replaced by the third level signal terminal LVGL, and the third level signal terminal LVGL can provide a signal lower than the second level signal terminal VGL.

[0083] Each transistor in the embodiment of the present application can be a thin film transistor or a field effect transistor or other devices with the same characteristics. The source (also called source electrode) and drain (also called drain electrode) of each transistor are symmetrical, so the source and drain are interchangeable. In the embodiment of the present application, the source can be used as the first end of the transistor and the drain can be used as the second end of the transistor, or the drain can be used as the first end of the transistor and the source can be used as the second end of the transistor. The middle end of each transistor is the gate (also called gate electrode) as the control end of the transistor. Each transistor in the embodiment of the present application can be a P-type transistor or an N-type transistor. Figures 4 to 6 The N-type transistor in is only used as an example.

[0084] Each of the strobe signal terminals (the first strobe signal terminal or the second strobe signal terminal) of the embodiment of the present application can be connected to two signals that are mutually inverted signals. For example, Figure 4 In the example, according to actual needs, the D0 terminal can be connected to any one of the D0 signal and the D0' signal which are mutually inverted signals. When the D0 signal is at a high potential, the D0' signal is at a low level. When the D0 signal is at a low level, the D0' signal is at a high potential. The D4' terminal can be connected to the D4 signal and the D4' signal which are mutually inverted signals.

[0085] The high potential signal and the low potential signal in the embodiment of the present application can be represented by 1 and 0 respectively, that is, 1 is used to represent the high potential signal and 0 is used to represent the low potential signal, wherein 1 and 0 represent logical potentials, which only indicate the high and low relationship of the potentials, and do not indicate the specific potential values.

[0086] The embodiment of the present application provides a pixel driving method, which can be applied to the shift register provided in any embodiment of the present application, such as Figure 7 As shown, the method includes:

[0087] S701, in a blanking phase, based on a first clock signal and a first selection signal, adjusting the potential of a second node through an input module and a first pull-down control module.

[0088] A frame includes a display phase and a blanking phase. In the display phase, the shift register can output a driving signal to drive a corresponding row of pixels for display. In the blanking phase, the shift register can output a compensation driving signal to sense the driving current of the corresponding row of pixels, thereby performing compensation based on the sensed driving circuit.

[0089] The first clock signal is a clock signal provided by the first clock signal terminal CLKA, and the first selection signal is a selection signal provided by the first selection signal terminal. There may be multiple first selection signal terminals, and correspondingly, there may also be multiple connected first selection signals.

[0090] S702, based on the first clock signal, the potential of the second node and the control signal, controlling the output of the compensation driving signal through the first output control module and the output module.

[0091] The control signal is a signal provided by the control signal terminal P.

[0092] The pixel driving method provided in the embodiment of the present application can control the on and off of the input module and the first pull-down control module based on the first clock signal and the first selection signal, and then adjust the potential of the second node QB. Based on the first clock signal, the potential of the second node QB and the control signal, the on and off of the first output control module and the output module can be controlled. When the first output control module and the output module are both turned on, a compensation driving signal can be output. The whole process does not depend on the cascade signal output by other shift registers, which is conducive to realizing compensation for random frame shifts.

[0093] Optionally, in the above step S701, based on the first clock signal and the first selection signal, the potential of the second node is adjusted through the input module and the first pull-down control module, which may include: in the first stage of the blanking stage, based on the first selection signal of the first potential, maintaining the off state of the first pull-down control module, so that the potential of the second node is maintained at the first potential; in the second and third stages of the blanking stage, based on the first clock signal of the first potential, maintaining the off state of the input module, so that the potential of the second node is maintained at the first potential; in the fourth stage of the blanking stage, based on the first clock signal of the second potential and the first selection signal of the second potential, turning on the input module and the first pull-down control module, and adjusting the potential of the second node to the second potential; the second potential is higher than the first potential, the first potential is a low potential, and the second potential is a high potential.

[0094] A plurality of first selection signals are connected to the first pull-down control module. The first selection signal of the first potential refers to the situation where each first selection signal is of the first potential. The second selection signal of the second potential refers to the situation where at least one first selection signal is of the second potential.

[0095] Reference Figure 4 In the shift register shown, in the fourth stage, when at least one of the four first selection signals D0, D1, D2 and D3 is at a high potential, a first selection unit 321 corresponding to the signal is turned on, and then the entire first pull-down control module 320 is turned on, which can raise the potential of the second node QB based on the high potential of the first node O.

[0096] Figure 8 A signal timing sequence of each signal terminal in the shift register provided in an embodiment of the present application is shown. Figure 8 In the timing example shown, in the fourth stage, the first selection signals D0 and D1 are both high potentials, the first selection signals D2 and D3 are both low potentials, and the four signals can be represented as 1100. At this time, the fifth transistor T5 and the fourth transistor T4 are both turned on, and then the first pull-down control module 320 is turned on, which can raise the potential of the second node QB based on the high potential of the first node O.

[0097] Optionally, in the above step S702, based on the first clock signal, the potential of the second node QB and the control signal, controlling the output of the compensation driving signal through the first output control module and the output module may include:

[0098] In the first stage of the blanking phase, based on the first clock signal of the second potential and the control signal of the second potential, the first output control module is turned on, the potential of the third node Q is increased to the second potential, and based on the first potential of the second node QB, the second potential of the third node Q is maintained; in the second stage of the blanking phase, based on the second potential of the third node Q, the output module is turned on, and the second clock signal of the second potential is output as a compensation drive signal.

[0099] Reference Figures 4 to 6 The shift register shown and Figure 8 The signal timing shown in the first stage ( Figure 8 Phase 1 in the Figure 8In stage 2), when the first clock signal provided by the first clock signal terminal CLKA is the second potential, i.e., the high potential, the eleventh transistor T11 in the first output control module 340 can be turned on, and when the control signal provided by the control signal terminal P is the high potential, the twelfth transistor T12 in the first output control module 340 can be turned on, so that the potential of the third node Q can be raised based on the high potential signal provided by the first level signal terminal VGH, so that the thirteenth transistor T13 in the output module 350 is turned on under the control of the high potential of the third node Q; in the second stage, when the second clock signal provided by the second clock signal terminal CLKB is the high potential, the high potential second clock signal can be output as the compensation drive signal to compensate the corresponding row of pixels.

[0100] In one example, the high potential control signal may be provided by the second output control module 360, referring to Figure 4 The shift register shown and Figure 8 As shown in the signal timing, in the stage before the first stage, when the third clock signal terminal CLKC provides a third clock signal of high potential, the fourteenth transistor T14 is turned on, and the four second selection signals D4', D5', D6' and D7' are all of high potential, and the corresponding fifteenth transistor T15, sixteenth transistor T16, seventeenth transistor T17 and eighteenth transistor T18 are all turned on, so that the potential of point P can be raised based on the high potential signal provided by the first level signal terminal VGH.

[0101] Optionally, in the above step S702, based on the first clock signal, the potential of the second node QB and the control signal, the output of the driving signal is controlled by the first output control module and the output module, and it can also include: in the third stage of the blanking stage, based on the first clock signal of the first potential, turning off the first output control module, so that the third node Q maintains the second potential, based on the second potential of the third node Q, maintaining the conductive state of the output module, and outputting the second clock signal of the first potential; in the fourth stage, based on the second potential of the second node QB, the potential of the third node Q is reduced to the first potential through the first pull-down module 330, so that the output module is turned off and the output is stopped.

[0102] Reference Figures 4 to 6 The shift register shown and Figure 7As shown in the signal timing, in the third stage, the first clock signal provided by the first clock signal terminal CLKA is the first potential, i.e., the low potential, the eleventh transistor T11 in the first output control module 340 is turned off, the entire first output control module 340 is turned off, the third node Q can maintain the previous high potential, so that the thirteenth transistor T13 in the output module 350 remains in the on state, and the second clock signal with a low potential provided by the second clock signal terminal CLKB is output. In the fourth stage, the potential of the second node QB is raised, and the eighth transistor T8 in the first pull-down module 330 can be controlled to be turned on, the potential of the third node Q is pulled down, the thirteenth transistor T13 in the output module 350 is turned off, and the output is stopped.

[0103] Refer to the following Figure 4 and Figure 8 , a specific example of a pixel driving method applied to a shift register provided in an embodiment of the present application is introduced:

[0104] In the first stage ( Figure 8 In stage 1), the first clock signal (hereinafter referred to as CLKA signal) provided by the first clock signal terminal CLKA is at a high potential, the first transistor T1 is turned on and the eleventh transistor T11 is turned on, the first transistor T1 raises the potential of the first node O, the first selection signals D0, D1, D2 and D3 are all at a low potential, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned off, and the potential of the second node QB cannot be raised, the second selection signals D4', D5', D6' and D7' are all at a high potential, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are all turned on, which can maintain the high potential of the point P, and then maintain the high potential of the point Q, and select a row of pixels based on the output of the thirteenth transistor T13.

[0105] In the second stage ( Figure 8 In stage 2), the second clock signal (hereinafter referred to as CLKB signal) provided by the second clock signal terminal CLKB is at a high potential, and the Q point still maintains a high potential, controlling the eighteenth transistor T18 to be turned on. The turned-on eighteenth transistor T18 can output a high potential CLKB signal to a corresponding row of pixels as a compensation drive signal.

[0106] In the third stage ( Figure 8 In stage 3), the CLKA signal is at a low potential, the eleventh transistor T11 is turned off, the Q point still maintains a high potential, the thirteenth transistor T13 remains on, the CLKB signal is at a low potential, and the thirteenth transistor T13 can output a low potential CLKB signal.

[0107] In the fourth stage ( Figure 8In stage 4), the CLKA signal is at a high potential, the first transistor T1 is turned on, and the potential of the point O is raised, the first selection signals D0 and D1 are at a high potential, the second selection signals D2 and D3 are at a low potential, the fifth transistor T5 and the fourth transistor T4 are both turned on, the third transistor T3 and the second transistor T2 are both turned off, the fifth transistor T5 and the fourth transistor T4 can raise the potential of the point QB based on the high potential of the point O, and the high potential of QB can control the seventeenth transistor T17, the fourteenth transistor T14 and the nineteenth transistor T19 to be turned on, respectively pulling down the potentials of the point Q, the point P and the output terminal Gout, so that the corresponding pixel row enters the low voltage holding stage.

[0108] Based on the same inventive concept, an embodiment of the present application further provides a gate driving circuit, which may include: multiple shift register groups, each shift register group includes multiple shift registers, and each shift register is any one of the shift registers provided in the embodiment of the present application.

[0109] The same type of clock signal terminals in the same shift register group are used to access m clock signals respectively; the same shift register group includes mn-m+1 shift registers to the mnth register, n is a positive integer, and m is an integer greater than 2; the same type of selection signal terminals in the same shift register group are used to access the same selection signal, different types of selection signal terminals are used to access different selection signal terminals, and some of the same type of selection signal terminals in different shift register groups are used to access different selection signals.

[0110] The grouping of the shift register can be determined according to the number of combinations of accessible selection signals. If a shift register has two selection signal ports and needs to be connected to two selection signals, there are four selection signals available for access, two of which are mutually inverted signals, such as D0 and D0', and the other two are mutually inverted signals, such as D1 and D1'. The four selection signals can form four combinations to access the shift register, such as the combination of D0 and D1, the combination of D0 and D1', the combination of D0' and D1, and the combination of D0' and D1', thereby forming four shift register groups, and each shift register in each shift register group is connected to the same selection signal combination.

[0111] Fig. 9 shows a connection diagram of a shift register group, Figure 8 The shift register in the embodiment includes four shift registers, namely GOA1, GOA2, GOA3 and GOA4, and the four shift registers are connected to the same selection signal, namely D0, D1, D2, D3, D4', D5', D6' and D7'. The selection signal can have 8 lines as one cycle.

[0112] For the same shift register group, the same type of selection signal terminal can be the selection signal terminal controlling the same selection unit in each shift register of the shift register group. In one example, if the structure of each shift register of the same shift register group is as follows: Figure 4 As shown, the D0 terminal in each shift register is a similar selection signal terminal, the D1 terminal of each shift register is a similar selection signal terminal, and the D2 terminal of each shift register is a similar selection signal terminal.

[0113] For the same shift register group, the same type of clock signal terminal may be the clock signal terminal of each shift register of the shift register group that controls the same type of transistor. In one example, if the structure of each shift register of the same shift register group is as follows: Figure 4 As shown, the first clock signal terminal CLKA of the input transistor, i.e., the first transistor T1, in each shift register is a clock signal terminal of the same type, the second clock signal terminal CLKB of the output transistor, i.e., the eighteenth transistor T18, in each shift register is a clock signal terminal of the same type, and the third clock signal terminal CLKC of the eighth transistor T8 is a clock signal terminal of the same type.

[0114] The number of shift registers in the same shift register group can be determined according to the number of clock signals provided, and this number can be used as the value of m. Figure 8 In the example, four different clock signals may be provided, namely CLK1, CLK2, CLK3 and CLK4, and then the same shift register group may include four shift registers GOA1, GOA2, GOA3 and GOA4, the first clock signal terminals CLKA of the four shift registers are respectively connected to CLK4, CLK1, CLK2, CLK3, the second clock signal terminals CLKB of the four shift registers are respectively connected to CLK1, CLK2, CLK3, CLK4, and the third clock signal terminals CLKC of the four shift registers are respectively connected to CLK2, CLK3, CLK4, CLK1. The clock signal may have 4 lines as a cycle.

[0115] By providing different clock signals to different shift registers, combined with the provided selection signal, the pixel rows can be partitioned and controlled. In the blanking phase of a frame, a pixel row can be randomly selected for compensation to achieve compensation for random frame shift. Figure 7 The signals in the first stage shown can act on four shift registers at the same time, and four pixel rows can be selected at the same time. The shift registers can be independent of each other and do not need to be cascaded, which simplifies the structure of the gate drive circuit and improves practicality.

[0116] The number of clock signals and the number of strobe signals connected to the gate drive circuit can be set according to actual needs and process conditions. Different numbers can achieve different resolutions. Figure 8In the example, the number of clock signals connected to the gate drive circuit is 4, and the number of select signals is 16, which can achieve 1024 (2 to the power of 10) rows of display drive; in other examples, if the number of clock signals connected to the gate drive electrode is 4, and the number of select signals is 18, then 2048 (2 to the power of 11) rows of display drive can be achieved.

[0117] Based on the same inventive concept, an embodiment of the present application also provides a pixel driving method, which can be applied to the gate driving circuit provided in the embodiment of the present application. The pixel driving method may include: based on multiple clock signals and multiple selection signals, randomly controlling a shift register to output a compensation driving signal in the blanking stage; the frequencies of some of the multiple selection signals are different.

[0118] The specific access method of multiple clock signals and multiple selection signals can refer to the content of the previous embodiment and will not be repeated here.

[0119] exist Figure 8 In the example shown, the plurality of selection signals include 16 signals in total, namely, D0, D0', D1, D1', D2, D2', D3, D3', D4, D4', D5, D5', D6, D6', D7 and D7', wherein D0', D1', D2', D3', D4', D5', D6', D7' are respectively the inverted signals of D0, D1, D2, D3, D4, D5, D6, D7, and ... 1. The frequencies of D2, D3, D4, D5, D6 and D7 can be reduced in sequence, and correspondingly, the frequencies of D0', D1', D2', D3', D4', D5', D6', D7' can also be reduced in sequence, and the pulse widths of D0, D1, D2, D3, D4, D5, D6 and D7 can be increased in sequence, and correspondingly, the pulse widths of D0', D1', D2', D3', D4', D5', D6', D7' can also be increased in sequence.

[0120] Reference Figure 8 For example, the highest frequency selection signal is D0, the frequency of D1 is half of the frequency of D0, the frequency of D2 is half of the frequency of D1, and so on. The selection signal with the smallest pulse width is D0, the pulse width of D1 is twice the pulse width of D0, the pulse width of D2 is twice the pulse width of D1, and so on. Each shift register group has 4 shift registers and is controlled by a fixed 4-cycle clock (the cycle is 4 lines), so the cycle of D0 can be determined to be 8 lines.

[0121] A higher frequency signal can be provided to the first selection signal terminal in the shift register to quickly adjust the potential of the second node to avoid the second node floating for a long time, and a lower frequency signal can be provided to the second selection signal terminal in the shift register.

[0122] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0123] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0124] The wording "comprising" used in the specification of the present application refers to the features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. The wording "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0125] It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" used herein may include wireless connection or wireless coupling.

[0126] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0127] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: An input module, a first pull-down control module, a first pull-down module, a first output control module, and an output module; The control end, the first end, and the second end of the input module are electrically connected to the first clock signal end, the first level signal end, and the first node respectively; The control end, the first end and the second end of the first pull-down control module are electrically connected to the first selection signal end, the first node and the second node respectively; The control end, the first end and the second end of the first pull-down module are electrically connected to the second node, the third node and the second level signal end respectively; The first control end, the second control end, the first end, and the second end of the first output control module are electrically connected to the first clock signal end, the control signal end, the first level signal end, and the third node respectively; The control end and the first end of the output module are electrically connected to the third node and the second clock signal end respectively, and the second end of the output module is the output end of the shift register.

2. The shift register according to claim 1, characterized in that: The first pull-down control module includes at least one first gating unit; The control end, the first end, and the second end of each first gating unit are electrically connected to the corresponding first gating signal end, the first node, and the second node respectively.

3. The shift register according to claim 2, characterized in that: The number of the first gating units is less than or equal to 6.

4. The shift register according to claim 2, characterized in that: The frequencies of the selection signals provided by the first selection signal terminals decrease in sequence.

5. The shift register according to claim 4, characterized in that: The pulse width of the selection signal provided by each first selection signal terminal increases sequentially.

6. The shift register according to any one of claims 1 to 5, characterized in that: Also includes: A second output control module; The first control end, the second control end and the first end of the second output control module are electrically connected to the third clock signal end, the second selection signal end and the first level signal end respectively; The second end of the second output control module serves as the control signal end and is electrically connected to the second control end of the first output control module.

7. The shift register according to claim 6, characterized in that: The second output control module includes: a pull-up unit and a second gating unit; The control end, the first end, and the second end of the pull-up unit are electrically connected to the third clock signal end, the first level signal end, and the first end of the second gating unit respectively; The control end of the second gating unit is electrically connected to the second gating signal end, and the second end of the second gating unit serves as the control signal end and is electrically connected to the second control end of the first output control module.

8. The shift register according to any one of claims 1 to 5, characterized in that: The first pull-down module further includes a third end; The third end of the first pull-down module is electrically connected to the control signal end.

9. The shift register according to claim 8, characterized in that: Also includes: A first anti-leakage module; The control end of the first anti-leakage module is electrically connected to the second node, at least one end of the first anti-leakage module is electrically connected to at least one end of the first pull-down module, and the other end of the first anti-leakage module is electrically connected to the second level signal end.

10. The shift register according to claim 8, characterized in that: Also includes: The second anti-leakage module; The control end, the first end, and the second end of the second anti-leakage module are electrically connected to the control signal end, the first level signal end, and the first pull-down module respectively.

11. A pixel driving method, characterized in that: Applied to the shift register according to any one of claims 1 to 10, the pixel driving method comprises: In the blanking phase, based on the first clock signal and the first selection signal, the potential of the second node is adjusted through the input module and the first pull-down control module; Based on the first clock signal, the potential of the second node and the control signal, the output of the compensation driving signal is controlled by the first output control module and the output module.

12. The pixel driving method according to claim 11, characterized in that: In the blanking phase, based on the first clock signal and the first selection signal, the potential of the second node is adjusted through the input module and the first pull-down control module, including: In a first stage of the blanking stage, based on a first selection signal of a first potential, the first pull-down control module is maintained in an off state, so that the potential of the second node is maintained at the first potential; In the second and third stages of the blanking stage, based on the first clock signal of the first potential, the input module is kept in an off state, so that the potential of the second node is maintained at the first potential; In the fourth stage of the blanking phase, based on the first clock signal of the second potential and the first selection signal of the second potential, the input module and the first pull-down control module are turned on, and the potential of the second node is adjusted to the second potential; the second potential is higher than the first potential.

13. The pixel driving method according to claim 12, characterized in that: The method of controlling the output of the compensation driving signal through the first output control module and the output module based on the first clock signal, the potential of the second node and the control signal comprises: In a first stage of the blanking stage, based on the first clock signal of the second potential and the control signal of the second potential, the first output control module is turned on to increase the potential of the third node to the second potential, and based on the first potential of the second node, the second potential of the third node is maintained; In the second stage of the blanking stage, based on the second potential of the third node, the output module is turned on to output the second clock signal of the second potential as a compensation driving signal.

14. The pixel driving method according to claim 13, characterized in that: The method of controlling the output of the compensation driving signal through the first output control module and the output module based on the first clock signal, the potential of the second node and the control signal also includes: In the third stage of the blanking stage, based on the first clock signal of the first potential, the first output control module is turned off to keep the third node at the second potential, and based on the second potential of the third node, the output module is kept in the on state to output the second clock signal of the first potential; In the fourth stage of the blanking stage, based on the second potential of the second node, the potential of the third node is reduced to the first potential through the first pull-down module, so that the output module is turned off and stops outputting.

15. A gate drive circuit, characterized in that: include: A plurality of shift register groups, each shift register group comprising a plurality of shift registers according to any one of claims 1 to 10; The same type of clock signal terminals in the same shift register group are used to respectively access m clock signal electrical connections; the same shift register group includes the mn-m+1th shift register to the mnth register, where n is a positive integer and m is an integer greater than 2; The same type of selection signal terminals in the same shift register are used to access the same selection signal, different types of selection signal terminals are used to access different selection signal terminals for electrical connection, and some of the same type of selection signal terminals in different shift register groups are used to access different selection signal terminals for electrical connection.

16. A pixel driving method, characterized in that: Applied to the gate driving circuit as claimed in claim 15, the pixel driving method comprises: Based on multiple clock signals and multiple strobe signals, a shift register is randomly controlled to output a compensation driving signal during a blanking phase; and frequencies of some strobe signals in the multiple strobe signals are different.

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