Shift register unit and driving method thereof, reset driving circuit, display device

Abstract

Provided are a shift register unit and a driving method thereof, a reset driving circuit, and a display device, and belong to the technical field of display. In the shift register unit, an input circuit can control the on-off of an input end and a pull-up node to control the potential of the pull-up node. A pull-down circuit can control the on-off of a first power supply end and a second power supply end and a pull-down node to control the potential of the pull-down node. An output circuit can control the on-off of the first power supply end and an output end in response to the potential of the pull-up node, and can control the on-off of the second power supply end and the output end in response to the potential of the pull-down node, so as to transmit a first power supply signal of a first potential and a second power supply signal of a second potential to the output end. The output end is coupled with a reset signal end. In this way, the input signal can be flexibly set based on a light-emitting control signal, so that the reset signal can be reliably transmitted to the reset signal end of the pixel circuit through the shift register unit, and the pixel circuit can reliably drive the light-emitting element to emit light.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit and its driving method, a reset driving circuit, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices are among the most common display devices in the current display field, with advantages such as high contrast, thinness and wide viewing angle.

[0003] In related technologies, OLED display devices generally include a display panel and multiple pixels located within the display panel. Each pixel includes a pixel circuit and a light-emitting element. The pixel circuit is coupled to multiple signal terminals and the light-emitting element, and is used to provide a light-emitting driving signal to the light-emitting element based on signals provided by the multiple signal terminals, thereby driving the light-emitting element to emit light. For example, the multiple signal terminals include at least a reset signal terminal capable of providing a reset signal and a light-emitting control terminal capable of providing a light-emitting control signal, and the pulse width of the reset signal generally needs to be equal to the pulse width of the light-emitting control signal to reliably drive the light-emitting element to emit light.

[0004] However, since the reset signal terminal is generally directly coupled to the power supply circuit that can provide the reset signal through the reset signal line, and is independent of the provision of the light emission control signal, the pulse widths of the reset signal and the light emission control signal cannot be reliably correlated, which in turn leads to the inability to reliably drive the light-emitting element to emit light. Summary of the Invention

[0005] A shift register unit and its driving method, a reset driving circuit, and a display device are provided, which can solve the problem of unreliable driving of light-emitting elements in related technologies. The technical solution is as follows:

[0006] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0007] The input circuit is coupled to the first clock terminal, the input terminal, and the pull-up node respectively, and is used to control the on / off state of the input terminal and the pull-up node in response to the first clock signal provided by the first clock terminal.

[0008] The pull-down circuit is coupled to the first clock terminal, the pull-up node, the input terminal, the first power supply terminal, the second power supply terminal, the second clock terminal, and the pull-down node, respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the first clock signal, the second clock signal provided by the second clock terminal, the input signal provided by the input terminal, and the second power supply signal provided by the second power supply terminal, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the pull-up node;

[0009] The output circuit is coupled to the pull-up node, the pull-down node, the first power supply terminal, the second power supply terminal, and the output terminal, respectively, and is used to control the connection and disconnection between the first power supply terminal and the output terminal in response to the potential of the pull-up node, and to control the connection and disconnection between the second power supply terminal and the output terminal in response to the potential of the pull-down node.

[0010] The output terminal is used to be coupled to the reset signal terminal of the pixel circuit, and the pulse width of the input signal is not greater than the pulse width of the light emission control signal provided by the light emission control terminal of the pixel circuit.

[0011] Optionally, the input circuit includes: a first input transistor and a second input transistor connected in series;

[0012] In this configuration, the control terminals of the first and second input transistors are both coupled to the first clock terminal, the first terminal of the first input transistor is coupled to the input terminal, the second terminal of the first input transistor is coupled to the first terminal of the second input transistor, and the second terminal of the second input transistor is coupled to the pull-up node.

[0013] Optionally, the shift register unit further includes: an input control circuit;

[0014] The input control circuit is coupled to the pull-up node and the first power supply terminal respectively, and is also coupled to the series node of the first input transistor and the second input transistor, and is used to control the on / off state of the first power supply terminal and the series node in response to the potential of the pull-up node.

[0015] Optionally, the input control circuit includes: an input control transistor;

[0016] The control electrode of the input control transistor is coupled to the pull-up node, the first electrode of the input control transistor is coupled to the first power supply terminal, and the second electrode of the input control transistor is coupled to the series node.

[0017] Optionally, the pull-down circuit includes: a pull-down control sub-circuit and a pull-down sub-circuit;

[0018] The pull-down control sub-circuit is coupled to the first clock terminal, the second clock terminal, the input terminal, the first power terminal, the second power terminal, and the pull-down control node, respectively, and is used to control the on / off state of the first power terminal and the pull-down control node in response to the first clock signal, and to control the on / off state of the second power terminal and the pull-down control node in response to the second clock signal and the input signal.

[0019] The pull-down sub-circuit is coupled to the pull-down control node, the pull-up node, the first power supply terminal, the second power supply terminal, and the pull-down node, respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-down control node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the pull-up node.

[0020] Optionally, the pull-down control sub-circuit includes: a first pull-down control transistor, a second pull-down control transistor, and a third pull-down control transistor;

[0021] The control terminal of the first pull-down control transistor is coupled to the first clock terminal, the first terminal of the first pull-down control transistor is coupled to the first power supply terminal, and the second terminal of the first pull-down control transistor is coupled to the pull-down control node.

[0022] The control electrode of the second pull-down control transistor is coupled to the input terminal, the first electrode of the second pull-down control transistor is coupled to the second power supply terminal, and the second electrode of the second pull-down control transistor is coupled to the pull-down control node.

[0023] The control electrode of the third pull-down control transistor is coupled to the second clock terminal, the first electrode of the second pull-down control transistor is coupled to the second power supply terminal, and the second electrode of the second pull-down control transistor is coupled to the pull-down control node.

[0024] Optionally, the pull-down sub-circuit includes: a first pull-down transistor and a second pull-down transistor;

[0025] The control electrode of the first pull-down transistor is coupled to the pull-down control node, the first electrode of the first pull-down transistor is coupled to the first power supply terminal, and the second electrode of the first pull-down transistor is coupled to the pull-down node.

[0026] The control terminal of the second pull-down transistor is coupled to the pull-up node, the first terminal of the second pull-down transistor is coupled to the second power supply terminal, and the second terminal of the second pull-down transistor is coupled to the pull-down node.

[0027] Optionally, the shift register unit further includes: a potential adjustment circuit;

[0028] The potential adjustment circuit is coupled to the pull-down control node and the pull-down node respectively, and is used to adjust the potential of the pull-down control node and the potential of the pull-down node.

[0029] Optionally, the potential adjustment circuit includes: a first capacitor;

[0030] The first end of the first capacitor is coupled to the pull-down control node, and the second end of the first capacitor is coupled to the pull-down node.

[0031] Optionally, the output circuit includes: a first output sub-circuit and a second output sub-circuit;

[0032] The first output sub-circuit is coupled to the pull-up node, the first power supply terminal and the output terminal respectively, and is used to control the on / off state of the first power supply terminal and the output terminal in response to the potential of the pull-up node;

[0033] The second output sub-circuit is coupled to the pull-down node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the pull-down node.

[0034] Optionally, the first output sub-circuit includes: a first output transistor and a second capacitor;

[0035] The control electrode of the first output transistor is coupled to the pull-up node, the first electrode of the first output transistor is coupled to the first power supply terminal, and the second electrode of the first output transistor is coupled to the output terminal.

[0036] The first terminal of the second capacitor is coupled to the control electrode of the first output transistor, and the second terminal of the second capacitor is coupled to the second electrode of the first output transistor.

[0037] Optionally, the second output sub-circuit includes: a second output transistor and a third capacitor;

[0038] The control electrode of the second output transistor is coupled to the pull-down node, the first electrode of the second output transistor is coupled to the second power supply terminal, and the second electrode of the second output transistor is coupled to the output terminal.

[0039] The first terminal of the third capacitor is coupled to the control electrode of the second output transistor, and the second terminal of the third capacitor is coupled to the first electrode of the second output transistor.

[0040] On the other hand, a method for driving a shift register unit is provided, the method being used to drive the shift register unit as described in the above aspect, the method comprising:

[0041] In the first stage, the potential of the first clock signal provided by the first clock terminal is the first potential, the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are the second potential. The input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node. The pull-down control circuit responds to the first clock signal, the second clock signal, the input signal and the second power signal provided by the second power terminal and controls the first power terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-down node and controls the second power terminal to be connected to the output terminal.

[0042] In the second stage, the potential of the first clock signal and the potential of the input signal are the first potential, and the potential of the second clock signal is the second potential. The input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node. The pull-down control circuit responds to the first clock signal, the second clock signal, the input signal, and the second power signal and controls the second power terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node and controls the first power terminal to be connected to the output terminal.

[0043] Wherein, the potential of the first power signal provided by the first power supply terminal is the first potential, and the potential of the second power signal is the second potential.

[0044] In another aspect, a reset driving circuit is provided, the reset driving circuit comprising: at least two cascaded shift register units as described in the above aspect;

[0045] In this system, the input terminal of the first-stage shift register unit is coupled to the reset enable terminal. In other shift register units besides the first-stage shift register unit, the input terminal of each shift register unit is coupled to the output terminal of the cascaded previous-stage shift register unit.

[0046] In another aspect, a display device is provided, the display device comprising: a display panel, and a reset drive circuit as described in yet another aspect above;

[0047] The display panel includes a plurality of pixels, each pixel including a pixel circuit and a light-emitting element. The pixel circuit is coupled to a reset signal terminal, a light-emitting control terminal and the light-emitting element respectively, and is used to drive the light-emitting element to emit light in response to a reset signal from the reset signal terminal and a light-emitting control signal from the light-emitting control terminal.

[0048] The reset drive circuit is coupled to the reset signal terminal and is used to provide a reset signal to the reset signal terminal.

[0049] Optionally, the pixel circuit includes a plurality of transistors, and all of the plurality of transistors are N-type oxide transistors.

[0050] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0051] A shift register unit, its driving method, reset driving circuit, and display device are provided. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit controls the connection and disconnection between the input terminal and the pull-up node to control the potential of the pull-up node. The pull-down circuit controls the connection and disconnection between the first power supply terminal and the second power supply terminal and the pull-down node to control the potential of the pull-down node. The output circuit responds to the potential of the pull-up node by controlling the connection and disconnection between the first power supply terminal and the output terminal, and also responds to the potential of the pull-down node by controlling the connection and disconnection between the second power supply terminal and the output terminal, thereby transmitting a first power supply signal at the first potential and a second power supply signal at the second potential to the output terminal. The output terminal is used to couple with a reset signal terminal. In this way, the input signal provided by the input terminal can be flexibly set based on the light emission control signal, enabling reliable transmission of the reset signal to the reset signal terminal of the pixel circuit through the shift register unit, thereby allowing the pixel circuit to reliably drive the light-emitting element to emit light. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure;

[0054] Figure 2 This is a schematic diagram of the structure of a pixel circuit and a light-emitting element provided in an embodiment of this disclosure;

[0055] Figure 3 This is a schematic diagram of another pixel circuit and light-emitting element provided in an embodiment of the present disclosure;

[0056] Figure 4 This is a timing diagram of the signal terminals of a pixel circuit provided in an embodiment of this disclosure;

[0057] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0058] Figure 6 This is a schematic diagram of the structure of another shift register unit provided in this embodiment;

[0059] Figure 7This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0060] Figure 8 This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0061] Figure 9 This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0062] Figure 10 This is a schematic diagram of another shift register unit provided in an embodiment of the present disclosure;

[0063] Figure 11 This is a flowchart of a driving method for a shift register unit provided in an embodiment of this disclosure;

[0064] Figure 12 This is a timing diagram of the signal terminals of a shift register unit provided in an embodiment of this disclosure;

[0065] Figure 13 yes Figure 10 The equivalent circuit diagram of the shift register unit in the first stage is shown below;

[0066] Figure 14 yes Figure 10 The equivalent circuit diagram of the shift register unit shown is shown in the second stage;

[0067] Figure 15 yes Figure 10 The equivalent circuit diagram of the shift register unit in the third stage is shown below;

[0068] Figure 16 yes Figure 10 The equivalent circuit diagram of the shift register unit in the fourth stage is shown below;

[0069] Figure 17 yes Figure 10 The equivalent circuit diagram of the shift register unit in the eighth stage is shown below;

[0070] Figure 18 yes Figure 10 The equivalent circuit diagram of the shift register unit shown in the tenth stage;

[0071] Figure 19 This is a timing simulation diagram of the signal terminals of a shift register unit provided in an embodiment of this disclosure;

[0072] Figure 20 This is a schematic diagram of a reset drive circuit provided in an embodiment of the present disclosure;

[0073] Figure 21This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0075] All transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this disclosure, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include either P-type or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. Additionally, multiple signals in the various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the signal has two potential states and do not represent that the first potential or the second potential has a specific numerical value throughout the text.

[0076] Figure 1 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure. For example... Figure 1 As shown, the shift register unit includes: input circuit 01, pull-down circuit 02, and output circuit 03.

[0077] The input circuit 01 is coupled (i.e. electrically connected) to the first clock terminal RCK, the input terminal Rin, and the pull-up node PU, respectively, and is used to control the on / off state of the input terminal Rin and the pull-up node PU in response to the first clock signal provided by the first clock terminal RCK.

[0078] For example, the input circuit 01 can be used to control the input terminal Rin to conduct with the pull-up node PU when the potential of the first clock signal provided by the first clock terminal RCK is at the first potential. At this time, the input signal provided by the input terminal Rin can be transmitted (or "written") to the pull-up node PU. Furthermore, the input circuit 01 can be used to control the input terminal Rin to disconnect from the pull-up node PU when the potential of the first clock signal is at the second potential.

[0079] Optionally, in this embodiment, the first potential can be an effective potential, and the second potential can be an ineffective potential. Furthermore, the first potential can be a high potential, and the second potential can be a low potential, meaning the first potential is larger than the second potential. The transistor in the circuit corresponding to this potential can be an N-type transistor. If the transistor in the circuit is a P-type transistor, then the first potential can be a low potential, and the second potential can be a high potential, meaning the first potential is smaller than the second potential. Further details will not be elaborated in the following embodiments.

[0080] The pull-down circuit 02 is coupled to the first clock terminal RCK, the pull-up node PU, the input terminal Rin, the first power supply terminal VGH, the second power supply terminal VGL, the second clock terminal RCB, and the pull-down node PD, respectively. It is used to control the on / off state of the first power supply terminal VGH and the pull-down node PD in response to the first clock signal, the second clock signal provided by the second clock terminal RCB, the input signal provided by the input terminal Rin, and the second power supply signal provided by the second power supply terminal VGL, and to control the on / off state of the second power supply terminal VGL and the pull-down node PD in response to the potential of the pull-up node PU.

[0081] For example, pull-down circuit 02 can control the first power supply terminal VGH to conduct with the pull-down node PD when the potential of the first clock signal is the first potential, the potential of the input signal is the second potential, and the potential of the second clock signal provided by the second clock terminal RCB is the second potential. At this time, the first power signal provided by the first power supply terminal VGH at the first potential can be transmitted to the pull-down node PD to charge it. Conversely, pull-down circuit 02 can also control the first power supply terminal VGH to disconnect from the pull-down node PD when the potential of the first clock signal is the second potential, the potential of the input signal is the first potential, and the potential of the second clock signal is the first potential.

[0082] Similarly, pull-down circuit 02 can control the second power supply terminal VGL to conduct with the pull-down node PD when the potential of the pull-up node PU is the first potential. At this time, the potential of the second power supply signal provided by the second power supply terminal VGL at the second potential can be transmitted to the pull-down node PD to reduce noise for the pull-down node PD. Furthermore, pull-down circuit 02 can control the second power supply terminal VGL to disconnect from the pull-down node PD when the potential of the pull-up node PU is the second potential.

[0083] The output circuit 03 is coupled to the pull-up node PU, the pull-down node PD, the first power supply terminal VGH, the second power supply terminal VGL, and the output terminal Rout, respectively. It is used to control the on / off state of the first power supply terminal VGH and the output terminal Rout in response to the potential of the pull-up node PU, and to control the on / off state of the second power supply terminal VGL and the output terminal Rout in response to the potential of the pull-down node PD.

[0084] For example, output circuit 03 can control the first power supply terminal VGH to conduct with output terminal Rout when the potential of pull-up node PU is at the first potential. At this time, the first power supply signal at the first potential can be transmitted to output terminal Rout. Also, output circuit 03 can control the first power supply terminal VGH to decouple from output terminal Rout when the potential of pull-up node PU is at the second potential.

[0085] Similarly, when the potential of the pull-down node PD is the first potential, the output circuit 03 can control the second power supply terminal VGL to conduct with the output terminal Rout. At this time, the second power supply signal at the second potential can be transmitted to the output terminal Rout. Also, when the potential of the pull-down node PD is the second potential, the output circuit 03 can control the second power supply terminal VGL to disconnect from the output terminal Rout.

[0086] That is, the output circuit 03 can transmit the first power supply signal of the first potential and the second power supply signal of the second potential to the output terminal Rout, so as to achieve the purpose of reliably transmitting output signals of different potentials to the output terminal Rout without adding a clock terminal.

[0087] It should be noted that the output terminal Rout of the shift register unit described in this embodiment is coupled to the reset signal terminal Rst1(n) of the pixel circuit. Thus, the first power supply signal of the first potential and the second power supply signal of the second potential ultimately transmitted to the output terminal Rout can be transmitted as a reset signal to the reset signal terminal Rst1(n). Furthermore, the pulse width of the input signal is not greater than (i.e., less than or equal to) the pulse width of the light emission control signal provided by the light emission control terminal EM(n) of the pixel circuit.

[0088] Example, Figure 2 A schematic diagram of a pixel circuit structure is shown. Figure 2 As shown, the pixel circuit P1 can be coupled to the reset signal terminal Rst1(n) and the light emission control terminal EM(n), respectively. It can also be coupled to the reset power supply terminal Vinit, the data signal terminal Data(n), the drive power supply terminal VDD, the first electrode of the light-emitting element L1, and the gate signal terminals Gate(n) and Gate(n-1). The second electrode of the light-emitting element L1 can be coupled to the pull-down power supply terminal VSS. The pixel circuit P1 can transmit a light emission driving signal to the first electrode of the light-emitting element L1 based on the signals provided by the coupled signal terminals and the signal provided by the drive power supply terminal VDD, causing the light-emitting element L1 to emit light under the voltage difference between the light emission driving signal and the pull-down power supply signal provided by the pull-down power supply terminal. The reset signal terminal Rst1(n) can be coupled to the output terminal Rout of the shift register unit described in the disclosed embodiment and receive the reset signal provided by the shift register unit. Accordingly, the shift register unit described in this disclosed embodiment can also be called a reset shift register unit.

[0089] Optional, combined Figure 2 It can also be seen that the commonly used pixel circuit is generally a 7T1C (i.e., seven transistors T1 to T7 and one capacitor C0, where T1 is the driving transistor) structure. Of course, other structures are also possible, such as 6T1C. Furthermore, the light-emitting element L1 described in this embodiment can be an OLED. Correspondingly, the first electrode of the light-emitting element L1 can be the anode, and the second electrode can be the cathode. The anode of an OLED is generally made of indium tin oxide (ITO) material with a high work function. Moreover, for OLEDs, due to process characteristics, the anode of the OLED is generally coupled to the pixel circuit P1 after the transistors in the pixel circuit P1 have been manufactured.

[0090] Of course, in some other embodiments, the light-emitting element L1 can also be Figure 3 The image shows a micro light-emitting diode (MLED). Combined with... Figure 3 For MLEDs, their anodes are generally coupled above the driving transistor T1 in the pixel circuit P1, and the anode of the MLED is coupled to the power supply terminal LVDD. The pixel circuit P1 is coupled to the cathode of the MLED. The reset power supply terminal is identified as IVDD, and the pull-down power supply terminal is identified as LVSS. Furthermore, regardless of the type of pixel, in the pixel circuit P1 described in this embodiment, all transistors can be N-type oxide transistors.

[0091] For example, in Figure 2 Based on the structure shown, Figure 4 A timing diagram of the signal terminals coupled to a pixel circuit P1 is shown. (Reference) Figure 4 It can be seen that before the light-emitting stage t03, that is, before the potential of the light-emitting control signal provided by the light-emitting control terminal EM is an effective potential, the reset signal terminal RST1(n) can continuously provide a reset signal of the first potential (i.e., the effective potential) so that the anode of the light-emitting element L1 can be maintained by the reset power supply signal provided by the reset power supply terminal Vinit, thus preventing the light-emitting element L1 from emitting light erroneously. After the potential of the light-emitting control signal jumps to an effective potential, the reset signal terminal RST1(n) can stop providing the reset signal of the effective potential. That is, Figure 4The pulse width of the input signal shown is equal to the pulse width of the light emission control signal. Here, the pulse width of the input signal can refer to the duration during which the input signal's potential is an effective potential. The pulse width of the light emission control signal can refer to the duration during which the light emission control signal's potential is an ineffective potential. Thus, this embodiment of the present disclosure, by setting the pulse width of the input signal provided by the input terminal Rin coupled to the shift register unit to be no greater than the pulse width of the light emission control signal provided by the light emission control terminal EM(n) of the pixel circuit, can reliably ensure that a valid reset signal is continuously provided to the reset signal terminal RST1(n) before the light emission stage, thereby ensuring that the light-emitting element L1 reliably emits light.

[0092] also, Figure 4 The diagram also schematically illustrates the gate drive signals provided by the gate signal terminals Gate(n) and Gate(n-1), and the data signal provided by the data signal terminal Data(n). Prior to the light-emitting stage t03, a reset stage t01 and a data writing stage t02 may also be included. In the reset stage t01, the potentials of the reset signal provided by the reset signal terminal RST1(n) and the gate drive signal provided by the gate signal terminal Gate(n-1) are both valid potentials, achieving a reset at the coupled point. In the data writing stage t02, the potential of the gate drive signal provided by the gate signal terminal Gate(n) is a first potential, ensuring that the data signal provided by the data signal terminal Data(n) is reliably written to the coupled point. Finally, the light-emitting element L1 is illuminated.

[0093] It should be noted that n represents the nth level, and n is generally an integer greater than 0. In this embodiment, it can actually include multiple cascaded levels. Figure 1 The shift register units shown are coupled to the reset signal terminals Rst1(n) of different pixel circuits P1. Multiple cascaded shift register units can also be called a reset drive circuit, abbreviated as RGOA. Furthermore, the input terminal Rin of the first-stage shift register unit is generally coupled to the reset enable terminal RSTV. In other stages of shift register units besides the first-stage unit, the input terminal Rin of each stage is coupled to the output terminal Rout of the cascaded previous-stage shift register unit. Figure 4 The input signal shown is the reset enable signal provided by the reset enable terminal RSTV coupled to the first-stage shift register unit. This embodiment can be considered as proposing an RGOA, and flexibly setting the pulse width of the reset enable signal provided by the reset enable terminal RSTV based on the light emission control signal to provide the required reset signal to the reset signal terminal Rst1(n) of the pixel circuit P1.

[0094] In summary, this disclosure provides a shift register unit. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit controls the connection and disconnection between the input terminal and the pull-up node to control the potential of the pull-up node. The pull-down circuit controls the connection and disconnection between the first power supply terminal and the second power supply terminal and the pull-down node to control the potential of the pull-down node. The output circuit responds to the potential of the pull-up node by controlling the connection and disconnection between the first power supply terminal and the output terminal, and responds to the potential of the pull-down node by controlling the connection and disconnection between the second power supply terminal and the output terminal, thereby transmitting a first power supply signal at the first potential and a second power supply signal at the second potential to the output terminal. The output terminal is used to couple with a reset signal terminal. Thus, the input signal provided by the input terminal can be flexibly set based on the light emission control signal, enabling reliable transmission of the reset signal to the reset signal terminal of the pixel circuit through the shift register unit, thereby enabling the pixel circuit to reliably drive the light-emitting element to emit light.

[0095] Figure 5 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. For example... Figure 5 As shown, the pull-down circuit 02 described in this embodiment may include: a pull-down control sub-circuit 021 and a pull-down sub-circuit 022.

[0096] The pull-down control sub-circuit 021 can be coupled to the first clock terminal RCK, the second clock terminal RCB, the input terminal Rin, the first power supply terminal VGH, the second power supply terminal VGL, and the pull-down control node PD_C. The pull-down control sub-circuit 021 can be used to control the on / off state of the first power supply terminal VGH and the pull-down control node PD_C in response to the first clock signal, and to control the on / off state of the second power supply terminal VGL and the pull-down control node PD_C in response to the second clock signal and the input signal.

[0097] For example, the pull-down control sub-circuit 021 can control the first power supply terminal VGH to conduct with the pull-down control node PD_C when the potential of the first clock signal is the first potential. At this time, the first power supply signal at the first potential can be transmitted to the pull-down control node PD_C. Conversely, the pull-down control sub-circuit 021 can control the first power supply terminal VGH to discouple from the pull-down control node PD_C when the potential of the first clock signal is the second potential.

[0098] Similarly, the pull-down control sub-circuit 021 can control the second power supply terminal VGL to conduct with the pull-down control node PD_C when the potential of the second clock signal and / or the potential of the input signal is the first potential. At this time, the second power supply signal at the second potential can be transmitted to the pull-down control node PD_C. Conversely, the pull-down control sub-circuit 021 can also control the second power supply terminal VGL to decouple from the pull-down control node PD_C when the potential of the second clock signal or the potential of the input signal is the second potential.

[0099] The pull-down sub-circuit 022 can be coupled to the pull-down control node PD_C, the pull-up node PU, the first power supply terminal VGH, the second power supply terminal VGL, and the pull-down node PD, respectively. The pull-down sub-circuit 022 can be used to control the on / off state of the first power supply terminal VGH and the pull-down node PD in response to the potential of the pull-down control node PD_C, and to control the on / off state of the second power supply terminal VGL and the pull-down node PD in response to the potential of the pull-up node PU.

[0100] For example, the pull-down sub-circuit 022 can control the first power supply terminal VGH to be coupled to the pull-down node PD when the potential of the pull-down control node PD_C is at the first potential. At this time, the first power supply signal at the first potential can be transmitted to the pull-down node PD. Furthermore, the pull-down sub-circuit 022 can control the first power supply terminal VGH to be disconnected from the pull-down node PD when the potential of the pull-down control node PD_C is at the second potential.

[0101] Similarly, the pull-down sub-circuit 022 can control the second power supply terminal VGL to couple with the pull-down node PD when the potential of the pull-up node PU is the first potential. At this time, the second power supply signal at the second potential can be transmitted to the pull-down node PD. Furthermore, the pull-down sub-circuit 022 can control the second power supply terminal VGL to disconnect from the pull-down node PD when the potential of the pull-up node PU is the second potential.

[0102] Figure 6 This is a schematic diagram of the structure of another shift register unit provided in an embodiment of this disclosure. For example... Figure 6 As shown, the output circuit 03 described in this embodiment may include: a first output sub-circuit 031 and a second output sub-circuit 032.

[0103] The first output sub-circuit 031 can be coupled to the pull-up node PU, the first power supply terminal VGH, and the output terminal Rout, respectively. The first output sub-circuit 031 is used to control the on / off state of the first power supply terminal VGH and the output terminal Rout in response to the potential of the pull-up node PU.

[0104] For example, the first output sub-circuit 031 can control the first power supply terminal VGH to conduct with the output terminal Rout when the potential of the pull-up node PU is at the first potential. At this time, the first power supply signal at the first potential can be transmitted to the output terminal Rout. Furthermore, the first output sub-circuit 031 can control the first power supply terminal VGH to decouple from the output terminal Rout when the potential of the pull-up node PU is at the second potential.

[0105] The second output sub-circuit 032 can be coupled to the pull-down node PD, the second power supply terminal VGL, and the output terminal Rout, respectively. The second output sub-circuit 032 can be used to control the on / off state of the second power supply terminal VGL and the output terminal Rout in response to the potential of the pull-down node PD.

[0106] For example, the second output sub-circuit 032 can control the second power supply terminal VGL to conduct with the output terminal Rout when the potential of the pull-down node PD is the first potential. At this time, the second power supply signal at the second potential can be transmitted to the output terminal Rout. Also, the second output sub-circuit 032 can control the second power supply terminal VGL to decouple from the output terminal Rout when the potential of the pull-down node PD is the second potential.

[0107] Figure 7 This is a schematic diagram of another shift register unit provided in an embodiment of this disclosure. For example... Figure 7 As shown, the input circuit 01 described in this embodiment may include a first input transistor M1a and a second input transistor M1b connected in series. By including two input transistors in series in the input circuit 01, the leakage current of the input circuit 01 can be reduced, ensuring reliable control of the potential of the pull-up node PU.

[0108] The control electrode (e.g., gate) of the first input transistor M1a and the control electrode of the second input transistor M1b can both be coupled to the first clock terminal RCK. The first electrode of the first input transistor M1a can be coupled to the input terminal Rin. The second electrode of the first input transistor M1a can be coupled to the first electrode of the second input transistor M1b. The second electrode of the second input transistor M1b can be coupled to the pull-up node PU.

[0109] Continue to refer to Figure 7 The pull-down control sub-circuit 021 may include: a first pull-down control transistor M2, a second pull-down control transistor M3, and a third pull-down control transistor M4.

[0110] The control electrode of the first pull-down control transistor M2 can be coupled to the first clock terminal RCK, the first electrode of the first pull-down control transistor M2 can be coupled to the first power supply terminal VGH, and the second electrode of the first pull-down control transistor M2 is coupled to the pull-down control node PD_C.

[0111] The control terminal of the second pull-down control transistor M3 can be coupled to the input terminal Rin, the first terminal of the second pull-down control transistor M3 can be coupled to the second power supply terminal VGL, and the second terminal of the second pull-down control transistor M3 can be coupled to the pull-down control node PD_C.

[0112] The control terminal of the third pull-down control transistor M4 can be coupled to the second clock terminal RCB, the first terminal of the second pull-down control transistor M3 can be coupled to the second power supply terminal VGL, and the second terminal of the second pull-down control transistor M3 can be coupled to the pull-down control node PD_C.

[0113] Optionally, in this embodiment of the present disclosure, the resistance of the first pull-down control transistor M2 can be greater than the resistance of the second pull-down control transistor M3. In this way, when both the first pull-down control transistor M2 and the second pull-down control transistor M3 are turned on, it can be ensured that the second power supply signal of the second potential is reliably transmitted from the second power supply terminal VGL to the control node PD_C.

[0114] Continue to refer to Figure 7 The pull-down sub-circuit 022 may include: a first pull-down transistor M5 and a second pull-down transistor M6.

[0115] The control electrode of the first pull-down transistor M5 can be coupled to the pull-down control node PD_C, the first electrode of the first pull-down transistor M5 can be coupled to the first power supply terminal VGH, and the second electrode of the first pull-down transistor M5 can be coupled to the pull-down node PD.

[0116] The control terminal of the second pull-down transistor M6 can be coupled to the pull-up node PU, the first terminal of the second pull-down transistor M6 can be coupled to the second power supply terminal VGL, and the second terminal of the second pull-down transistor M6 can be coupled to the pull-down node PD.

[0117] Continue to refer to Figure 7 The first output sub-circuit 031 may include: a first output transistor M7 and a second capacitor C2.

[0118] The control electrode of the first output transistor M7 can be coupled to the pull-up node PU, the first electrode of the first output transistor M7 can be coupled to the first power supply terminal VGH, and the second electrode of the first output transistor M7 can be coupled to the output terminal Rout.

[0119] The first terminal of the second capacitor C2 can be coupled to the control electrode of the first output transistor M7, and the second terminal of the second capacitor C2 can be coupled to the second electrode of the first output transistor M7.

[0120] Continue to refer to Figure 7 The second output sub-circuit 032 may include: a second output transistor M8 and a third capacitor C3.

[0121] The control electrode of the second output transistor M8 can be coupled to the pull-down node PD, the first electrode of the second output transistor M8 can be coupled to the second power supply terminal VGL, and the second electrode of the second output transistor M8 can be coupled to the output terminal Rout.

[0122] The first terminal of the third capacitor C3 can be coupled to the control terminal of the second output transistor M8, and the second terminal of the third capacitor C3 can be coupled to the first terminal of the second output transistor M8.

[0123] Optional, in Figure 7 Based on the structure shown, refer to Figure 8 This illustrates yet another shift register unit provided in an embodiment of the present disclosure. For example... Figure 8 As shown, the shift register unit described in this embodiment may further include: input control circuit 04.

[0124] The input control circuit 04 can be coupled to the pull-up node PU and the first power supply terminal VGH, respectively, and can also be coupled to the series node CBC of the first input transistor M1a and the second input transistor M1b. The input control circuit 04 can be used to control the on / off state of the first power supply terminal VGH and the series node CBC in response to the potential of the pull-up node PU.

[0125] For example, the input control circuit 04 can control the first power supply terminal VGH to conduct with the series node CBC when the potential of the pull-up node PU is at the first potential. At this time, the first power supply signal at the first potential can be transmitted to the series node CBC. Furthermore, the input control circuit 04 can control the first power supply terminal VGH to disconnect from the series node CBC when the potential of the pull-up node PU is at the second potential. This avoids leakage at the series node CBC, thereby ensuring reliable charging of the pull-up node PU, that is, ensuring that the potential of the pull-up node PU is reliably maintained at the first potential.

[0126] Optional, Figure 9 A schematic diagram of another shift register unit provided in an embodiment of this disclosure is shown. Figure 9 As shown, the shift register unit described in this embodiment may further include a potential adjustment circuit 05.

[0127] The potential adjustment circuit 05 can be coupled to the pull-down control node PD_C and the pull-down node PD, respectively. The potential adjustment circuit 05 can be used to adjust the potential of the pull-down control node PD_C and the pull-down node PD. This ensures the potential stability of the pull-down control node PD_C and the pull-down node PD.

[0128] For example, in Figure 8 and Figure 9 On this basis, Figure 10 A schematic diagram of another shift register unit provided in an embodiment of this disclosure is shown. Figure 10 As shown, the input control circuit 04 described in this embodiment may include an input control transistor M1c. The potential adjustment circuit 05 may include a first capacitor C1.

[0129] The control electrode of the input control transistor M1c can be coupled to the pull-up node PU, the first electrode of the input control transistor M1c can be coupled to the first power supply terminal VGH, and the second electrode of the input control transistor M1c can be coupled to the series node CBC.

[0130] The first terminal of the first capacitor C1 can be coupled to the pull-down control node PD_C, and the second terminal of the first capacitor C1 can be coupled to the pull-down node PD. Based on this, it can be seen that the potential adjustment circuit 05 can reliably adjust the potential of the pull-down control node PD_C and the pull-down node PD through its own bootstrap function.

[0131] It should be noted that the above Figure 10 The shift register unit shown is a 10T3C (i.e., including 10 transistors and 3 capacitors) shift register unit. Furthermore, in the above embodiments, the description is based on the example of each transistor being an N-type transistor and an Oxide transistor, with the first potential being higher than the second potential.

[0132] In summary, this disclosure provides a shift register unit. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit controls the connection and disconnection between the input terminal and the pull-up node to control the potential of the pull-up node. The pull-down circuit controls the connection and disconnection between the first power supply terminal and the second power supply terminal and the pull-down node to control the potential of the pull-down node. The output circuit responds to the potential of the pull-up node by controlling the connection and disconnection between the first power supply terminal and the output terminal, and responds to the potential of the pull-down node by controlling the connection and disconnection between the second power supply terminal and the output terminal, thereby transmitting a first power supply signal at the first potential and a second power supply signal at the second potential to the output terminal. The output terminal is used to couple with a reset signal terminal. Thus, the input signal provided by the input terminal can be flexibly set based on the light emission control signal, enabling reliable transmission of the reset signal to the reset signal terminal of the pixel circuit through the shift register unit, thereby enabling the pixel circuit to reliably drive the light-emitting element to emit light.

[0133] Figure 11 This disclosure provides a driving method for a shift register unit, which is used to drive the shift register unit as shown in the above figures. Figure 11 As shown, the method includes:

[0134] Step 1101, First stage: The potential of the first clock signal provided by the first clock terminal is the first potential; the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are the second potential; the input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node; the pull-down control circuit responds to the first clock signal, the second clock signal, the input signal, and the second power signal provided by the second power terminal and controls the first power terminal to be connected to the pull-down node; the output circuit responds to the potential of the pull-down node and controls the second power terminal to be connected to the output terminal.

[0135] Step 1102, Second Stage: The potential of the first clock signal and the potential of the input signal are the first potential, and the potential of the second clock signal is the second potential. The input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node. The pull-down control circuit responds to the first clock signal, the second clock signal, the input signal, and the second power supply signal and controls the second power supply terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node and controls the first power supply terminal to be connected to the output terminal.

[0136] The potential of the first power signal provided by the first power supply terminal can be a first potential, and the potential of the second power signal can be a second potential.

[0137] Optional, with Figure 10 The shift register unit shown here, in which the input terminal Rin is coupled to the input enable terminal RSTV, and each transistor is an N-type transistor, with the first potential (i.e., the effective potential) being high and the second potential (i.e., the ineffective potential) being low, is used as an example to describe in detail the driving principle of the shift register unit described in this embodiment:

[0138] Example, Figure 12 This is a timing diagram of each signal terminal in a shift register unit provided in an embodiment of this disclosure. For example... Figure 12 As shown, the entire driving process can be divided into 10 stages, from 1 to 10.

[0139] In the first stage 1, the potential of the first clock signal provided by the first clock terminal RCK is high, while the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) and the potential of the second clock signal provided by the second clock terminal RCB are both low. Based on this, the first input transistor M1a, the second input transistor M1b, and the first pull-down control transistor M2 are all turned on, while the second pull-down control transistor M3 and the third pull-down control transistor M4 are all turned off. Correspondingly, firstly, the input terminal Rin is connected to the pull-up node PU, and the low-potential input signal can be transmitted to the pull-up node PU via the turned-on first input transistor M1a and second input transistor M1b, thereby discharging the pull-up node PU, at which point the potential of the pull-up node PU is low. Based on this, the second pull-down transistor M6, the first output transistor M7, and the input control transistor M1c are all turned off. Secondly, the first power supply terminal VGH is connected to the pull-down control node PD_C. A high-level first power supply signal can be transmitted to the pull-down control node PD_C via the activated first pull-down control transistor M2, thus charging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is high. Based on this, the first pull-down transistor M5 is turned on, and the first power supply terminal VGH is connected to the pull-down node PD. The first power supply signal of the first potential can also be transmitted to the pull-down node PD via the activated first pull-down transistor M5, thus charging the pull-down node PD. At this time, the potential of the pull-down node PD is high. Based on this, the second output transistor M8 is turned on. Correspondingly, the second power supply terminal VGH is connected to the output terminal Rout. The second power supply signal of the second potential can be transmitted to the output terminal Rout via the activated second output transistor M8, thus discharging the output terminal Rout. At this time, the potential of the output terminal Rout is low. Furthermore, under the bootstrap effect of the first capacitor C1, the pull-down node PD can reliably be at a high potential. For example, Figure 13 The equivalent circuit diagram of the shift register unit in the first stage 1 is shown.

[0140] In Phase 2, the potential of the first clock signal provided by the first clock terminal RCK is low, while the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) and the potential of the second clock signal provided by the second clock terminal RCB are both high. The potential of the pull-up node PU is maintained at the low potential of Phase 1 under the action of the second capacitor C2. Based on this, both the second pull-down control transistor M3 and the third pull-down control transistor M4 are turned on. The first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, the input control transistor M1c, the first output transistor M7, and the second pull-down transistor M6 are all turned off. Correspondingly, the second power supply terminal VGL is connected to the pull-down control node PD_C, and the second power supply signal at the second potential can be transmitted to the pull-down control node PD_C via the turned-on second pull-down control transistor M3 and third pull-down control transistor M4, thereby discharging the pull-down control node PD_C, at which point the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Thus, under the bootstrap effect of the first capacitor C1, the pull-down node PD can maintain a high potential in the first stage 1. Based on this, the second output transistor M8 turns on. Correspondingly, the second power supply terminal VGH is connected to the output terminal Rout, and the second power supply signal at the second potential can be transmitted to the output terminal Rout via the turned-on second output transistor M8, thereby continuing to discharge the output terminal Rout, at which time the potential of the output terminal Rout is low. For example, Figure 14 The equivalent circuit diagram of the shift register unit in the second stage 2 is shown.

[0141] In the third stage, the potential of the first clock signal provided by the first clock terminal RCK and the potential of the input signal provided by the input enable terminal RSTV (i.e., input terminal Rin) are both high, while the potential of the second clock signal provided by the second clock terminal RCB is low. Based on this, the first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, and the second pull-down control transistor M3 are all turned on, while the third pull-down control transistor M4 is turned off. Correspondingly, firstly, the first power supply terminal VGH and the second power supply terminal VGL are both connected to the pull-down control node PD_C. However, because the resistance of the first pull-down control transistor M2 is greater than the resistance of the second pull-down control transistor M3, the second power supply signal at the second potential can be transmitted to the pull-down control node PD_C via the turned-on second pull-down control transistor M3, thereby discharging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Secondly, the input terminal Rin is connected to the pull-up node PU. A high-potential input signal can be transmitted to the pull-up node PU via the activated first input transistor M1a and second input transistor M1b, thus charging the pull-up node PU, which is now at a high potential. Based on this, the input control transistor M1c, the first output transistor M7, and the second pull-down transistor M6 are all turned on. Correspondingly, the first power supply terminal VGH is connected to the series node CBC. The first power supply signal of the first potential can be transmitted to the series node CBC via the activated input control transistor M1c, ensuring reliable activation of the first input transistors M1a and M1b. The second power supply terminal VGL is connected to the pull-down node PD. The second power supply signal of the second potential can be transmitted to the pull-down node PD via the activated second pull-down transistor M6, thus discharging the pull-down node PD, which is now at a low potential. Based on this, the second output transistor M8 is turned off. Furthermore, the first power supply terminal VGH is connected to the output terminal Rout, and the first power supply signal at the first potential can be transmitted to the output terminal Rout through the activated first output transistor M7, thereby charging the output terminal Rout. At this time, the potential of the output terminal Rout is high. For example, Figure 15 The equivalent circuit diagram of the shift register unit in stage 3 is shown.

[0142] Furthermore, in the third stage t3, due to the bootstrap effect of the second capacitor C2, the potential of the pull-up node PU can be charged to a higher voltage. At this time, the potential change value of the pull-up node PU is ΔV. PU It can satisfy: ΔV PU =C20 / (CgsM7+C20+C PU )*ΔVRout; C20 refers to the capacitance of the second capacitor C2, CgsM7 refers to the parasitic capacitance of the first output transistor M7, C PUThis refers to the parasitic capacitance value at the pull-up node PU, excluding the parasitic capacitance of the second capacitor C2 and the first output transistor M7. ΔVRout refers to the potential change value at the output terminal Rout. This change value refers to the change value compared to the previous stage.

[0143] In stage 4, the potential of the first clock signal provided by the first clock terminal RCK is low, while the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) and the potential of the second clock signal provided by the second clock terminal RCB are both high. Furthermore, the potential of the pull-up node PU is maintained at the high potential of stage 3 under the action of the second capacitor C2. Based on this, the input control transistor M1c, the second pull-down control transistor M3, the third pull-down control transistor M4, the second pull-down transistor M6, and the first output transistor M7 are all turned on. The first input transistor M1a, the second input transistor M1b, and the first pull-down control transistor M2 are all turned off. Correspondingly, firstly, the first power supply terminal VGH is connected to the series node CBC, and the first power supply signal at the first potential can be transmitted to the series node CBC via the turned-on input control transistor M1c. Secondly, the second power supply terminal VGL is connected to the pull-down control node PD_C. The second power supply signal at the second potential can be transmitted to the pull-down control node PD_C through the enabled second pull-down control transistor M3 and the third pull-down control transistor M4, thereby discharging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Thirdly, the second power supply terminal VGL is connected to the pull-down node PD. The second power supply signal at the second potential can be transmitted to the pull-down node PD through the enabled second pull-down transistor M6, thereby discharging the pull-down node PD. At this time, the potential of the pull-down node PD is low. Based on this, the second output transistor M8 is turned off. Fourthly, the first power supply terminal VGH is connected to the output terminal Rout. The first power supply signal at the first potential can be transmitted to the output terminal Rout through the enabled first output transistor M7, thereby charging the output terminal Rout. At this time, the potential of the output terminal Rout is high. For example, Figure 16 The equivalent circuit diagram of the shift register unit in stage 4 is shown.

[0144] In stage 5, the potential of the first clock signal provided by the first clock terminal RCK and the potential of the input signal provided by the input enable terminal RSTV (i.e., input terminal Rin) are both high, while the potential of the second clock signal provided by the second clock terminal RCB is low. Based on this, the first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, and the second pull-down control transistor M3 are all turned on, while the third pull-down control transistor M4 is turned off. Correspondingly, firstly, the first power supply terminal VGH and the second power supply terminal VGL are both connected to the pull-down control node PD_C. However, because the resistance of the first pull-down control transistor M2 is greater than the resistance of the second pull-down control transistor M3, the second power supply signal at the second potential can be transmitted to the pull-down control node PD_C via the turned-on second pull-down control transistor M3, thereby discharging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Secondly, the input terminal Rin is connected to the pull-up node PU. The high-potential input signal can be transmitted to the pull-up node PU through the enabled first input transistor M1a and second input transistor M1b, thus continuing to charge the pull-up node PU and maintaining its high potential. Based on this, the output control transistor M1c, the first pull-down transistor M6, and the first output transistor M7 are all turned on. Correspondingly, the first power supply terminal VGH is connected to the series node CBC, and the first power supply signal at the first potential can continue to be transmitted to the series node CBC through the enabled input control transistor M1c. The second power supply terminal VGL is connected to the pull-down node PD, and the second power supply signal at the second potential can be transmitted to the pull-down node PD through the enabled second pull-down transistor M6, thus continuing to discharge the pull-down node PD, which is now at a low potential. Based on this, the second output transistor M8 is turned off. Furthermore, the first power supply terminal VGH is connected to the output terminal Rout, and the first power supply signal at the first potential can be transmitted to the output terminal Rout through the turned-on first output transistor M7, thereby continuing to charge the output terminal Rout. At this time, the potential of the output terminal Rout is high. Since the switching states of each transistor in the fifth stage 5 are the same as those in the third stage 3, its equivalent circuit diagram can be referred to... Figure 15 .

[0145] In stage 6, the potential of the first clock signal provided by the first clock terminal RCK is low, while the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) and the potential of the second clock signal provided by the second clock terminal RCB are both high. Furthermore, the potential of the pull-up node PU is maintained at the high potential of stage 5 under the action of the second capacitor C2. Based on this, the input control transistor M1c, the second pull-down control transistor M3, the third pull-down control transistor M4, the second pull-down transistor M6, and the first output transistor M7 are all turned on. The first input transistor M1a, the second input transistor M1b, and the first pull-down control transistor M2 are all turned off. Correspondingly, firstly, the first power supply terminal VGH is connected to the series node CBC, and the first power supply signal at the first potential can be transmitted to the series node CBC via the turned-on input control transistor M1c. Secondly, the second power supply terminal VGL is connected to the pull-down control node PD_C. The second power supply signal at the second potential can be transmitted to the pull-down control node PD_C through the enabled second pull-down control transistor M3 and the third pull-down control transistor M4, thereby discharging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Thirdly, the second power supply terminal VGL is connected to the pull-down node PD. The second power supply signal at the second potential can be transmitted to the pull-down node PD through the enabled second pull-down transistor M6, thereby discharging the pull-down node PD. At this time, the potential of the pull-down node PD is low. Based on this, the second output transistor M8 is turned off. Fourthly, the first power supply terminal VGH is connected to the output terminal Rout. The first power supply signal at the first potential can be transmitted to the output terminal Rout through the enabled first output transistor M7, thereby charging the output terminal Rout. At this time, the potential of the output terminal Rout is high. Since the switching states of the transistors in stage 6 are the same as those in stage 4, their equivalent circuit diagram can be referenced. Figure 16 .

[0146] In stage 7, the potential of the first clock signal provided by the first clock terminal RCK and the potential of the input signal provided by the input enable terminal RSTV (i.e., input terminal Rin) are both high, while the potential of the second clock signal provided by the second clock terminal RCB is low. Based on this, the first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, and the second pull-down control transistor M3 are all turned on, while the third pull-down control transistor M4 is turned off. Correspondingly, firstly, the first power supply terminal VGH and the second power supply terminal VGL are both connected to the pull-down control node PD_C. However, because the resistance of the first pull-down control transistor M2 is greater than the resistance of the second pull-down control transistor M3, the second power supply signal at the second potential can be transmitted to the pull-down control node PD_C via the turned-on second pull-down control transistor M3, thereby discharging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Secondly, the input terminal Rin is connected to the pull-up node PU. The high-potential input signal can be transmitted to the pull-up node PU through the enabled first input transistor M1a and second input transistor M1b, thus continuing to charge the pull-up node PU and maintaining its high potential. Based on this, the output control transistor M1c, the first pull-down transistor M6, and the first output transistor M7 are all turned on. Correspondingly, the first power supply terminal VGH is connected to the series node CBC, and the first power supply signal at the first potential can continue to be transmitted to the series node CBC through the enabled input control transistor M1c. The second power supply terminal VGL is connected to the pull-down node PD, and the second power supply signal at the second potential can be transmitted to the pull-down node PD through the enabled second pull-down transistor M6, thus continuing to discharge the pull-down node PD, which is now at a low potential. Based on this, the second output transistor M8 is turned off. Furthermore, the first power supply terminal VGH is connected to the output terminal Rout, and the first power supply signal at the first potential can be transmitted to the output terminal Rout through the turned-on first output transistor M7, thereby continuing to charge the output terminal Rout. At this time, the potential of the output terminal Rout is high. Since the switching states of each transistor in stage 7 are the same as those in stage 5, and the switching states of each transistor in stage 5 are the same as those in stage 3, their equivalent circuit diagram can be referenced. Figure 15 .

[0147] In stage 8, the potential of the first clock signal provided by the first clock terminal RCK and the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) are both low, while the potential of the second clock signal provided by the second clock terminal RCB is high. Furthermore, the potential of the pull-up node PU is maintained at the high potential of stage 7 under the action of the second capacitor C2. Based on this, the first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, and the second pull-down control transistor M3 are all turned off, while the third pull-down control transistor M4, the second pull-down transistor M6, and the first output transistor M7 are all turned on. Correspondingly, firstly, the second power supply terminal VGL is connected to the pull-down control node PD_C, and the second power supply signal at the second potential is transmitted to the pull-down control node PD_C through the turned-on third pull-down control transistor M4, thereby discharging the pull-down control node PD_C, at which point the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Secondly, the first power supply terminal VGH is connected to the series node CBC, and the first power supply signal at the first potential can continue to be transmitted to the series node CBC via the enabled input control transistor M1c. Thirdly, the second power supply terminal VGL is connected to the pull-down node PD, and the second power supply signal at the second potential can be transmitted to the pull-down node PD via the enabled second pull-down transistor M6, thereby continuing to discharge the pull-down node PD. At this time, the potential of the pull-down node PD is low. Based on this, the second output transistor M8 is turned off. Fourthly, the first power supply terminal VGH is connected to the output terminal Rout, and the first power supply signal at the first potential can be transmitted to the output terminal Rout via the enabled first output transistor M7, thereby continuing to charge the output terminal Rout. At this time, the potential of the output terminal Rout is high. For example, Figure 17 The equivalent circuit diagram of the shift register unit in stage 8 is shown.

[0148] In stage 9, the potential of the first clock signal provided by the first clock terminal RCK is high, while the potential of the input signal provided by the input enable terminal RSTV (i.e., the input terminal Rin) and the potential of the second clock signal provided by the second clock terminal RCB are both low. Based on this, the first input transistor M1a, the second input transistor M1b, and the first pull-down control transistor M2 are all turned on, while the second pull-down control transistor M3 and the third pull-down control transistor M4 are all turned off. Correspondingly, firstly, the input terminal Rin is connected to the pull-up node PU, and the low-potential input signal can be transmitted to the pull-up node PU via the turned-on first input transistor M1a and second input transistor M1b, thereby discharging the pull-up node PU, at which point the potential of the pull-up node PU is low. Based on this, the second pull-down transistor M6, the first output transistor M7, and the input control transistor M1c are all turned off. Secondly, the first power supply terminal VGH is connected to the pull-down control node PD_C. The high-potential first power signal can be transmitted to the pull-down control node PD_C via the activated first pull-down control transistor M2, thereby charging the pull-down control node PD_C. At this time, the potential of the pull-down control node PD_C is high. Based on this, the first pull-down transistor M5 is turned on, and the first power supply terminal VGH is connected to the pull-down node PD. The first-potential first power signal can also be transmitted to the pull-down node PD via the activated first pull-down transistor M5, thereby charging the pull-down node PD. At this time, the potential of the pull-down node PD is high. Based on this, the second output transistor M8 is turned on. Correspondingly, the second power supply terminal VGH is connected to the output terminal Rout. The second-potential second power signal can be transmitted to the output terminal Rout via the activated second output transistor M8, thereby discharging the output terminal Rout. At this time, the potential of the output terminal Rout is low. Furthermore, under the bootstrap effect of the first capacitor C1, the pull-down node PD can reliably be at a high potential. Since the switching states of the transistors in stage 9 are the same as in stage 1, their equivalent circuit diagram can be referenced. Figure 13 .

[0149] Furthermore, in stage 9, due to the bootstrap effect of the second capacitor C2, the potential of the pull-down control node PD_C can be charged to a higher voltage. At this time, the potential change value ΔV of the pull-down control node PD_C is... PD_C It can satisfy: ΔV PD_C =C10 / (CgsM5+C10+C PD_C )*ΔV PD C10 refers to the capacitance of the first capacitor C1, and CgsM5 refers to the parasitic capacitance of the first pull-down transistor M5. PD_C This refers to the parasitic capacitance value at the pull-down control node PD_C, excluding the parasitic capacitance of the first capacitor C1 and the first pull-down transistor M5, ΔV. PDThis refers to the change in potential of the pull-down node PD. The change here refers to the change between the current stage and the previous stage.

[0150] In stage 10, the potential of the first clock signal provided by the first clock terminal RCK and the potential of the input signal provided by the input enable terminal RSTV (i.e., input terminal Rin) are both low, while the potential of the second clock signal provided by the second clock terminal RCB is high. Furthermore, the potential of the pull-up node PU is maintained at the low potential of stage 9 under the action of the second capacitor C2. The potential of the pull-down node PD is maintained at the high potential of stage 9 under the action of the first capacitor C1. Based on this, the first input transistor M1a, the second input transistor M1b, the first pull-down control transistor M2, the second pull-down control transistor M3, the first output transistor M7, the output control transistor M1c, and the second pull-down transistor M6 are all turned off, while the third pull-down control transistor M4 and the second output transistor M8 are both turned on. Correspondingly, firstly, the second power supply terminal VGL is connected to the pull-down control node PD_C, and the low-potential second power supply signal can be transmitted to the pull-down control node PD_C via the turned-on third pull-down control transistor M4, thereby discharging the pull-down control node PD_C, at which point the potential of the pull-down control node PD_C is low. Based on this, the first pull-down transistor M5 is turned off. Secondly, the second power supply terminal VGH is connected to the output terminal Rout, and the second power supply signal at the second potential can be transmitted to the output terminal Rout through the turned-on second output transistor M8, thereby continuing to discharge the output terminal Rout. At this time, the potential of the output terminal Rout is low. For example, Figure 18 The equivalent circuit diagram of the shift register unit in stage 10 is shown.

[0151] in, Figures 13 to 18 In the diagram, the "×" marked with a dashed line is used to indicate that the transistor is off. Furthermore, Figures 13 to 18 The text also indicates the direction of signal flow for high and low potentials. Figure 12 On this basis, Figure 19 A signal simulation diagram is shown, illustrating the timing of the output Rout of eight cascaded shift register units 00. The horizontal axis represents time in microseconds (μs), and the horizontal axis represents voltage in volts (V). Furthermore, it should be noted that the first stage of step 1101 may refer to the first stage 1 described in the above embodiment, and the second stage may refer to the third stage 3 described in the above embodiment.

[0152] In summary, this disclosure provides a driving method for a shift register unit. In this method, the shift register unit includes an input circuit capable of controlling the on / off state of the input terminal and the pull-up node to control the potential of the pull-up node. A pull-down circuit capable of controlling the on / off state of the first power supply terminal and the second power supply terminal and the pull-down node to control the potential of the pull-down node. An output circuit capable of controlling the on / off state of the first power supply terminal and the output terminal in response to the potential of the pull-up node, and capable of controlling the on / off state of the second power supply terminal and the output terminal in response to the potential of the pull-down node, thereby transmitting a first power supply signal at the first potential and a second power supply signal at the second potential to the output terminal. The output terminal is used to couple with a reset signal terminal. Thus, the input signal provided by the input terminal can be flexibly set based on the light emission control signal, enabling reliable transmission of a reset signal to the reset signal terminal of the pixel circuit through the shift register unit, thereby enabling the pixel circuit to reliably drive the light-emitting element to emit light.

[0153] Figure 20 This is a schematic diagram of a reset drive circuit provided in an embodiment of this disclosure. Figure 20 As shown, the reset drive circuit includes at least two cascaded shift register units 00 as shown in the above figures. Furthermore, as described in the above embodiment, the input terminal Rin of the first-stage shift register unit 00 can be coupled to the reset enable terminal RSTV. In the other stages of shift register units 00 besides the first-stage shift register unit 00, the input terminal Rin of each stage of shift register unit 00 can be coupled to the output terminal Rout of the cascaded previous-stage shift register unit 00.

[0154] Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 21 As shown, the display device includes: a display panel 100, and as shown in the figure. Figure 20 The reset drive circuit 000 is shown.

[0155] The display panel 100 may include multiple pixels, and the pixels may include, for example, Figure 2 or Figure 3 The pixel circuit P1 and the light-emitting element L1 are shown. The pixel circuit P1 can be coupled to the reset signal terminal Rst1(n), the light-emitting control terminal EM(n), and the light-emitting element L1, respectively. It can be used to drive the light-emitting element L1 to emit light in response to the reset signal from the reset signal terminal Rst1(n) and the light-emitting control signal from the light-emitting control terminal EM(n). The reset drive circuit 000 can be coupled to the reset signal terminal Rst1(n) and is used to provide a reset signal to the reset signal terminal Rst1(n).

[0156] Optionally, as described in the above embodiments, the pixel circuit P1 may include a plurality of transistors, and the plurality of transistors may all be N-type oxide transistors.

[0157] Optionally, the display device can be any product or component with display functionality, such as an OLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, or navigator.

[0158] It should be understood that the terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0159] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0160] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0161] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0162] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0163] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0164] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the reset drive circuit, shift register unit, each circuit and each sub-circuit described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0165] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A shift register unit, characterized in that, The shift register unit includes: The input circuit is coupled to the first clock terminal, the input terminal, and the pull-up node respectively, and is used to control the on / off state of the input terminal and the pull-up node in response to the first clock signal provided by the first clock terminal. The pull-down circuit is coupled to the first clock terminal, the pull-up node, the input terminal, the first power supply terminal, the second clock terminal, the second power supply terminal, and the pull-down node, respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the first clock signal, the second clock signal provided by the second clock terminal, the input signal provided by the input terminal, and the second power supply signal provided by the second power supply terminal, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the pull-up node; The output circuit is coupled to the pull-up node, the pull-down node, the first power supply terminal, the second power supply terminal, and the output terminal, respectively, and is used to control the on / off state of the first power supply terminal and the output terminal in response to the potential of the pull-up node, and to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the pull-down node; the output terminal is coupled to the reset signal terminal of the pixel circuit, and the pulse width of the input signal is not greater than the pulse width of the light emission control signal provided by the light emission control terminal of the pixel circuit; The input circuit includes: a first input transistor and a second input transistor connected in series; The control terminals of the first and second input transistors are both coupled to the first clock terminal. The first terminal of the first input transistor is coupled to the input terminal. The second terminal of the first input transistor is coupled to the first terminal of the second input transistor. The second terminal of the second input transistor is coupled to the pull-up node.

2. The shift register unit according to claim 1, characterized in that, The shift register unit further includes: an input control circuit; The input control circuit is coupled to the pull-up node and the first power supply terminal respectively, and is also coupled to the series node of the first input transistor and the second input transistor, and is used to control the on / off state of the first power supply terminal and the series node in response to the potential of the pull-up node.

3. The shift register unit according to claim 2, characterized in that, The input control circuit includes: an input control transistor; The control electrode of the input control transistor is coupled to the pull-up node, the first electrode of the input control transistor is coupled to the first power supply terminal, and the second electrode of the input control transistor is coupled to the series node.

4. The shift register unit according to any one of claims 1 to 3, characterized in that, The pull-down circuit includes: a pull-down control sub-circuit and a pull-down circuit; The pull-down control sub-circuit is coupled to the first clock terminal, the second clock terminal, the input terminal, the first power terminal, the second power terminal, and the pull-down control node, respectively, and is used to control the on / off state of the first power terminal and the pull-down control node in response to the first clock signal, and to control the on / off state of the second power terminal and the pull-down control node in response to the second clock signal and the input signal. The pull-down sub-circuit is coupled to the pull-down control node, the pull-up node, the first power supply terminal, the second power supply terminal, and the pull-down node, respectively, and is used to control the connection and disconnection between the first power supply terminal and the pull-down node in response to the potential of the pull-down control node, and to control the connection and disconnection between the second power supply terminal and the pull-down node in response to the potential of the pull-up node.

5. The shift register unit according to claim 4, characterized in that, The pull-down control sub-circuit includes: a first pull-down control transistor, a second pull-down control transistor, and a third pull-down control transistor; The control terminal of the first pull-down control transistor is coupled to the first clock terminal, the first terminal of the first pull-down control transistor is coupled to the first power supply terminal, and the second terminal of the first pull-down control transistor is coupled to the pull-down control node. The control electrode of the second pull-down control transistor is coupled to the input terminal, the first electrode of the second pull-down control transistor is coupled to the second power supply terminal, and the second electrode of the second pull-down control transistor is coupled to the pull-down control node. The control electrode of the third pull-down control transistor is coupled to the second clock terminal, the first electrode of the second pull-down control transistor is coupled to the second power supply terminal, and the second electrode of the second pull-down control transistor is coupled to the pull-down control node.

6. The shift register unit according to claim 4, characterized in that, The pull-down sub-circuit includes: a first pull-down transistor and a second pull-down transistor; The control electrode of the first pull-down transistor is coupled to the pull-down control node, the first electrode of the first pull-down transistor is coupled to the first power supply terminal, and the second electrode of the first pull-down transistor is coupled to the pull-down node. The control terminal of the second pull-down transistor is coupled to the pull-up node, the first terminal of the second pull-down transistor is coupled to the second power supply terminal, and the second terminal of the second pull-down transistor is coupled to the pull-down node.

7. The shift register unit according to claim 5 or 6, characterized in that, The shift register unit further includes: a potential adjustment circuit; The potential adjustment circuit is coupled to the pull-down control node and the pull-down node respectively, and is used to adjust the potential of the pull-down control node and the potential of the pull-down node.

8. The shift register unit according to claim 7, characterized in that, The potential adjustment circuit includes: a first capacitor; The first end of the first capacitor is coupled to the pull-down control node, and the second end of the first capacitor is coupled to the pull-down node.

9. The shift register unit according to any one of claims 1 to 3, characterized in that, The output circuit includes: a first output sub-circuit and a second output sub-circuit; The first output sub-circuit is coupled to the pull-up node, the first power supply terminal and the output terminal respectively, and is used to control the on / off state of the first power supply terminal and the output terminal in response to the potential of the pull-up node; The second output sub-circuit is coupled to the pull-down node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the pull-down node.

10. The shift register unit according to claim 9, characterized in that, The first output sub-circuit includes: a first output transistor and a second capacitor; The control electrode of the first output transistor is coupled to the pull-up node, the first electrode of the first output transistor is coupled to the first power supply terminal, and the second electrode of the first output transistor is coupled to the output terminal. The first terminal of the second capacitor is coupled to the control electrode of the first output transistor, and the second terminal of the second capacitor is coupled to the second electrode of the first output transistor.

11. The shift register unit according to claim 9, characterized in that, The second output sub-circuit includes: a second output transistor and a third capacitor; The control electrode of the second output transistor is coupled to the pull-down node, the first electrode of the second output transistor is coupled to the second power supply terminal, and the second electrode of the second output transistor is coupled to the output terminal. The first terminal of the third capacitor is coupled to the control electrode of the second output transistor, and the second terminal of the third capacitor is coupled to the first electrode of the second output transistor.

12. A method for driving a shift register unit, characterized in that, The method is used to drive a shift register unit as described in any one of claims 1 to 11, the method comprising: In the first stage, the potential of the first clock signal provided by the first clock terminal is the first potential, the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are the second potential. The input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node. The pull-down control circuit responds to the first clock signal, the second clock signal, the input signal and the second power signal provided by the second power terminal and controls the first power terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-down node and controls the second power terminal to be connected to the output terminal. In the second stage, the potential of the first clock signal and the potential of the input signal are the first potential, and the potential of the second clock signal is the second potential. The input circuit responds to the first clock signal and controls the input terminal to be connected to the pull-up node. The pull-down control circuit responds to the first clock signal, the second clock signal, the input signal, and the second power signal and controls the second power terminal to be connected to the pull-down node. The output circuit responds to the potential of the pull-up node and controls the first power terminal to be connected to the output terminal. Wherein, the potential of the first power signal provided by the first power supply terminal is the first potential, and the potential of the second power signal is the second potential.

13. A reset drive circuit, characterized in that, The reset drive circuit includes: at least two cascaded shift register units as described in any one of claims 1 to 11; In this system, the input terminal of the first-stage shift register unit is coupled to the reset enable terminal. In other shift register units besides the first-stage shift register unit, the input terminal of each shift register unit is coupled to the output terminal of the cascaded previous-stage shift register unit.

14. A display device, characterized in that, The display device includes: a display panel, and a reset drive circuit as described in claim 13; The display panel includes a plurality of pixels, each pixel including a pixel circuit and a light-emitting element. The pixel circuit is coupled to a reset signal terminal, a light-emitting control terminal and the light-emitting element respectively, and is used to drive the light-emitting element to emit light in response to a reset signal from the reset signal terminal and a light-emitting control signal from the light-emitting control terminal. The reset drive circuit is coupled to the reset signal terminal and is used to provide a reset signal to the reset signal terminal.

15. The display device according to claim 14, characterized in that, The pixel circuit includes multiple transistors, and all of the multiple transistors are N-type oxide transistors.

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