IGBT drive protection control circuit and equipment

Abstract

The present invention discloses an IGBT drive protection control circuit and device. The IGBT drive protection control circuit includes: a signal acquisition circuit for acquiring a circuit fault detection signal, and outputting a fault protection signal when determining that a circuit fault occurs according to the fault detection signal; a drive isolation circuit for driving an IGBT module and outputting a first fault feedback signal when an IGBT module fault is detected; a hardware protection circuit for outputting a first off-wave signal and a fault signal when receiving a fault protection signal or a first fault feedback signal; a control module for outputting a second off-wave signal in response to a fault signal or a first fault feedback signal or a fault protection signal; and a PWM output circuit for stopping outputting a PWM pulse signal in response to at least one of the first off-wave signal and the second off-wave signal. The circuit can realize the software and hardware protection functions of the IGBT module in multiple paths, thereby improving reliability.

Description

Technical Field

[0001] The present invention relates to the field of IGBT protection technology, and in particular to an IGBT drive protection control circuit and device. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor) and MOS (Metal-Oxide-Semiconductor Field-Effect Transistor). It has the advantages of high input impedance of MOSFET and low on-state voltage drop of GTR (Giant Transistor). It can be widely used in AC motors, inverters, switching power supplies, lighting circuits, traction drives and other fields.

[0003] However, due to the fast switching speed of high-power IGBT modules, faults such as overvoltage, overcurrent, overtemperature, short circuit, and false start-up may occur during operation. Especially for IGBTs with half-bridge topology, the upper and lower bridge arms cannot be turned on at the same time. If the design is unreasonable or the protection is not timely, the bridge arm short circuit is very likely to occur, causing the machine to explode. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide an IGBT drive protection control circuit, which can realize software and hardware protection of the IGBT module in multiple paths and improve reliability.

[0005] A second object of the present invention is to provide a device.

[0006] In order to solve the above problems, an embodiment of the first aspect of the present invention provides an IGBT drive protection control circuit, including: a signal acquisition circuit, used to acquire a circuit fault detection signal, and output a fault protection signal when it is determined that the circuit fails according to the fault detection signal; a first drive isolation circuit, wherein a first output end of the first drive isolation circuit is connected to an IGBT module, used to drive the IGBT module and output a first fault feedback signal when a fault of the IGBT module is detected; a hardware protection circuit, wherein a first input end of the hardware protection circuit is connected to an output end of the signal acquisition circuit, and a second input end of the hardware protection circuit is connected to a second output end of the first drive isolation circuit, used to output a first fault feedback signal when a fault of the IGBT module is detected. outputting a first OFF signal and a fault signal when receiving the fault protection signal or the first fault feedback signal; a control module, wherein the first input end of the control module is connected to the second output end of the hardware protection circuit, and the second input end of the control module is connected to the second output end of the first drive isolation circuit, for outputting a second OFF signal in response to the fault signal or the first fault feedback signal, or the first input end of the control module is connected to the output end of the signal acquisition circuit, and the second input end of the control module is connected to the second output end of the first drive isolation circuit, for outputting the second OFF signal in response to the fault protection signal or the first fault feedback signal; a PWM (Pulse width modulation) output circuit, wherein the first input end of the PWM output circuit is connected to the first output end of the hardware protection circuit, and the second input end of the PWM output circuit is connected to the first output end of the control module, for stopping outputting a PWM pulse signal in response to at least one of the first OFF signal and the second OFF signal.

[0007] According to the IGBT drive protection control circuit of the embodiment of the present invention, whether the circuit is faulty is detected by the signal acquisition circuit, and when the circuit fails, such as overvoltage, overcurrent, overtemperature, etc., a fault protection signal is sent to the hardware protection circuit, and the hardware protection circuit outputs a first off-wave signal to stop the PWM output circuit from outputting the PWM pulse signal, thereby realizing the hardware off-wave function. At the same time, the signal acquisition circuit can directly send the fault protection signal to the control module, or the hardware protection circuit can output the fault signal to the control module, and the control module outputs a second off-wave signal to control the PWM output circuit to stop outputting the PWM pulse signal, thereby realizing software protection for the IGBT module. In addition, whether the IGBT module is faulty is detected by the first drive isolation circuit, and when it is determined that the IGBT module fails, a first fault feedback signal is sent to the hardware protection circuit and the control module to form a closed-loop control to effectively protect the IGBT module. Thus, the multi-path protection function that can be off-wave in both software and hardware is realized in the above manner, thereby improving reliability.

[0008] In some embodiments, the hardware protection circuit includes: a first signal receiving unit, the input end of the first signal receiving unit is connected to the signal acquisition circuit, and is used to receive the fault protection signal; a second signal receiving unit, the input end of the second signal receiving unit is connected to the first drive isolation circuit, and is used to receive the first fault feedback signal; a latch unit, the first input end of the latch unit is connected to the output end of the first signal receiving unit and the output end of the second signal receiving unit, the second input end of the latch unit is connected to the second output end of the control module, the first output end of the latch unit is connected to the first input end of the PWM output circuit, and the second output end of the latch unit is connected to the first input end of the control module, and is used to latch the fault protection signal and the first fault feedback signal and output the first off-wave signal to the PWM output circuit and output the fault signal to the control module.

[0009] In some embodiments, the latch unit includes: the control module, which is also used to output a fault clearing signal when the circuit returns to normal; the latch unit, which is also used to clear the fault protection signal and the first fault feedback signal in response to the fault clearing signal.

[0010] In some embodiments, the hardware protection circuit also includes: a crash detection unit, the input end of the crash detection unit is connected to the third output end of the control module, the output end of the crash detection unit is connected to the first input end of the latch unit, and is used to detect the operating state of the control module and output a control abnormality signal when the operating state is abnormal; the latch unit is also used to output the first off-wave signal according to the control abnormality signal.

[0011] In some embodiments, the hardware protection circuit also includes: a prompt unit, a first end of the prompt unit is connected to the first output end of the latch unit and the second output end of the latch unit, a second end of the prompt unit is connected to the first input end of the PWM output circuit and the first input end of the control module, and a third end of the prompt unit is grounded, for providing a fault prompt in response to the fault protection signal or the first fault feedback signal.

[0012] In some embodiments, the drive isolation circuit includes N drive isolation units connected to the IGBT module, each of the drive isolation units includes an upper bridge arm drive sub-unit and a lower bridge arm drive sub-unit; the IGBT drive protection control circuit also includes N interlocking circuits, the first input ends of the N interlocking circuits are connected to the output end of the PWM output circuit, the second input ends of the N interlocking circuits are correspondingly connected to the output ends of the N drive isolation units, and the output ends of the N interlocking circuits are correspondingly connected to the input ends of the N drive isolation units, for interlocking the upper bridge arm drive sub-unit and the lower bridge arm drive sub-unit in each of the drive isolation units.

[0013] In some embodiments, the drive isolation unit also includes: an IGBT drive chip, the IGBT drive chip includes an internal current source and a comparator; an IGBT desaturation detection unit, the first end of the IGBT desaturation detection unit is connected to the IGBT module, the second end of the IGBT desaturation detection unit is connected to the internal current source, and the third end of the IGBT desaturation detection unit is connected to the input end of the comparator, for detecting a short-circuit signal of the IGBT module; when the short-circuit signal exceeds the inversion threshold of the comparator, the IGBT drive chip stops outputting the IGBT drive signal and sends the first fault feedback signal to the interlock circuit, the hardware protection circuit and the control module; the interlock circuit is also used to stop outputting the PWM pulse signal when receiving the first fault feedback signal.

[0014] In some embodiments, the IGBT desaturation detection unit includes: a capacitor subunit, a first end of the capacitor subunit is connected to the internal current source, a second end of the capacitor subunit is connected to the input end of the comparator, and a third end of the capacitor subunit is grounded; a resistor subunit, a first end of the resistor subunit is connected to the second end of the capacitor subunit; a diode subunit, an anode end of the diode subunit is connected to the second end of the resistor subunit, and a cathode end of the diode subunit is connected to the IGBT module.

[0015] In some embodiments, N=1 or N=2.

[0016] A second aspect of the present invention provides a device, including: an IGBT module; the IGBT drive protection control circuit described in the above embodiment, wherein the IGBT drive protection control circuit is connected to the IGBT module.

[0017] According to the device of the embodiment of the present invention, by adopting the IGBT drive protection control circuit provided by the above embodiment, the IGBT module can be effectively protected and the reliability of the device can be improved.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1 is a structural block diagram of an IGBT drive protection control circuit according to an embodiment of the present invention;

[0021] Figure 2 is a structural block diagram of an IGBT drive protection control circuit according to another embodiment of the present invention;

[0022] Figure 3 is a circuit diagram of a PWM output circuit according to an embodiment of the present invention;

[0023] Figure 4 is a circuit diagram of a hardware protection circuit according to an embodiment of the present invention;

[0024] Figure 5 is a circuit diagram of a deadlock detection unit according to an embodiment of the present invention;

[0025] Figure 6 is a circuit diagram of a driving isolation circuit according to an embodiment of the present invention;

[0026] Figure 7 is a circuit diagram of an interlock circuit according to an embodiment of the present invention;

[0027] Figure 8 is a working flow chart of an IGBT drive protection control circuit according to an embodiment of the present invention;

[0028] Fig. 9 is a structural block diagram of a device according to an embodiment of the present invention.

[0029] Reference numerals:

[0030] IGBT drive protection control circuit 10; device 20;

[0031] Signal acquisition circuit 1; drive isolation circuit 2; hardware protection circuit 3; control module 4; PWM output circuit 5; interlocking circuit 6;

[0032] A first signal receiving unit 11; a second signal receiving unit 12; a latch unit 13; a drive isolation unit 14; a freeze detection unit 16; a prompt unit 17; an IGBT drive chip 18; an IGBT desaturation detection unit 19; a capacitor subunit 21; a resistor subunit 22; a diode subunit 23; an upper bridge arm drive subunit 24; and a lower bridge arm drive subunit 25. DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0034] In the related art, for the driving protection control of IGBT, the protection path is single and the reliability is not high.

[0035] In order to solve the above problems, a first embodiment of the present invention provides an IGBT drive protection control circuit. The circuit can be used to implement software and hardware protection of the IGBT module in multiple paths, thereby improving reliability.

[0036] like Figure 1 As shown in FIG. 2 , the IGBT drive protection control circuit 10 of the embodiment of the present invention includes a signal acquisition circuit 1 , a drive isolation circuit 2 , a hardware protection circuit 3 , a control module 4 and a PWM output circuit 5 .

[0037] The signal acquisition circuit 1 is used to acquire circuit fault detection signals, and output a fault protection signal when it is determined that a circuit fault occurs according to the fault detection signal. The signal acquisition circuit 1 can be designed according to actual requirements such as the DC or AC information to be acquired, and there is no limitation on this. For example, the signal acquisition circuit 1 can include acquisition circuits such as a voltage sampling circuit, a current sampling circuit, a temperature sampling circuit, an overvoltage protection circuit, an overcurrent protection circuit, and an overtemperature protection circuit, so as to detect overvoltage, overcurrent, overtemperature and other faults in the circuit through multiple paths, and achieve the purpose of comprehensively detecting fault signals in the circuit.

[0038] For example, the signal acquisition circuit 1 can be responsible for real-time detection of the voltage, current and temperature in the circuit through a voltage sampling circuit, a current sampling circuit and a temperature sampling circuit respectively. The voltage, current and other signals output a level signal through the sampling circuit, and the level signal is transmitted to the input end of the overvoltage protection circuit, the overcurrent protection circuit and the overtemperature protection circuit. The overvoltage protection circuit, the overcurrent protection circuit and the overtemperature protection circuit are all composed of a reference source and a comparator. The voltage value of the reference source is the protection value. Under normal operating conditions, the comparator outputs a high-level signal. When the level value of the level signal output by any sampling circuit is higher or lower than the protection value, the comparator outputs a low-level signal. Therefore, when any of overvoltage, overcurrent and overtemperature faults occurs, the signal acquisition circuit 1 changes the normally output high-level signal into a low-level signal. The low-level signal is the fault protection signal. When the fault disappears, the signal output by the signal acquisition circuit 1 will return to the high-level signal in the normal state.

[0039] The first output end of the drive isolation circuit 2 is connected to the IGBT module 9, and is used to drive the IGBT module 9 and output a first fault feedback signal when a fault of the IGBT module 9 is detected. That is, in a normal state, the drive isolation circuit 2 outputs a high-level signal to the IGBT module 9 to drive the IGBT module 9; when the IGBT module 9 fails, the drive isolation circuit 2 will output a low-level signal, i.e., the first fault feedback signal, to the hardware protection circuit 3 and the control module 4, so as to take corresponding protection measures for the IGBT module 9.

[0040] The first input end of the hardware protection circuit 3 is connected to the output end of the signal acquisition circuit 1, and the second input end of the hardware protection circuit 3 is connected to the second output end of the drive isolation circuit 2, and is used to output the first cut-off signal and the fault signal when receiving the fault protection signal or the first fault feedback signal. Specifically, the hardware protection circuit 3 can receive the fault protection signal sent by the signal acquisition circuit 1, and can also receive the first fault feedback signal sent by the drive isolation circuit 2, and flip the received signal to output the first cut-off signal and the fault signal to protect the IGBT module 9. That is, in a normal state, the signal acquisition circuit 1 and the drive isolation circuit 2 will both output a high-level signal to the hardware protection circuit 3, and the hardware protection circuit 3 flips the received high-level signal to output a low-level signal to the PWM output circuit 5; and when the hardware protection circuit 3 receives the low-level signal output by the signal acquisition circuit 1 and / or the drive isolation circuit 2, that is, after receiving the fault protection signal and / or the first fault feedback signal, the hardware protection circuit 3 jumps the normally output low-level signal to a high-level signal, that is, the first cut-off signal and the fault signal are high-level signals.

[0041] The control module 4 is the central controller of the IGBT drive protection control circuit. A suitable main control chip can be selected according to actual needs, such as DSP (Digital Signal Process), ARM (Advanced RISC Machines, microprocessor), etc. as the main control chip, and there is no limitation on this. The control module 4 is the minimum system circuit composed of the main control chip and the crystal oscillator, watchdog, JTAG (Joint Test Action Group, joint test working group) and other peripheral components of the main control chip. Figure 1 As shown, the first input end of the control module 4 is connected to the second output end of the hardware protection circuit 3, and the second input end of the control module 4 is connected to the second output end of the drive isolation circuit 2, and is used to output a second off-wave signal in response to a fault signal or a first fault feedback signal. That is, when the control module 4 receives any one of the fault signal output by the hardware protection circuit 3 or the first fault feedback signal output by the drive isolation circuit 2, the control module 4 will set the off-wave through software, that is, output the second off-wave signal, so as to realize the software off-wave function.

[0042] Or, if Figure 2 As shown, the first input end of the control module 4 is connected to the output end of the signal acquisition circuit 1, and the second input end of the control module 4 is connected to the second output end of the drive isolation circuit 2, for outputting a second off-wave signal in response to a fault protection signal or a first fault feedback signal. That is, when the control module 4 receives any one of the fault protection signal output by the signal acquisition circuit 1 or the first fault feedback signal output by the drive isolation circuit 2, the control module 4 will set the off-wave through software, that is, output the second off-wave signal, to achieve the software off-wave function. It can be understood that when the signal acquisition circuit 1 is directly connected to the control module 4, the signal acquisition circuit 1 has a latching function to maintain the fault protection signal and transmit it to the control module 4.

[0043] That is, under normal conditions, the control module 4 outputs a PWM pulse signal to the PWM output circuit 5 to drive the IGBT module 9; upon receiving fault information transmitted by the signal acquisition circuit 1 or the hardware protection circuit 3 or the drive isolation circuit 2, the control module 4 outputs a second shut-off signal to stop transmitting the PWM pulse signal.

[0044] The first input terminal of the PWM output circuit 5 is connected to the first output terminal of the hardware protection circuit 3, and the second input terminal of the PWM output circuit 5 is connected to the output terminal of the control module 4, and is used to stop outputting the PWM pulse signal in response to at least one of the first off-wave signal and the second off-wave signal. Among them, the PWM output circuit 5 uses a logic chip with an enable pin, such as Figure 3The circuit diagram of the PWM output circuit is shown. Pin 1 of the logic chip U1 is an enable pin, and the output signal of U1 is the same as the input signal. Figure 3 The PDPINTA signal is the signal output by the hardware protection circuit 3. In normal state, the PDPINTA signal is a low-level signal. When a circuit fails, the PDPINTA signal is a high-level signal, i.e., the first shutdown signal. In this state, the logic chip U1 stops outputting, realizing the hardware shutdown function.

[0045] Specifically, when the PWM output circuit 5 receives the first shut-off signal output by the hardware protection circuit 3, regardless of whether the control module 4 outputs the PWM pulse signal, the PWM output circuit 5 will stop outputting the PWM pulse signal, that is, the enable pin of the logic chip U1 can directly stop outputting the PWM pulse signal without passing through the control module 4, thereby realizing a pure hardware shut-off function; when the PWM output circuit 5 receives the second shut-off signal output by the control module 4, the PWM output circuit 5 is controlled to stop outputting the PWM pulse signal through the software setting of the control module 4, thereby realizing a software shut-off function.

[0046] In summary, through the above design of the IGBT drive protection control circuit 10, when the signal acquisition circuit 1 detects a fault in the circuit, the hardware protection circuit 3 can output a first cut-off signal to the PWM output circuit 5, so that the PWM output circuit 5 directly stops outputting the PWM pulse signal, thereby realizing the hardware cut-off function; the hardware protection circuit 3 can also output a fault signal or the information acquisition module 1 directly outputs a fault protection signal to the control module 4, and based on the software setting of the control module 4, a second cut-off signal is sent to the PWM output circuit 5, so that the PWM output circuit 5 stops outputting the PWM pulse signal, thereby realizing the software cut-off function; at the same time, when a circuit fault occurs, the hardware protection circuit 3 directly executes the hardware cut-off function, which can also avoid the problem of being unable to cut off the wave when the software cut-off fails. And, when the drive isolation circuit 2 detects a fault in the IGBT module 9, the hardware protection circuit 3 can receive the first fault feedback signal, and the hardware protection circuit 3 can output the first cut-off signal to the PWM output circuit 5, so that the PWM output circuit 5 directly stops outputting the PWM pulse signal; the control module 4 can also receive the first fault feedback signal, and the control module 4 can output the second cut-off signal to the PWM output circuit 5, so that the PWM output circuit 5 stops outputting the PWM pulse signal. Therefore, through the above method, it is possible to detect faults such as overvoltage, overcurrent, overtemperature, short circuit, etc. through multiple paths, and to realize software and hardware protection functions through multiple paths when a circuit fault occurs. In addition, when a fault in the IGBT module 9 is detected, the driving isolation circuit 2 outputs a first fault feedback signal to the hardware protection circuit 3 and the control module 4 to form a closed-loop control, thereby effectively protecting the IGBT module 9 and further improving the safety and reliability of the circuit.

[0047] According to the IGBT drive protection control circuit 10 of the embodiment of the present invention, the signal acquisition circuit 1 detects whether the circuit is faulty, and when the circuit fails, such as overvoltage, overcurrent, overtemperature, etc., a fault protection signal is sent to the hardware protection circuit 3, and the hardware protection circuit 3 outputs a first off-wave signal to stop the PWM output circuit 5 from outputting the PWM pulse signal, thereby realizing the hardware off-wave function. At the same time, the signal acquisition circuit 1 can directly send a fault protection signal to the control module 4 or the hardware protection circuit 3 outputs a fault signal to the control module 4, and the control module 4 outputs a second off-wave signal to control the PWM output circuit 5 to stop outputting the PWM pulse signal, thereby realizing software protection for the IGBT module 9. In addition, the drive isolation circuit 2 detects whether the IGBT module 9 is faulty, and when it is determined that the IGBT module 9 fails, a first fault feedback signal is sent to the hardware protection circuit 3 and the control module 4 to form a closed-loop control to effectively protect the IGBT module 9. Thus, the multi-path protection function that can be off-wave in both software and hardware is realized in the above manner, thereby improving reliability.

[0048] In some embodiments, Figure 4 As shown, the hardware protection circuit 3 includes a first signal receiving unit 11 , a second signal receiving unit 12 and a latch unit 13 .

[0049] Among them, the input end of the first signal receiving unit 11 is connected to the output end of the signal acquisition circuit 1, and is used to receive the fault protection signal; the input end of the second signal receiving unit 12 is connected to the second output end of the drive isolation circuit 2, and is used to receive the first fault feedback signal; the first input end of the latch unit 13 is connected to the output end of the first signal receiving unit 11 and the output end of the second signal receiving unit 12, the second input end of the latch unit 13 is connected to the second output end of the control module 4, the first output end of the latch unit 13 is connected to the first input end of the PWM output circuit 5, and the second output end of the latch unit 13 is connected to the first input end of the control module 4, and is used to latch the fault protection signal and the first fault feedback signal, and output the first off-wave signal to the PWM output circuit 5 and output the fault signal to the control module 4.

[0050] For example, refer to Figure 4As shown, the first signal receiving unit 11 and the second signal receiving unit 12 form a multi-input OR gate through diodes, and the latch unit 13 is composed of devices U4A and U4B, resistors and capacitors. The output end of the signal acquisition circuit 1 is connected to the cathode of the diode at the input end of the first signal receiving unit 11, and the second output end of the drive isolation circuit 2 is connected to the cathode of the diode at the input end of the second signal receiving unit 12, thereby forming a multi-input OR gate through diodes, and the signals transmitted by the signal acquisition circuit 1 and the drive isolation circuit 2 are flipped and latched through the latch unit 13. When any fault occurs in the circuit, the anode of the diode in the corresponding signal receiving unit jumps to a low-level signal, that is, the input end of the latch unit 13 is a low-level signal, and the latch unit 13 latches the low-level signal, so that the input end of the latch unit 13 remains in a low-level state and no longer changes with the change of the input signal, so that the debugging personnel can understand the fault situation according to the latched signal, and then, the input low-level signal is flipped to a high-level signal through the devices U4A and U4B of the latch unit 13, that is, the output end of the latch unit 13 outputs a high-level signal. Furthermore, after receiving the high level signal output by the latch unit 13 , the PWM output circuit 5 performs hardware shutdown, and after receiving the high level signal output by the latch unit 13 , the control module 4 performs software shutdown.

[0051] by Figure 4 For example, specifically, after the signal acquisition circuit 1 detects a circuit fault, the signal acquisition circuit 1 outputs a fault protection signal to the first signal receiving unit 11. Figure 4 The FAULT-U signal and the FAULT-I signal are signals transmitted by the signal acquisition circuit 1. The FAULT-U signal and the FAULT-I signal are high-level signals in a normal state, and jump to low-level signals in the event of a fault, that is, the first signal receiving unit 11 receives a fault protection signal, and the first signal receiving unit 11 sends a low-level signal to the latch unit 13 for latching, that is, the latch unit 13 caches the fault protection signal, so that the first input end of the latch unit 13 maintains a fault state, and then, after the fault protection signal is flipped by the latch unit, it is flipped from a low-level signal to a high-level signal, so as to output a high-level signal, that is, the first off-wave signal and the fault signal to the PWM output circuit 5 and the control module 4 respectively.

[0052] And, after the drive isolation circuit 2 detects a fault in the IGBT module 9, the drive isolation circuit 2 outputs a first fault feedback signal to the second signal receiving unit 12, Figure 4The FAULT signal is a signal transmitted by the driving isolation circuit 2. The FAULT signal is a high-level signal in a normal state, and jumps to a low-level signal in the event of a fault, that is, the second signal receiving unit 12 receives the first fault feedback signal, and the second signal receiving unit 12 transmits the low-level signal to the latch unit 13 for latching, that is, the latch unit 13 caches the first fault feedback signal, so that the second input end of the latch unit 13 maintains a fault state, and then, after the first fault feedback signal is flipped by the latch unit, it is flipped from a low-level signal to a high-level signal, so as to output a high-level signal, that is, the first off-wave signal and the fault signal to the PWM output circuit 5 and the control module 4 respectively.

[0053] Figure 4 The PDPINTA signal is a signal outputted from the first output terminal of the latch unit 13, which is a low-level signal in a normal state. When a circuit fault occurs, i.e., the input terminal of the latch unit 13 receives a fault protection signal or a first fault feedback signal, the signal jumps to a high-level signal, i.e., the first off-wave signal is a high-level signal. Thus, the latch unit 13 outputs the first off-wave signal to the PWM output circuit 5 through the first output terminal of the latch unit 13 according to the received fault protection signal or the first fault feedback signal, so as to stop the PWM output circuit 5 from outputting the PWM pulse signal in the hardware circuit; at the same time, Figure 4 The PDPINTA_DSP signal is a signal output from the second output terminal of the latch unit 13. It is a low-level signal under normal conditions and jumps to a high-level signal when a fault occurs, that is, the fault signal is a high-level signal. Therefore, the fault signal is output to the control module 4 through the second output terminal of the latch unit 13, so that the PWM output circuit 5 stops outputting the PWM pulse signal in the software setting.

[0054] In some embodiments, the control module 4 is further used to output a clear fault signal when the circuit returns to normal; the latch unit 13 is further used to clear the fault protection signal and the first fault feedback signal in response to the clear fault signal.

[0055] Specifically, when a circuit fails, the latch unit 13 latches the received low-level signal such as a fault protection signal or a first fault feedback signal. The first off-wave signal and the fault signal output by the latch unit 13 are continuous high-level signals. When the signal output by the signal acquisition circuit 1 is restored to a high-level signal, the signal output by the latch unit 13 is still a continuous high-level signal, that is, the PWM output circuit 5 and the control module 4 still believe that the circuit is in a fault state and cannot operate normally. Therefore, after the circuit returns to normal, a clear fault signal is sent to the latch unit 13 through the control module 4. When the second input end of the latch unit 13 receives the clear fault signal sent by the control module 4, that is, when the DSP_REST signal is a low-level signal, the latch unit 13 is reset, thereby avoiding the problem that the hardware protection circuit 3 is always latched in a fault state.

[0056] In some embodiments, Figure 5 As shown, the hardware protection circuit 3 further includes a crash detection unit 16 .

[0057] Among them, the input end of the crash detection unit 16 is connected to the third output end of the control module 4, and the output end of the crash detection unit 16 is connected to the first input end of the latch unit 13, which is used to detect the operating status of the control module 4 and output a control abnormality signal when the operating status is abnormal; the latch unit 13 is also used to output a first off-wave signal according to the control abnormality signal.

[0058] For example, refer to Figure 5 As shown, the crash detection unit 16 is a crash detection circuit composed of transistors Q7, Q8, resistors, capacitors, diodes and other devices. After the circuit is powered on, when the control module 4 operates normally, the DSP_RUN2 signal, such as a square wave signal, is an operation signal sent by the control module 4. The operation signal becomes a continuous high-level signal after passing through the capacitor C39. The high-level signal drives the transistor Q8 to turn on, and after the transistor Q8 is turned on, the base of the transistor Q7 becomes a low-level signal, so the transistor Q7 is not turned on. At this time, the collector of the transistor Q7, that is, the output end of the crash detection unit 16, is a high-level signal. The high-level signal is transmitted to the first input end of the latch unit 13, and the output end of the latch unit 13 outputs a low-level signal, thereby driving the IGBT module 9 to operate normally. When the control module 4 is in an abnormal operation state, such as a crash, the control module 4 has no signal output, that is, the DSP_RUN2 signal is a low-level signal after passing through the capacitor C39, so the transistor Q8 is not turned on, and the base of the transistor Q7 is a high-level signal, and the transistor Q7 is turned on. At this time, the collector of the transistor Q7 is a low-level signal, that is, the control abnormality signal is a low-level signal, and the low-level signal is transmitted to the first input end of the latch unit 13, and the output end of the latch unit 13 outputs a high-level signal, so that the latch unit 13 outputs a first off-wave signal according to the control abnormality signal, so as to stop the PWM output circuit 5 from outputting the PWM pulse signal in the hardware circuit. Therefore, the crash detection unit 16 monitors whether the control module 4 is operating normally in real time, so that when the control module 4 is in an abnormal operation state, the PWM output circuit 5 can be controlled to turn off the wave in time, effectively protecting the IGBT module 9.

[0059] In summary, through the above design of the IGBT drive protection control circuit 10, in the embodiment of the present invention, the fault signals such as the abnormal operating state signal of the control module 4, overvoltage, overcurrent, overtemperature and the abnormal operating state signal of the IGBT module 9 are combined to form a multi-input OR gate. When any fault occurs in the circuit, the latch unit 13 will output a high-level signal, that is, output the first off-wave signal and the fault signal to the PWM output circuit 5 and the control module 4 respectively, so as to control the PWM output circuit 5 to turn off the wave, thereby effectively protecting the IGBT module 9.

[0060] In some embodiments, Figure 4 As shown, the hardware protection circuit 3 further includes a prompt unit 17 .

[0061] Among them, the first end of the prompt unit 17 is connected to the first output end of the latch unit 13 and the second output end of the latch unit 13, the second end of the prompt unit 17 is connected to the first input end of the PWM output circuit 5 and the first input end of the control module 4, and the third end of the prompt unit 17 is grounded, which is used to respond to the fault protection signal or the first fault feedback signal for fault prompt.

[0062] For example, refer to Figure 4 As shown, the prompt unit 17 is composed of a light emitting diode D16, a resistor R56 and a capacitor C42, and is used to prompt that a circuit fault occurs. Specifically, when any fault occurs in the circuit, the output end of the latch unit 13 outputs a high level signal, and the light emitting diode D16 of the prompt unit 17 emits light, thereby playing the role of a fault prompt.

[0063] In some embodiments, for different IGBT module topologies, the drive isolation circuit 2 of the embodiment of the present invention includes N drive isolation units 14 connected to the IGBT module 9, each drive isolation unit 14 includes an upper bridge arm drive subunit 24 and a lower bridge arm drive subunit 25, for example Figure 6 As shown. And, as Figure 1 As shown in FIG. 2, the IGBT drive protection control circuit 10 further includes N interlocking circuits 6, the first input ends of the N interlocking circuits 6 are connected to the output end of the PWM output circuit 5, the second input ends of the N interlocking circuits 6 are correspondingly connected to the output ends of the N drive isolation units 14, and the output ends of the N interlocking circuits 6 are correspondingly connected to the input ends of the N drive isolation units 14, for interlocking the upper bridge arm drive subunit 24 and the lower bridge arm drive subunit 25 in each drive isolation unit 14. Therefore, the embodiment of the present invention can design a corresponding IGBT drive protection control circuit 10 according to the topology type of the IGBT module 9, thereby improving the applicability of the IGBT drive protection control circuit 10.

[0064] In some embodiments, N=1, that is, the drive isolation circuit 2 includes a drive isolation unit 14, such as Figure 6 As shown, the upper bridge arm driving subunit 24 of the driving isolation unit 14 is connected to the IGBT module 9 through the PWM1_A1 terminal to send a PWM driving signal, and the lower bridge arm driving subunit 25 of the driving isolation unit 14 is connected to the IGBT module 9 through the PWM3_A3 terminal to send a PWM driving signal. And, in order to be applicable to an IGBT topology structure in which the upper and lower bridge arms cannot be turned on at the same time, such as a full-bridge topology, a T-type three-level topology, an I-type three-level topology, a single-phase half-bridge inverter topology, and other topologies, an interlocking circuit 6 is correspondingly provided in the embodiment of the present invention, and the first input terminal of the interlocking circuit 6 is connected to the output terminal of the PWM output circuit 5, and the second input terminal of the interlocking circuit 6 is connected to the output terminal of the driving isolation unit 14, that is, Figure 6 The FAULT1 and FAULT3 terminals in the interlock circuit 6 are connected, and the output terminal of the interlock circuit 6 is connected to the input terminal of the drive isolation unit 14. Figure 6 The PWM1_A terminal and the PWM1_B terminal are connected to interlock the upper bridge arm driving subunit 24 and the lower bridge arm driving subunit 25, that is, the interlocking circuit 6 is used to control the lower bridge arm driving subunit 25 circuit to be turned off when the upper bridge arm driving subunit 24 circuit is turned on, or to control the upper bridge arm driving subunit 24 circuit to be turned off when the lower bridge arm driving subunit 25 circuit is turned on. Therefore, when a failure occurs in the control module 4 and causes the bridge arm to be directly connected, the interlocking circuit 6 can effectively avoid the problem of bridge arm directly connected due to control program errors, prevent machine explosion, and improve reliability.

[0065] For example, refer to Figure 3 and Figure 7 As shown, the first input end of the interlocking circuit 6 is a set of complementary PWM square wave signals output by the PWM output circuit 5, that is, when the PWM1_1 signal is high level, PWM3_1 is low level, or when the PWM1_1 signal is low level, PWM3_1 is high level. After the PWM square wave signal passes through the interlocking circuit 6, it is transmitted to the upper bridge arm driving subunit 24 and the lower bridge arm driving subunit 25 through PWM1_A and PWM1_B respectively. In addition, the embodiment of the present invention is also provided with a level of NAND gate at the rear end of the interlocking circuit 6, that is, devices U3A and U3B, thereby ensuring that the waveform input to the interlocking circuit 6 is consistent with the waveform output. Specifically, when the input ends of the interlocking circuit 6 are high level signals at the same time, the outputs of the interlocking circuit 6 are all low level signals; when the input ends of the interlocking circuit 6 are low level signals at the same time, the outputs of the interlocking circuit 6 are all low level signals, thereby avoiding the situation where the upper and lower bridge arms of the rear end IGBT module 9 are opened at the same time due to the simultaneous output of high level signals, thereby preventing the machine from exploding.

[0066] Furthermore, the FAULT1 signal and the FAULT3 signal are signals fed back by the drive isolation unit 14. When the circuit is operating normally, the FAULT1 signal and the FAULT3 signal are both high-level signals, and they jump to low-level signals when a fault occurs. The FAULT1 signal and the FAULT3 signal are output to the cathode of the diode in the interlock circuit 6 to form a multi-input OR gate. When any signal is a low-level signal, that is, when the first fault feedback signal is received, the output of the interlock circuit 6 is a low-level signal, that is, the interlock circuit 6 directly stops outputting the PWM pulse signal, effectively protecting the IGBT module 9. Furthermore, when any signal of the FAULT1 signal and the FAULT3 signal is a low-level signal, the diode D6 emits light to indicate that a circuit fault has occurred.

[0067] In addition, the FAULT1 signal and the FAULT3 signal can also be transmitted to the control module 4 through the FAULT signal of the OR gate output terminal formed by the cathode of the diode in the interlock circuit 6, or the FAULT1 signal and the FAULT3 signal can also be transmitted to the control module 4 separately, so that the control module 4 can perform protection operations in time when a circuit fails, thereby improving reliability.

[0068] In addition, under normal conditions, since the power supply of the control module 4 is different from the power supply of the interlocking circuit 6, the PWM pulse signal output by the control module 4 cannot be directly transmitted to the interlocking circuit 6. Therefore, by using a logic chip with an enable pin through the PWM output circuit 5, the PWM pulse signal output by the control module 4 can be converted into a PWM pulse signal received by the interlocking circuit 6 to ensure the effective operation of the circuit.

[0069] In some other embodiments, N=2, that is, the drive isolation circuit 2 includes two drive isolation units 14, and the IGBT drive protection control circuit 10 is correspondingly provided with two interlock circuits 6. Specifically, the first output end of each drive isolation unit 14 is connected to the IGBT module 9, and the second output end of each drive isolation unit 14 is connected to the second input end of the control module 4; the first input end of each interlock circuit 6 is connected to the output end of the PWM output circuit 5, for example, the first input end of one of the interlock circuits 6 is connected Figure 3 The PWM1_1 terminal and the PWM3_1 terminal in the PWM output circuit 5 shown in the figure, the second input terminal of the interlock circuit 6 is connected to the second output terminal of the corresponding drive isolation unit 14, and the output terminal of the interlock circuit 6 is connected to the input terminal of the corresponding drive isolation unit 14; the first input terminal of another interlock circuit 6 is connected Figure 3 The PWM2_1 terminal and the PWM4_1 terminal in the PWM output circuit 5 are shown, and the second input terminal of the interlock circuit 6 is connected to the second output terminal of the corresponding drive isolation unit 14 , and the output terminal of the interlock circuit 6 is connected to the input terminal of the corresponding drive isolation unit 14 .

[0070] It should be noted that the specific structures and principles of each set of drive isolation units 14 and interlocking circuits 6 provided in the embodiment of the present invention are respectively the same as those provided in the above embodiment of the present invention. Figure 6 and Figure 7 The specific structure and principle shown are the same. Please refer to the description of this part for details. In order to reduce redundancy, they will not be repeated here.

[0071] It is understandable that, without departing from the concept of the present invention, the IGBT drive protection control circuit 10 of the embodiment of the present invention can be adaptively deformed and improved according to the topological structure of the IGBT module 9, and there is no limitation to this.

[0072] In some embodiments, Figure 6 As shown, the driving isolation unit 14 further includes an IGBT driving chip 18 and an IGBT desaturation detection unit 19 .

[0073] Among them, the IGBT driving chip 18 includes an internal current source and a comparator; the first end of the IGBT desaturation detection unit 19 is connected to the IGBT module 9, the second end of the IGBT desaturation detection unit 19 is connected to the internal current source, and the third end of the IGBT desaturation detection unit 19 is connected to the input end of the comparator, which is used to detect the short-circuit signal of the IGBT module 9.

[0074] Specifically, when the short-circuit signal detected by the IGBT desaturation detection unit 19 exceeds the reversal threshold of the comparator, the IGBT driver chip 18 stops outputting the IGBT drive signal, and, because in this case, the IGBT driver chip 18 will quickly perform the off-wave function, but because the circuit front end does not know that the circuit back end has a fault, the circuit front end is still in a normal output state, therefore, the IGBT driver chip 18 will simultaneously send a first fault feedback signal to the interlock circuit 6, the hardware protection circuit 3 and the control module 4, thereby, the interlock circuit 6 stops outputting the PWM pulse signal when receiving the first fault feedback signal, and the hardware protection circuit performs the hardware off-wave function when receiving the first fault feedback signal, and the control module 4 performs the software off-wave function when receiving the first fault feedback signal. In addition, since the IGBT driver chip 18 stops outputting the IGBT drive signal only in the case of a fault, and continues to output the IGBT drive signal when the fault disappears, by sending the first fault feedback signal to the interlock circuit 6 and the hardware protection circuit 3, it can also ensure that the circuit front end is still in the off-wave state when the fault disappears, so that the debugging personnel can understand the fault situation.

[0075] For example, refer to Figure 6As shown, the drive isolation unit 14 adopts an isolated IGBT drive chip 18 such as U2 and U5, and has a short-circuit overcurrent protection function. The IGBT drive chip 18 integrates an internal current source and a comparator. When the IGBT module 9 is normally turned on and off, the IGBT desaturation detection unit 19 does not work; when the IGBT module 9 is short-circuited, the Vce voltage of the IGBT module 9 will quickly rise to the bus voltage. In this case, the short-circuit signal detected by the IGBT desaturation detection unit 19 will rise until the short-circuit signal reaches the threshold of the comparator, triggering the comparator to reverse, so that the IGBT drive chip 18 stops outputting the IGBT drive signal, such as shutting off the output of the IGBT drive square wave, effectively protecting the IGBT module 9.

[0076] Based on the above operation, the IGBT driver chip 18 simultaneously outputs the first fault feedback signal to the hardware protection circuit 3 and the control module 4 to achieve the purpose of closed-loop protection. In addition, the driver isolation unit 14 receives the clear driver chip fault signal output by the control module 4, that is, Figure 6 As shown in the RST signal, specifically, when the FAULT1 signal or the FAULT3 signal outputs a low level, it indicates that a short circuit occurs in the IGBT module 9. When the circuit resumes normal operation, the control module 4 needs to output the RST signal as a high level, and then the drive isolation unit 14 will clear the drive chip fault, and the drive isolation unit 14 will reset and operate normally.

[0077] In some embodiments, Figure 6 As shown, the IGBT desaturation detection unit 19 includes a capacitor subunit 21 , a resistor subunit 22 and a diode subunit 23 .

[0078] Among them, the first end of the capacitor subunit 21 is connected to the internal current source, the second end of the capacitor subunit 21 is connected to the input end of the comparator, and the third end of the capacitor subunit 21 is grounded; the first end of the resistor subunit 22 is connected to the second end of the capacitor subunit 21; the anode end of the diode subunit 23 is connected to the second end of the resistor subunit 22, and the cathode end of the diode subunit 23 is connected to the IGBT module 9.

[0079] For example, refer to Figure 6As shown, the IGBT desaturation detection unit 19 is an IGBT desaturation detection protection circuit composed of a resistor subunit 22, i.e., a resistor R13a, a diode subunit 23, i.e., a diode D2a, and a capacitor subunit 21, i.e., capacitors C45, C5, and C7. Among them, capacitors C5 and C7 can play a filtering role. When a short circuit overcurrent occurs in the IGBT module 9, the Vce voltage of the IGBT module 9 will quickly rise to the bus voltage. In this case, the diode D2a is cut off, and the internal current source charges the capacitor C45. The voltage across the capacitor C45, i.e., the short circuit signal, rises to the comparator reversal threshold, triggering the comparator to reverse, so that the IGBT driver chip 18 turns off the output of the IGBT drive square wave, thereby achieving the purpose of protecting the IGBT module 9.

[0080] Please refer to the following Figure 1-8 The working process of the IGBT driving protection control circuit according to the embodiment of the present invention is illustrated by way of example, and the specific steps are as follows.

[0081] Step S1, determining whether a circuit failure occurs.

[0082] Step S2: The circuit operates normally, and the signal acquisition circuit outputs a high-level signal to the hardware protection circuit.

[0083] Step S3: After the high-level signal is flipped and latched by the hardware protection circuit, it is output as a low-level signal.

[0084] Step S4: After receiving the low level signal, the control module normally outputs the PWM pulse signal to the PWM output circuit.

[0085] Step S5, after receiving the low level signal, the PWM output circuit converts the PWM pulse signal output by the control module into a PWM pulse signal that can be received by the interlocking circuit.

[0086] Step S6: the interlocking circuit transmits the PWM pulse signal to the drive isolation circuit.

[0087] Step S7, the drive isolation circuit transmits the PWM pulse signal to the IGBT module to drive the IGBT module. At the same time, the drive isolation circuit determines that the IGBT module is not faulty, and the drive isolation circuit outputs a high level signal to the interlock circuit, the control module and the hardware protection circuit.

[0088] Step S8: The IGBT module operates normally.

[0089] Step S9, after the signal acquisition circuit detects the circuit fault acquisition signal, it outputs a low level signal, namely a fault protection signal, to the hardware protection circuit.

[0090] Step S10, after the low level signal is flipped and latched by the hardware protection circuit, a high level signal is output, that is, the first off-wave signal is a high level signal and sent to the PWM output circuit; the fault signal is a high level signal and sent to the control module.

[0091] In step S11 , the control module outputs a second OFF signal to the PWM output circuit according to the fault signal.

[0092] In step S12, the PWM output circuit stops outputting the PWM pulse signal according to the first off-wave signal or the second off-wave signal.

[0093] Step S13, after the driving isolation circuit detects that the IGBT module has a fault, it simultaneously outputs a low level signal, namely, a first fault feedback signal, to the hardware protection circuit and the interlocking circuit.

[0094] Step S14, the interlocking circuit turns off the wave, that is, the output of the PWM pulse signal can be directly stopped.

[0095] Therefore, through the above steps, closed-loop detection control from the front end to the back end and closed-loop detection control from the back end to the front end can be realized, so as to achieve the purpose of fully protecting the IGBT module 9.

[0096] In summary, the embodiment of the present invention detects overvoltage, overcurrent, overtemperature and other faults through multi-path detection by the information acquisition circuit 1, and transmits the fault information to the hardware protection circuit 3 and the control module 4, and the PWM output circuit 5 selects a logic chip with an enable pin, which can realize a pure hardware shutdown function in the event of a fault, and the interlock circuit 6 can avoid the fault of the bridge arms being opened at the same time, and the drive isolation circuit 2 adopts an IGBT drive isolation chip with its own short-circuit overcurrent protection function, and can feedback the fault information to the interlock circuit 6, the hardware protection circuit 3 and the control module 4 to form a closed-loop protection. The IGBT drive protection control circuit 10 is designed in this way to realize the multi-path IGBT fault detection function, as well as the multi-path protection function that can shut down the software and hardware, greatly improving the safety and effectiveness of the circuit.

[0097] A second aspect of the present invention provides a device 20, such as Fig. 9 As shown, the device 20 includes an IGBT module 9 and the IGBT drive protection control circuit 10 provided in the above embodiment.

[0098] The IGBT drive protection control circuit 10 is connected to the IGBT module 9 .

[0099] It should be noted that during the operation of the device 20 of the embodiment of the present invention, its specific implementation method is similar to the specific implementation method of the IGBT drive protection control circuit 10 of any of the above-mentioned embodiments of the present invention. For details, please refer to the description of the IGBT drive protection control circuit 10. In order to reduce redundancy, it will not be repeated here.

[0100] According to the device 20 of the embodiment of the present invention, by adopting the IGBT drive protection control circuit 10 provided in the above embodiment, the IGBT module 9 can be effectively protected, thereby improving the reliability of the device 20.

[0101] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0102] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An IGBT drive protection control circuit, characterized in that: include: A signal acquisition circuit, used for acquiring a circuit fault detection signal, and outputting a fault protection signal when it is determined that the circuit fails according to the fault detection signal; A driving isolation circuit, wherein a first output terminal of the driving isolation circuit is connected to the IGBT module, and is used to drive the IGBT module and output a first fault feedback signal when a fault of the IGBT module is detected; A hardware protection circuit, wherein a first input end of the hardware protection circuit is connected to an output end of the signal acquisition circuit, and a second input end of the hardware protection circuit is connected to a second output end of the drive isolation circuit, and is used to output a first off-wave signal and a fault signal when receiving the fault protection signal or the first fault feedback signal; A control module, wherein the first input end of the control module is connected to the second output end of the hardware protection circuit, and the second input end of the control module is connected to the second output end of the drive isolation circuit, and is used to output a second OFF wave signal in response to the fault signal or the first fault feedback signal; or, the first input end of the control module is connected to the output end of the signal acquisition circuit, and the second input end of the control module is connected to the second output end of the drive isolation circuit, and is used to output the second OFF wave signal in response to the fault protection signal or the first fault feedback signal; a PWM output circuit, wherein a first input terminal of the PWM output circuit is connected to a first output terminal of the hardware protection circuit, and a second input terminal of the PWM output circuit is connected to a first output terminal of the control module, and is used for stopping outputting a PWM pulse signal in response to at least one of the first off-wave signal and the second off-wave signal; The drive isolation circuit comprises N drive isolation units connected to the IGBT module, each of the drive isolation units comprising an upper bridge arm drive sub-unit and a lower bridge arm drive sub-unit; The IGBT drive protection control circuit also includes N interlocking circuits, the first input ends of the N interlocking circuits are connected to the output end of the PWM output circuit, the second input ends of the N interlocking circuits are correspondingly connected to the output ends of the N drive isolation units, and the output ends of the N interlocking circuits are correspondingly connected to the input ends of the N drive isolation units, for interlocking the upper bridge arm drive sub-unit and the lower bridge arm drive sub-unit in each of the drive isolation units.

2. The IGBT drive protection control circuit according to claim 1, characterized in that: The hardware protection circuit comprises: A first signal receiving unit, wherein an input end of the first signal receiving unit is connected to an output end of the signal acquisition circuit and is used to receive the fault protection signal; a second signal receiving unit, wherein an input end of the second signal receiving unit is connected to a second output end of the drive isolation circuit, and is used to receive the first fault feedback signal; A latch unit, wherein a first input end of the latch unit is connected to an output end of the first signal receiving unit and an output end of the second signal receiving unit, a second input end of the latch unit is connected to a second output end of the control module, a first output end of the latch unit is connected to a first input end of the PWM output circuit, and a second output end of the latch unit is connected to a first input end of the control module, for latching the fault protection signal and the first fault feedback signal and outputting the first off-wave signal to the PWM output circuit and outputting the fault signal to the control module.

3. The IGBT drive protection control circuit according to claim 2, characterized in that: The control module is further configured to output a fault clearing signal when the circuit returns to normal; The latch unit is further configured to clear the fault protection signal and the first fault feedback signal in response to the fault clearing signal.

4. The IGBT drive protection control circuit according to claim 2, characterized in that: The hardware protection circuit also includes: A crash detection unit, wherein the input end of the crash detection unit is connected to the third output end of the control module, and the output end of the crash detection unit is connected to the first input end of the latch unit, and is used to detect the operating state of the control module and output a control abnormality signal when the operating state is abnormal; The latch unit is further configured to output the first off-wave signal according to the abnormal control signal.

5. The IGBT drive protection control circuit according to claim 3, characterized in that: The hardware protection circuit also includes: A prompt unit, wherein a first end of the prompt unit is connected to the first output end of the latch unit and the second output end of the latch unit, a second end of the prompt unit is connected to the first input end of the PWM output circuit and the first input end of the control module, and a third end of the prompt unit is grounded, for providing a fault prompt in response to the fault protection signal or the first fault feedback signal.

6. The IGBT drive protection control circuit according to claim 1, characterized in that: The drive isolation unit further includes: An IGBT driver chip, wherein the IGBT driver chip includes an internal current source and a comparator; An IGBT desaturation detection unit, wherein a first end of the IGBT desaturation detection unit is connected to the IGBT module, a second end of the IGBT desaturation detection unit is connected to the internal current source, and a third end of the IGBT desaturation detection unit is connected to the input end of the comparator, for detecting a short-circuit signal of the IGBT module; When the short-circuit signal exceeds the reversal threshold of the comparator, the IGBT driver chip stops outputting the IGBT driver signal and sends the first fault feedback signal to the interlock circuit, the hardware protection circuit and the control module; The interlock circuit is further configured to stop outputting the PWM pulse signal when receiving the first fault feedback signal.

7. The IGBT drive protection control circuit according to claim 6, characterized in that: The IGBT desaturation detection unit comprises: A capacitor unit, wherein a first end of the capacitor unit is connected to the internal current source, a second end of the capacitor unit is connected to the input end of the comparator, and a third end of the capacitor unit is grounded; a resistor subunit, wherein a first end of the resistor subunit is connected to a second end of the capacitor subunit; A diode subunit, wherein an anode terminal of the diode subunit is connected to the second end of the resistor subunit, and a cathode terminal of the diode subunit is connected to the IGBT module.

8. The IGBT drive protection control circuit according to claim 1, characterized in that: N=1 or N=2.

9. A device, characterized in that: include: IGBT modules; The IGBT drive protection control circuit according to any one of claims 1 to 8, wherein the IGBT drive protection control circuit is connected to the IGBT module.

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