Early error detection and automatic correction technology for memory components to improve reliability

Abstract

Embodiments of the present application relate to early error detection and automatic correction techniques for storage elements to improve reliability. A semiconductor chip with error detection and correction includes a plurality of pipelines and each pipeline is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipeline to generate a number of events consisting of read-type events and / or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can collectively detect and correct erroneous memory entries across the plurality of storage elements.

Description

Technical Field

[0001] The present description relates generally to semiconductor systems, and in particular to early error detection and auto-correction techniques for memory elements to achieve improved reliability in semiconductor systems. Background Art

[0002] In semiconductors, there are two main types of errors in storage elements, hard errors and soft errors. Hard errors are problems caused by permanent physical defects. Soft errors are problems that cause temporary conditions to change the stored data in an unexpected way. Soft errors are caused by events rather than persistent physical conditions. Soft errors can occur in transmission lines, digital logic, analog circuits, magnetic storage devices, and elsewhere, but are most common in semiconductor storage devices because the erroneous data is persistent and causes other unexpected results over a much longer period of time. The soft error rate (SER) is the rate at which a device encounters soft errors. It is usually expressed as the number of failures per unit time (FIT) or the mean time between failures (MTBF). FIT is a unit used to quantify failures per unit time and is equivalent to one error per billion hours of device operation. MTBF is usually specified in years of device operation.

[0003] Soft errors can be caused by ionizing radiation such as alpha particles, cosmic rays, and thermal neutrons. Alpha particles can be caused by the decay of traces of radioactive materials in packaging, and cosmic rays on the earth's surface consist of a shower of high-energy secondary particles such as fast neutrons, protons, and muons, which are formed from primary cosmic particles. Thermal neutrons are caused by fast neutrons losing their energy and reaching thermal equilibrium with their surroundings, and can form charged particles such as alpha particles, gamma rays, and lithium nuclei, which can cause soft errors in semiconductor memory devices. Soft errors can also be caused by random noise or signal integrity problems such as inductive or capacitive crosstalk.

[0004] Traditionally, if detected, soft errors can be corrected by rewriting the correct data to replace the erroneous data. Systems can use error correction to correct soft errors on the fly using error correction codes (ECC). However, in many systems, it may be impossible to determine the correct data or even find that there is an error. In addition, before detection or correction can occur, the system may have crashed, in which case the recovery process must include a restart. Some characteristics of reliable systems may include fault tolerance (FT), high availability (HA), and disaster recovery (DR). FT is about making individual components of the system resilient to failures, and for system components that are considered fault-tolerant, any downtime is unacceptable. HA involves making the entire system as a whole resilient to failures. For systems that are considered highly available, only a very small amount of downtime (e.g., 0.05% (i.e., 99.95% uptime)) is acceptable. DR is about recovering a system that has been shut down (whether or not it is considered HA), thereby ensuring that the HA uptime target is met.

[0005] Macro storage elements (hereinafter, macros) are implemented in hardware, some details of which are described herein. Macros are examples of pre-designed storage elements (e.g., configuration memories that logic designers can use in chip designs). Macros are designed at the transistor level and are therefore quite efficient in terms of chip area and power consumption. As an implementation in macros, column multiplexing (C-Muxing) is used to ensure that adjacent bits in a logical entry are scattered across different (e.g., two) physical entries. This in turn ensures that the extent of multi-bit flips is limited to a small number, ideally only one. For example, for a logical entry with a single ECC across n bits, a physical macro with CMUX=1 enables the even bits of the logical entry to be stored in physical location 0 and the odd bits of the logical entry to be stored in physical location 1. This allows detection and correction of 2-bit flips, and detection but not correction of 3-bit to 5-bit flips.

[0006] In a static random access memory (SRAM) or static register file (SRF) macro, when the macro is read, its data content with corresponding ECC is accessed and error checked. SRF macros usually have built-in column multiplexing. Therefore, if a soft error flips multiple bits (e.g., 2 bits), the flipped bits are not part of the same logical entry. Therefore, a single ECC field across the logical entries will correct single-bit errors in two logical entries. In other words, a bit flip in a logical entry only affects that specific logical entry.

[0007] However, with Ternary Content Addressable Memory (TCAM), the compare command does not read the contents of the macro and only outputs the match and the index where the match occurred. Therefore, during the compare, the entry contents are not available. Error detection does not occur until the TCAM location is explicitly read and an error check is performed. This makes the detection interval much longer. For TCAM macros, there is no built-in column multiplexing support. As such, when there is a bit flip in the TCAM, it not only affects the one or several locations, but also the entire priority decoding, rendering the entire macro instance unusable until the error is corrected. Since TCAM is used for critical packet processing and forwarding functions, undetected errors may drop or (even worse) mis-forward a large amount of traffic that may paralyze the entire network.

[0008] In summary, TCAM has a much higher probability of a significantly larger number of bit flips. The system will witness packets being lost or (even worse) mis-forwarded until the error is detected and then corrected, which typically takes tens of milliseconds even after detection, which itself may not occur until all TCAM entries have been explicitly scanned. This can be a major problem with TCAM in the networking industry today. Summary of the invention

[0009] An embodiment of the present application provides a system including error detection and correction, the system comprising: a plurality of pipelines, each pipeline coupled to one or more ports on a semiconductor chip; and a state machine coupled to the plurality of pipelines and configured to generate a plurality of events, wherein: the plurality of events include one of a read-type event or a scan-type event associated with a plurality of storage elements, and the state machine is implemented in hardware and configured to detect and correct errors including erroneous memory entries across the plurality of storage elements.

[0010] Another embodiment of the present application provides an error detection and correction method, the method comprising: coupling a state machine to multiple pipelines; and configuring the state machine to perform the following operations: accessing the configuration memory of the multiple pipelines to generate multiple events; and implementing a LEAN scheme to reduce at least two of the critical packet path latency, chip area, and chip power consumption, wherein: the multiple events include one of a read-type event or a scan-type event associated with the configuration memory.

[0011] Another embodiment of the present application provides an error detection and correction method, the method comprising: coupling a state machine to multiple pipelines; and configuring the state machine to perform the following operations: accessing the configuration memory of the multiple pipelines to generate multiple events; and implementing a CAD scheme to reduce at least two of critical packet path latency, chip area, and chip power consumption, wherein: the multiple events include one of a read-type event or a scan-type event. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Certain features of the inventive technology are set forth in the appended claims.For purposes of illustration, however, several embodiments of the inventive technology are set forth in the following figures.

[0013] Figure 1 is a block diagram illustrating an example of a macro instantiation architecture based on a latency efficient auto-correction (LEAN) scheme according to various aspects of the present technology.

[0014] Figure 2 It is a diagram illustrating various aspects of the technology according to the present invention. Figure 1 A timing diagram of an example of the flow of events in the LEAN solution.

[0015] Figure 3 is a table illustrating an example of bit flipping in a ternary content addressable memory (TCAM).

[0016] Figure 4 is a block diagram illustrating an example of a typical comparison and detection (CAD) architecture in accordance with aspects of the present techniques.

[0017] Figure 5 The diagram shows Figure 4 Table of examples of the probability of errors in two CAD macros.

[0018] Figure 6 is a block diagram illustrating an example of a CAD plus correction architecture in accordance with aspects of the present technology.

[0019] Fig. 7A is a diagram illustrating an example of column multiplexing outside of a macro utilizing multiple error correction code (ECC) fields in accordance with aspects of the present techniques. Figure 7B is a diagram illustrating an example of interleaving of ECC bits while stored in a macro in accordance with aspects of the present techniques.

[0020] Figure 7C is a diagram illustrating an example of column multiplexing outside of a macro utilizing multiple ECC fields and a corresponding table in accordance with aspects of the present techniques.

[0021] Figure 8 is a table illustrating examples of required ECC bits and redundant parity bits for different numbers of data bits.

[0022] Fig. 9 is a diagram illustrating an example of a centralized state machine for reading pipeline entries.

[0023] Fig.10is a flow chart illustrating an example of an error detection and correction method according to some aspects of the present technology.

[0024] Fig.11 is a flow chart illustrating an example of an error detection and correction method according to some aspects of the present technology.

[0025] Fig.12 The present invention is an electronic system in which some aspects of the present technology are implemented. DETAILED DESCRIPTION

[0026] The detailed description set forth below is intended to be an illustration of various configurations of the present invention technology and is not intended to represent the only configurations in which the present invention technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description, which includes specific details for providing a thorough understanding of the present invention technology. However, the present invention technology is not limited to the specific details set forth herein and can be practiced without one or more of the specific details. In some examples, structures and components are shown in block diagram form to avoid obscuring the concepts of the present invention technology.

[0027] The present technology is directed to methods and systems for early error detection and automatic correction techniques for memory elements to achieve improved reliability in semiconductor systems. The disclosed technology is based on a latency efficient automatic correction (LEAN) scheme that focuses on reliability aspects in general and early error detection of all configuration memories such as static random access memory (SRAM) or static register file (SRF) and TCAM in particular. The present technology also focuses on automatic error correction of all configuration memories such as SRAM, SRF and TCAM without software (S / W) intervention, and focuses on optimizing hardware (H / W) logic and latency for error detection and correction of configuration memories such as SRAM and SRF.

[0028] LEAN and compare and detect (CAD) schemes are capable of detecting any number of bit flips in about a few nanoseconds in all kinds of semiconductor memory elements including SRAM, SRF and TCAM memory elements. LEAN and CAD-correction (CAD-C) schemes are capable of automatically correcting errors in tens of nanoseconds even under full (100%) traffic load without any software intervention. The CAD scheme is capable of detecting any number of bit flips without any redundant parity bits and / or error correction code (ECC) bits or logic, thus saving cost. The CAD-C scheme is capable of automatically correcting any number of bit flips without the need for expensive ECC bits and logic. LEAN and CAD-C schemes optimize critical packet path latency as well as chip area and power, for example by eliminating column multiplexing in macros. The critical path can be determined by using timing simulation of the chip circuit system.

[0029] Column multiplexing in macros can be eliminated, saving chip area and power consumption as well as achieving favorable aspect ratios to help eliminate congestion and achieve better timing in physical design. An auxiliary state machine is provided to periodically access the macros at configurable time intervals. In this regard, it is important to note the following facts. Errors in a given macro may not be detected unless accessed by a packet or by a central processing unit (CPU); packets do not read the TCAM; and even worse, if this period is too long and the error is not detected and corrected in a timely manner, then a correctable bit flip in the macro can become an even undetectable error due to bit flips that are beyond the handling of the implemented mechanism. The present technology provides a configurable method for discarding all packets that hit a detected error entry even as soon as they are detected in the TCAM until they are corrected so that traffic is not forwarded incorrectly.

[0030] Figure 11 is a block diagram illustrating an example of a macro instantiation architecture 100 based on a LEAN scheme according to various aspects of the present technology. The macro instantiation architecture 100 includes a multiplexer (Mux) 110, a memory macro 120, an ECC logic 130, an ECC reporting logic 140, a functional logic 150, a logic 160, a corrected entry buffer logic 170, and a number of flops, including flops 122, 142, 172 and optional flops 124 and 152. The macro instantiation architecture 100 provides the ECC logic 130 and the ECC reporting logic 140 in parallel with the functional logic 150. This is an important feature of the disclosed technology, which is different from the prior art in that the ECC logic and reporting are in series with the functional logic. Write data input 102 is fed through multiplexer 110 to be written to memory macro 120, which is an instantiation of pre-designed memory (e.g., RAM, SRF, TCAM) used in a router or switch chip (e.g., semiconductor chip). In some implementations, memory macro 120 may store tables, such as ingress and egress address tables for a router or switch.

[0031] Functional logic 150 includes electronic circuitry capable of performing the functionality of a chip (e.g., a router or switch). ECC logic 130 includes logic circuitry and is responsible for error detection and correction. ECC reporting logic 140 includes logic circuitry for reporting error corrections to logic 160. Corrections from ECC logic 130 are provided to jumpers 172 through corrected entry buffer logic 170, which is a corrected entry buffer (cor_entry_buf) and is used to compensate for packet delivery rate (PDR) macro latency increases. The corrections are then sent to memory macro 120 via multiplexer 110. Jumpers 122 and optional jumpers 124 and 152 act as delays and can compensate for latency. In some implementations, a temporary cache memory is used to store corrected entries after correction by the ECC logic and provide the corrected data from the cache memory in response to a read operation while the corrected data is waiting to be written back to the memory macro 120.

[0032] Figure 2 It is a diagram illustrating various aspects of the technology according to the present invention. Figure 1 2 is a timing diagram 200 of an example of the flow of events in the LEAN scheme of FIG. 2. As can be seen from the timing diagram 200, a read command 210 is received during a clock cycle in which a read address 220 is valid. An event cluster 230 including events A, B, C, and D occurs within a clock cycle in which the read address 220 is valid. During event A, a read command 210 is received from a memory (e.g., Figure 1During event B, externally toggled memory data is available, ECC is checked, and one bit of error-corrected data is available. During event C, toggled error reporting is performed with cor_entry_buf enabled (e.g., Figure 1 During event D, cor_entry_buf is unavailable because it has already been written back to memory. Output data (DOUT) 240 includes error data (ED), corrected data (CDC) from cor_entry_buf available during events B, C, and D, and corrected data (CDM) directly from memory that becomes available after event E.

[0033] Figure 3 3 is a table 300 illustrating an example of bit flips in a TCAM. The error probabilities in the logic entries of a memory implemented with 7nm technology are shown for both SRAM and TCAM. The errors are shown as the number of bit flips, where a bit of data is changed from zero to one, or vice versa. For example, the probabilities of a 2-bit flip error are 19.75% and 19.72% for SRAM and TCAM, respectively, which are almost the same. For higher bit flip errors, the probabilities for SRAM and TCAM differ greatly. Even higher probabilities of five or more bit flips in TCAM are observed in 5nm technology. It should be noted that TCAM does not have local column multiplexing and the cost of error correction increases for any solution that emulates column multiplexing by duplicating parity bits and / or ECC bits per logic entry.

[0034] Figure 4 4 is a block diagram illustrating an example of a typical compare and detect (CAD) architecture 400 according to some aspects of the present technology. In a single packet processing pipeline (hereinafter, pipeline), the upper limit of bandwidth is mainly governed by a given technology. When the total supported bandwidth of a chip needs to be more than a single pipeline, multiple packet processing pipelines are used on the chip. Therefore, inevitably, there are copies of configuration memories (SRAM, SRF, and TCAM) with the same data for different pipelines on the chip. Since TCAM does not support dual comparisons (such as dual reads) available on SRAM and SRF, TCAM has even more copies of the same data because the data cannot be shared across two pipelines as in SRAM and SRF.

[0035] The present technology supports CAD, which compares the contents of corresponding locations across copies in a read / scan event to detect errors. CAD architecture 400 includes macros 410 (macro 0) and 420 (macro 2), logic circuitry 430, macro 440 with dual access support, access logic pipeline 450 (pipeline 0), and access logic pipeline 460 (pipeline 1). In some implementations, macros 410 and 420 may be TCAMs, and macro 440 may be SRAM or SRF. Input data packet 402 is read by macros 410 and 420, and logic circuitry 430 compares the contents of corresponding locations within macros 410 and 420 across copies in a read / scan event to detect errors. It should be noted that macros 410 and 420 (TCAM) are not separately disclosed in the register file. There is only one logic instance per pipeline (e.g., access logic pipeline 450 or access logic pipeline 460), so the content at all positions of macros 410 and 420 (TCAM) is always the same, except when there is an error, which will be detected by logic circuit system 430. If there is a mismatch at any position across macros 410 and 420, then the position is detected as having an error. Therefore, error detection does not require redundant bits (parity / ECC). It should be noted that it is extremely unlikely to have errors in both macros 410 and 420 (TCAM) at the same time. As will be discussed below, it is almost impossible to have exactly the same error across the same position in macros 410 and 420 (TCAM). Macro 440 may include associated data for providing output data 404. A typical TCAM stores the corresponding position in the key to be compared and the associated data. If the TCAM indicates a match, then this action is performed. For example, when 5-tuple data (e.g., source / destination IP addresses, source / destination ports, and protocol fields) is stored in the TCAM, actions such as “forward the packet to a specific destination,” “copy the packet to the CPU,” and / or “drop the packet” are stored in the associated data.

[0036] Figure 5 The diagram shows Figure 4 Table 500 is an example of the probability of having errors in two macros of the CAD. Table 500 is self-explanatory and indicates that although the mean time between failures (MTBF) of a 0.2 Mbit TCAM (512 x 200) is approximately 16,806,723 hours, Figure 4 The MTBF with errors in both macros 410 and 420 is about 1.16E+17 years, which is even much longer than the age of the universe. In addition, it is almost impossible to have the MTBF with exactly the same error at exactly the same position in both macros 410 and 420.

[0037] Figure 6is a block diagram illustrating an example of a CAD plus correction architecture 600 in accordance with some aspects of the present technology. The CAD plus correction architecture 600 is similar to Figure 4 CAD architecture 400 is implemented in the same manner as above, except that parity bit block 610 is added before logic circuit system 430. The contents of both macros 410 and 420 are configured by software to be identical. Parity bit block 610 is implemented to know which entry has an error so that another good entry can be used to correct the erroneous entry. In the case of having multiple (P) parity bits within parity bit block 610, each covering non-adjacent bits in a position, up to (2x P-1) consecutive bit reversals can be detected. For example, if parity bit block 610 with P=4 is implemented, it can detect up to seven (=2x4-1) consecutive bit reversals for automatic correction, which is guaranteed within tens of nanoseconds. If automatic correction is not possible (exceeding the supported number of consecutive bit reversals for a given chip), errors that cannot be corrected by hardware can still be indicated to the software so that the software can correct the error using existing error correction mechanisms.

[0038] In summary, CAD is the cheapest technique and provides full detection capability (any number of bit inversions in a logic entry) without any redundant bits (such as ECC and / or parity or corresponding logic). CAD can be implemented for any and all configuration memories that have multiple copies across the pipeline. Using CAD, column multiplexing can be completely removed from all macros, thus significantly saving chip area and power consumption.

[0039] When CAD is used, redundant ECC bits and logic for configuration tables are not needed. This is beneficial for chip area, power and latency savings. If auto-correction is desirable, only parity bits (only one, not many in the case of ECC bits) and logic (much simpler than ECC) are needed.

[0040] Fig. 7A 700A is a diagram illustrating an example of a column multiplexing scheme 700A outside a macro utilizing multiple ECC fields in accordance with some aspects of the present technology. In general, a macro implements column multiplexing where adjacent bits in a logical entry are stored in different physical entries. This implementation has significant overhead, especially for smaller macros. Column multiplexing can be implemented outside a macro to achieve a better aspect ratio for the macro (tall and narrow macros block horizontal routing, causing congestion in the floor plan), reduced area, reduced power, better timing for ECC implementation, and significantly wider macros that meet given timing specifications, which can reduce macro instance counts, thereby reducing overhead areas on the macro, test design (DFT), and chip.

[0041] When critical for a given application, sufficient ECC fields may be implemented for column multiplexing to reduce the probability of uncorrectable errors. This may result in having almost zero failures per unit time (FIT) or a long MTBF. As an example, if a given technology has a maximum of 7-bit upsets, the probability of uncorrectable errors may be reduced by implementing column multiplexing outside the macro with multiple ECC fields, interleaving the ECC bits while stored in the macro, as discussed below.

[0042] In an example column multiplexing scheme 700A that implements column multiplexing outside a macro using multiple ECC fields, an ECC field 710 consists of ECC fields E0 and E1, each having m bits, and a data field 720 includes the data bits in a logical entry. As shown, ECC field E0 only considers even bits (0, 2, 4, etc.) in the data bits, and ECC field E1 only considers odd bits (1, 3, 5, etc.) for ECC calculations. Therefore, any two-bit inversion can affect different ECC fields, thereby emulating column multiplexing. It should be noted that the ECC bits themselves need to be interleaved while being stored in the macro to ensure that no logically consecutive ECC bits are physically adjacent to each other in the macro. Using the column multiplexing scheme 700A, up to two-bit inversions can be detected and corrected; only three to five-bit inversions can be detected and not corrected; and six or more bit inversions cannot be detected.

[0043] Figure 7B 700B is a diagram illustrating an example of an interleaving scheme 700B for ECC bits while being stored in a macro in accordance with some aspects of the present technology. In the interleaving scheme 700B, the ECC fields 730 include interleaved ECC fields each having m bits, and the data field 740 includes n data bits that can be stored in a logical entry on a monolithic macro or multiple macros. In some implementations, the data bits may also be optionally interleaved with the ECC bits while being stored in the macro.

[0044] Figure 7C 700C and a corresponding table 770 are diagrams illustrating an example of a macro outer column multiplexing scheme 700C and a corresponding table 770 utilizing ECC fields according to some aspects of the present technology. The ECC field 750 consists of ECC fields E0, E1, and E2, each having m bits, and the data field 760 includes data bits that can be stored in a logical entry in one monolithic macro or multiple macros. As shown, the ECC field E0 considers only bits (0, 3, 6, etc.) of the data bits, the ECC field E1 considers only bits (1, 4, 7, etc.) for ECC calculations, and the ECC field E2 considers only bits (2, 5, 8, etc.) for ECC calculations.

[0045] As shown in table 770, using macro outer column multiplexing scheme 700C, one- to three-bit inversions can be detected and corrected; only four- to eight-bit inversions can be detected and not corrected; and even nine-bit or more inversions cannot be detected.

[0046] Figure 8 8 is a table 800 illustrating examples of required ECC bits and redundant parity bits for different numbers of data bits. Table 800 includes four columns 810, 820, 830, and 840. Column 810 shows the number of data bits. Column 820 shows the corresponding number of redundant ECC bits required to detect two bit flips and correct one bit flips per field. Column 830 indicates the corresponding number of redundant parity bits required to detect one bit flips per field, and column 840 includes comments that are self-explanatory. Fig. 99 is a diagram illustrating an example of a centralized state machine 910 for reading pipeline 920 entries. State machine 910 can trigger periodic read and / or scan events for configuration memory (e.g., SRAM, SRF, TCAM) entries, for example, with a configurable interval between read and / or scan events to facilitate detection and / or correction of errors. This is a supplement to packet and CPU rad access. It should be noted that packets are the main number of events for configuration memory, and packet events do not read TCAM entries. Pipeline 920 is a packet processing pipeline and includes a number (n) of pipelines (pipeline 0, pipeline 1... pipeline n). Each pipeline may include appropriate logic and / or circuit systems and configuration memories that are centrally read and / or scanned to detect and correct errors. The state machine facilitates detection and / or correction of errors by implementing one or more aspects of the present invention technology discussed above (e.g., LEAN, CAD, and CAD-C schemes) without any software intervention. In some implementations, the state machine 910 includes LEAN, CAD, and CAD-C architectures for implementing LEAN, CAD, and CAD-C schemes, respectively. For example, the LEAN architecture may include: ECC logic and ECC reporting logic, which are implemented in parallel with the functional logic; and a logic implementation scheme to separate the ECC check from the main logic path to reduce timing and latency. In one or more implementations, the state machine 910 implements the CAD scheme by comparing the contents of corresponding positions across copies of storage elements in the pipeline, and any number of bit flips can be detected without redundant parity bits and / or ECC bits or logic to save cost. In some implementations, the state machine 910 can implement the CAD scheme without the need for ECC bits and ECC logic to compare duplicate entries (duplicate copies of the same data entry) within all configuration memories on the semiconductor chip to detect errors. In one or more implementations, the state machine 910 can implement the CAD-C scheme to identify erroneous entries among the duplicate entries and automatically correct the erroneous entries without the need for software intervention or ECC logic to identify and correct the erroneous entries.

[0047] Fig.10 1 is a flow chart illustrating an example of an error detection and correction method 1000 according to some aspects of the present technology. The method 1000 includes converting a state machine (e.g., Fig. 9 910) is coupled to a number of pipelines (e.g., Fig. 9 920)(1010) and configure the state machine to access the configuration memory of the pipeline (e.g., Figure 1 120) to generate a plurality of events (1020). The method 1000 further includes configuring the state machine to implement the LEAN scheme (e.g. Figure 1) in order to reduce critical packet path latency, chip area, and chip power consumption (1030). The pipeline is a packet processing pipeline, and the event is one of a read event or a scan event of a configuration memory, during which the configuration memory is read or scanned, respectively.

[0048] Fig.11 1 is a flow chart illustrating an example of an error detection and correction method 1100 according to some aspects of the present technology. The method 1100 includes converting a state machine (e.g., Fig. 9 910) is coupled to a number of pipelines (e.g., Figure 4 450 and 460) (1110) and configure the state machine to access the configuration memory of the pipeline (e.g., Figure 4 410 and 420) to generate a plurality of events (1120). Method 1000 further includes configuring the state machine to implement the CAD scheme (such as Figure 4 ) in order to reduce critical packet path latency, chip area, and chip power consumption (1130). The pipeline is a packet processing pipeline, and the event is one of a read event or a scan event of a configuration memory.

[0049] Fig.12 1200 is an electronic system within which some aspects of the present technology are implemented. Electronic system 1200 may be and / or may be a portion of a network switch or router for a data center or enterprise network. Electronic system 1200 may include various types of computer-readable media and interfaces for various other types of computer-readable media. Electronic system 1200 includes bus 1208, one or more processing units 1212, system memory 1204 (and / or buffers), ROM 1210, permanent storage 1202, input device interface 1214, output device interface 1206, and one or more network interfaces 1216, or subsets and variations thereof.

[0050] Bus 1208 collectively represents all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of electronic system 1200. In one or more implementations, bus 1208 communicatively connects one or more processing units 1212 with ROM 1210, system memory 1204, and permanent storage 1202. From these various memory units, one or more processing units 1212 retrieve instructions to be executed and data to be processed in order to perform the processes of the present disclosure. In different implementations, one or more processing units 1212 may be a single processor or a multi-core processor. In one or more aspects, one or more processing units 1212 may be used to implement Fig. 9 The state machine 910 and / or implementation Fig.10 and 11method.

[0051] ROM 1210 stores static data and instructions required by one or more processing units 1212 and other modules of electronic system 1200. On the other hand, permanent storage 1202 can be a read and write memory device. Permanent storage 1202 can be a non-volatile memory unit that stores instructions and data even when electronic system 1200 is turned off. In one or more implementations, a mass storage device (such as a magnetic or optical disk and its corresponding magnetic disk drive) can be used as permanent storage 1202.

[0052] In one or more embodiments, a removable storage device (such as a floppy disk, a flash drive and its corresponding disk drive) may be used as the permanent storage device 1202. Like the permanent storage device 1202, the system memory 1204 may be a read and write memory device. However, unlike the permanent storage device 1202, the system memory 1204 may be a volatile read and write memory, such as a random access memory (RAM). The system memory 1204 may store any of the instructions and data that one or more processing units 1212 may need at runtime. In one or more embodiments, the processes of the present disclosure are stored in the system memory 1204, the permanent storage device 1202, and / or the ROM 1210. From these various memory units, the one or more processing units 1212 retrieve instructions to be executed and data to be processed in order to perform the processes of one or more embodiments. In one or more aspects, the storage unit 1202 may represent Figure 2 Pipeline 920 and Figure 1 Macro 120 or Figure 4 The storage elements within macros 410 and 420 are shown in FIG.

[0053] The bus 1208 is also connected to an input device interface 1214 and an output device interface 1206. The input device interface 1214 enables a user to communicate information and selection commands to the electronic system 1200. For example, input devices that can be used with the input device interface 1214 can include an alphanumeric keyboard and a pointing device (also referred to as a "cursor control device"). For example, the output device interface 1206 can enable the display of images generated by the electronic system 1200. For example, output devices that can be used with the output device interface 1206 can include a printer and a display device, such as a liquid crystal display (LCD), a light emitting diode (LED) display, an organic light emitting diode (OLED) display, a flexible display, a flat panel display, a solid-state display, a projector, or any other device for outputting information. One or more implementations can include a device that functions as both an input device and an output device, such as a touch screen. In these implementations, the feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and the input from the user can be received in any form including sound, voice, or tactile input.

[0054] Finally, if Fig.12 , bus 1208 also couples electronic system 1200 to one or more networks and / or to one or more network nodes through one or more network interfaces 1216. In this manner, electronic system 1200 may be part of a computer network, such as a local area network (LAN), a wide area network (WAN), an intranet, or a network of networks, such as the Internet. Any or all components of electronic system 1200 may be used in conjunction with the present disclosure.

[0055] Embodiments within the scope of the present disclosure may be implemented in part or in whole using a tangible computer-readable storage medium (or multiple tangible computer-readable storage media of one or more types) encoding one or more instructions. The tangible computer-readable storage medium may also be non-transitory in nature.

[0056] Computer-readable storage media may be any storage media that can be read, written, or otherwise accessed by a general or special purpose computing device, including any processing electronics and / or processing circuitry capable of executing instructions. For example, without limitation, computer-readable media may include any volatile semiconductor memory, such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. Computer-readable media may also include any non-volatile semiconductor memory, such as ROM, PROM, EPROM, EEPROM, NVRAM, Flash, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, racetrack memory, FJG, and Millipede memory.

[0057] Furthermore, the computer-readable storage medium may include any non-semiconductor memory, such as optical disk storage, magnetic disk storage, magnetic tape, other magnetic storage, or any other medium capable of storing one or more instructions. In one or more implementations, the tangible computer-readable storage medium may be directly coupled to the computing device, while in other implementations, the tangible computer-readable storage medium may be indirectly coupled to the computing device, such as via one or more wired connections, one or more wireless connections, or any combination thereof.

[0058] Instructions may be directly executable or may be used to develop executable instructions. For example, instructions may be implemented as executable or non-executable machine code or as instructions in a high-level language that may be compiled to produce executable or non-executable machine code. In addition, instructions may also be implemented as data or may include data. Computer executable instructions may also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, functions, etc. As recognized by those skilled in the art, details including but not limited to the number, structure, sequence, and organization of instructions may vary significantly without changing the underlying logic, function, processing, and output.

[0059] Although the above discussion primarily refers to microprocessors or multi-core processors that execute software, one or more implementations are performed by one or more integrated circuits (such as ASICs or FPGAs). In one or more implementations, such integrated circuits execute instructions stored on the circuits themselves or on a distributed storage system (such as a storage network).

[0060] Those skilled in the art will appreciate that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have generally been described above with respect to their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. The described functionality may be implemented in varying ways by a technician for each specific application. Various components and blocks may be arranged in different ways (e.g., arranged in different orders or partitioned in different ways), all without departing from the scope of the present technology.

[0061] It should be understood that any particular order or hierarchy of the blocks in the disclosed process is an illustration of an example method. Based on design preferences, it should be understood that the specific order or hierarchy of the blocks in the process can be rearranged, or all of the illustrated blocks can be executed. Any of the blocks can be executed simultaneously. In one or more embodiments, multitasking and parallel processing can be advantageous. In addition, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software / hardware product or packaged into multiple software / hardware products.

[0062] As used in this specification and any technical solution of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms exclude people or groups of people. For the purpose of this specification, the term "display" or "displaying" means displaying on an electronic device.

[0063] As used herein, the phrase "at least one of" following a list of items (with the terms "and" or "or" separating any of the items) modifies the list as a whole, rather than modifying each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each of the listed items; rather, the phrase recognizes a meaning that includes at least one of any of the items and / or at least one of any combination of the items and / or at least one of each of the items. By way of example, the phrases "at least one of A, B, and C" or "at least one of A, B, or C" each refer to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0064] The predicates "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of an object, but are intended to be used interchangeably. In one or more embodiments, a processor configured to monitor and control the operation of a component may also mean a processor programmed to monitor and control the operation or a processor operable to monitor and control the operation. Similarly, a processor configured to execute code may be configured as a processor programmed to execute code or operable to execute code.

[0065] Phrases such as "on one hand", "the aspect", "on the other hand", "some aspects", "one or more aspects", "an embodiment", "the embodiment", "another embodiment", "some embodiments", "one or more embodiments", "an example", "the example", "another example", "some examples", "one or more examples", "a configuration", "the configuration", "another configuration", "some configurations", "one or more configurations", "the present invention", "the present disclosure", "the present disclosure" and other variations thereof are for convenience and do not imply that the disclosure associated with such phrases is essential to the present invention or that this disclosure applies to all configurations of the present invention. The disclosure associated with such phrases may apply to all configurations or one or more configurations. The disclosure associated with such phrases may provide one or more examples. Phrases such as one hand or some aspects may refer to one or more aspects and vice versa, and this applies similarly to the other aforementioned phrases.

[0066] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Furthermore, to the extent the terms "including," "having," and the like are used in the specification or claims, such terms are intended to be inclusive in a manner similar to the meaning of the term "comprising" when "comprising" is used as a transition word in a technical solution.

[0067] All structural and functional equivalents of the elements of various aspects described throughout this disclosure that are known or later known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be committed to the public, regardless of whether such disclosure is explicitly described in the claims. Any technical solution element will not be interpreted according to the provisions of 35 U.S.C. §112 (f) unless the element is explicitly described using the phrase "means for...", or in the case of a method technical solution, the element is described using the phrase "step for...".

[0068] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. It will be readily apparent to those skilled in the art that various modifications to these aspects are possible, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given a full range consistent with the language technical scheme, wherein the reference to an element in the singular form is not intended to mean "one and only one" (unless specifically stated), but to mean "one or more". Unless otherwise specifically stated, the term "some" refers to one or more. Male pronouns (e.g., his) include female and neutral genders (e.g., her and its), and vice versa. If any, the title and subtitle are only used for convenient purposes and do not limit the disclosure of the present invention.

Claims

1. A system for error detection and correction, the system comprising: a plurality of pipelines, each pipeline coupled to one or more ports on the semiconductor chip and including a configuration memory; and a state machine coupled to the plurality of pipelines and configured to access the configuration memory to generate a plurality of events, each of the plurality of events having a configurable interval between them, in: The plurality of events include one of a read-type event or a scan-type event of the configuration memory, and the state machine is implemented in hardware and configured to detect and correct errors including erroneous memory entries across the configuration memory.

2. The system of claim 1, wherein a plurality of storage elements are embedded in the plurality of pipelines, and wherein the errors comprise bit flip errors within the plurality of storage elements of the plurality of pipelines.

3. The system of claim 2, wherein the state machine is configured to discard packets arriving at a detected erroneous memory entry until the erroneous memory entry is corrected to help prevent traffic from being erroneously forwarded. The system of claim 1 , wherein the plurality of events comprises periodic events having configurable time intervals. 5 . The system of claim 2 , wherein the plurality of storage elements comprises a configuration memory including one or more of a static random access memory (SRAM), a register file (SRF), or a ternary content addressable memory (TCAM).

6. The system of claim 1, wherein the state machine is configured to: Detect and correct errors by implementing a latency-efficient automatic correction (LEAN) approach; and Initiates periodic scans at configurable intervals to trigger read operations to check for errors.

7. The system of claim 6, wherein the state machine is configured to implement the LEAN scheme to reduce at least two of critical packet path latency, chip area, and chip power consumption.

8. The system of claim 7, wherein the state machine is configured to implement the LEAN scheme without column multiplexing of configuration memory in order to reduce at least two of the critical packet path latency, the chip area, and the chip power consumption.

9. The system of claim 7, wherein the LEAN scheme comprises: Error Correction Code (ECC) logic and ECC reporting logic implemented in parallel with the functional logic; and A logic implementation configured to separate ECC checking from the main logic path in order to reduce timing and latency.

10. The system of claim 9, wherein the LEAN architecture further comprises: logic configured to implement the LEAN scheme by writing correct entries back into storage elements of the plurality of pipelines, wherein the LEAN scheme is configured to automatically correct errors in less than 100 nanoseconds without software intervention even at 100% traffic load; A temporary cache memory is configured to store corrected entries after correction by the ECC logic and to provide corrected data from the cache memory in response to a read operation while the corrected data is awaiting write back to the macro.

11. The system of claim 1 , wherein the state machine is configured to detect errors by implementing a compare-and-detect CAD scheme without column multiplexing of configuration memory in order to reduce at least two of critical packet path latency, chip area, and chip power consumption.

12. The system of claim 11, wherein the state machine is configured to implement the CAD scheme by comparing contents of corresponding positions across copies of storage elements within the multiple pipelines, and wherein the CAD scheme is configured to detect bit flips without using parity bits and / or ECC bits or ECC logic to save cost.

13. The system of claim 12, wherein the state machine is configured to implement a CAD-correction (CAD-C) scheme by further using a block of parity bits configured to facilitate error detection to help prevent content containing errors from being used.

14. The system of claim 13, wherein the state machine is configured to implement the CAD-C scheme without requiring the ECC bits and the ECC logic in order to correct bit flip errors.

15. The system of claim 13, wherein the state machine is configured to implement the CAD scheme without requiring the ECC bits and the ECC logic to compare duplicate copies of data entries in order to detect errors.

16. The system of claim 13, wherein the state machine is configured to implement the CAD-C scheme without requiring software intervention or the ECC logic in order to identify erroneous entries among duplicate copies of data entries and correct the erroneous entries.

17. An error detection and correction method, the method comprising: coupling the state machine to a plurality of pipelines, the plurality of pipelines including a configuration memory; and The state machine is configured to do the following: accessing the configuration memory of the plurality of pipelines to generate a plurality of events having a configurable interval between each of the plurality of events; and Implementing a latency-efficient automatic calibration (LEAN) scheme to reduce at least two of critical packet path latency, chip area, and chip power consumption, in: The plurality of events include one of a read-type event or a scan-type event of the configuration memory.

18. The method of claim 17, further comprising implementing the LEAN scheme by providing ECC logic and ECC reporting logic in parallel with functional logic; and The correct entry is written back into the configuration memory.

19. The method of claim 18, further comprising configuring the state machine to reduce at least two of the critical packet path latency, the chip area, and the chip power consumption without column multiplexing configuration memory.

20. An error detection and correction method, the method comprising: coupling the state machine to a plurality of pipelines, the plurality of pipelines including a configuration memory; and The state machine is configured to do the following: accessing the configuration memory of the plurality of pipelines to generate a plurality of events having a configurable interval between each of the plurality of events; and Implementing a comparison and detection CAD scheme to reduce at least two of critical packet path latency, chip area, and chip power consumption, in: The plurality of events include one of a read-type event or a scan-type event in the configuration memory.

21. The method of claim 20, wherein said at least two of the critical packet path latency, the chip area, and the chip power consumption are reduced by removing the need for column multiplexing of configuration memory.

22. The method of claim 20, wherein implementing the CAD scheme comprises detecting bit flips in less than 100 nanoseconds in semiconductor memory elements including SRAM, SRF, and TCAM.

23. The method of claim 20, further comprising configuring the state machine to implement a CAD-C scheme to correct bit flip errors without the need for ECC bits and ECC logic by further using a block of parity bits to facilitate error detection by identifying the erroneous contents of corresponding locations of the configuration memory to prevent the erroneous contents from being used, wherein the CAD-C scheme is configured to automatically correct errors in less than 100 nanoseconds even under full traffic load without the need for software intervention.

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