A semiconductor device, a manufacturing method thereof, a packaging structure, and an electronic device

Abstract

The application provides a semiconductor device and a manufacturing method, a packaging structure and an electronic device, to improve the heat dissipation and reliability of the semiconductor device. The semiconductor device comprises a substrate, a protective layer, a first semiconductor layer, a first barrier layer, a second barrier layer and a channel layer arranged in sequence on the substrate, a source electrode, a drain electrode and a gate electrode are arranged on the side of the channel layer away from the substrate, and the gate electrode is located between the source electrode and the drain electrode; the substrate is made of diamond; the first barrier layer is made of indium aluminum gallium nitride; and the second barrier layer is made of aluminum nitride.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a semiconductor device, its fabrication method, packaging structure, and electronic equipment. Background Technology

[0002] High electron mobility transistors (HEMTs) are characterized by high power density and high operating frequency. At 4 GHz, the power density can reach 40 W / mm, which is about 10 times that of traditional semiconductor power devices. Therefore, HEMTs are often used in high-power radio frequency devices and electronic power devices, including radio frequency power amplifiers, automotive power electronics and next-generation high-efficiency power conversion devices.

[0003] In current gallium nitride (GaN) HEMT devices, GaN materials are typically grown on sapphire, silicon, or silicon carbide substrates via heteroepitaxial growth. Sapphire, silicon, or silicon carbide substrates have limitations in thermal conductivity. With the further development of communication technologies, GaN HEMT devices need to operate at higher frequencies and power densities, thus placing higher demands on heat dissipation. Furthermore, currently commercially available GaN HEMTs are primarily gallium polarimetric devices; the fabrication process for nitrogen polarimetric devices is still immature, and the quality of gallium nitride materials is relatively poor, making it impossible to achieve high-performance nitrogen polarimetric devices. Summary of the Invention

[0004] This application provides a semiconductor device, its fabrication method, packaging structure, and electronic device, which are used to improve the heat dissipation and reliability of the semiconductor device.

[0005] In a first aspect, this application provides a semiconductor device, which may include a substrate and a protective layer, a first semiconductor layer, a first barrier layer, a second barrier layer, and a channel layer disposed sequentially away from the substrate. A source, a drain, and a gate are disposed on the side of the channel layer opposite to the substrate, with the gate located between the source and drain. The first barrier layer may be made of indium aluminum gallium nitride (IALGaN), and the second barrier layer may be made of aluminum nitride. The substrate contains diamond, and the high thermal conductivity of diamond helps improve the heat dissipation performance of the semiconductor device. Furthermore, in this application, the substrate of the semiconductor device is relatively close to the two-dimensional electron gas located at the interface between the channel layer and the second barrier layer, thereby achieving near-junction heat dissipation. This allows the heat generated by the semiconductor device to be efficiently and quickly transferred to the substrate. Combined with the high thermal conductivity of the substrate, this effectively improves the heat dissipation performance and reliability of the semiconductor device.

[0006] In specific configurations, the substrate can be a diamond substrate or a composite substrate containing diamond components; this application does not impose any restrictions on this.

[0007] In some possible implementations, the source and drain can be formed by electron beam evaporation, and both the source and drain can be four-layer alloy structures. From the direction away from the substrate, the four layers of the source and drain can be made of titanium, aluminum, nickel, and gold, respectively. The gate can also be formed by electron beam evaporation, and the gate can be a two-layer alloy structure. From the direction away from the substrate, the two layers of the gate can be made of nickel and gold, respectively.

[0008] In some possible implementations, the aluminum content in the first barrier layer can be 10% to 50%, and the indium content can be 0% to 20%.

[0009] In some possible implementations, the thickness of the second barrier layer can be less than the thickness of the first barrier layer. By setting two barrier layers, the concentration of the two-dimensional electron gas can be increased, thereby improving the performance of the semiconductor device.

[0010] In some possible implementations, the channel layer can be a single-layer structure, in which case the channel layer material can be gallium nitride (GaN). Alternatively, the channel layer can be a two-layer structure, in which case the two layers of the channel layer, from the direction away from the substrate, can be made of gallium nitride (GaN) and aluminum gallium nitride (AlGaN), respectively. Furthermore, the channel layer can also be a three-layer structure, in which case the three layers of the channel layer, from the direction away from the substrate, can be made of gallium nitride (GaN), aluminum gallium nitride (AlGaN), and gallium nitride (GaN), respectively.

[0011] In some possible implementations, the semiconductor device may further include a second semiconductor layer disposed between the first semiconductor layer and the first barrier layer. The second semiconductor layer is an N-type semiconductor doped with silicon, wherein the silicon doping concentration may be 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 Adding a second semiconductor layer can provide a higher carrier concentration, which helps to improve device performance.

[0012] In some possible implementations, the semiconductor device may further include a third semiconductor layer, which may be disposed between the second semiconductor layer and the first barrier layer. The third semiconductor layer is an N-type semiconductor doped with silicon, wherein the silicon doping concentration may be 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The third semiconductor layer can regulate the stress between the second semiconductor layer and the first barrier layer, and can reduce the load at the interface between the second semiconductor layer and the first barrier layer, thereby helping to further improve the performance of the device.

[0013] In a specific configuration, the material of the third semiconductor layer can be aluminum gallium nitride, wherein the aluminum content can be 0% to 30%, and the aluminum content in the third semiconductor layer can gradually increase from the direction away from the substrate.

[0014] In some possible implementations, the semiconductor device may further include a fifth semiconductor layer, which may specifically be an N-type semiconductor. The fifth semiconductor layer may include a first portion and a second portion, wherein the first portion may be disposed between the source and the channel layer, and the second portion may be disposed between the drain and the channel layer. The fifth semiconductor layer can reduce the contact resistance between the source and drain and the channel layer, thereby improving the performance of the semiconductor device.

[0015] In some possible embodiments, from the direction away from the protective layer, the substrate may include a diamond nucleation layer, a diamond heat homogenizing layer, and a diamond support layer stacked sequentially, wherein the SP in the diamond heat homogenizing layer 3 The carbon content is higher than that of SP in the diamond nucleation layer and diamond support layer. 3 Carbon content. SP in diamond 3 The higher the carbon content, the better the thermal conductivity. Therefore, by setting a diamond heat exchanger layer with high thermal conductivity, the gate temperature can be reduced quickly, and the heat dissipation performance of semiconductor devices can be improved.

[0016] In some possible implementations, the semiconductor device may further include a support substrate disposed on the side of the substrate opposite to the protective layer. The support substrate may be made of silicon or silicon carbide. This design allows for a relatively thinner substrate. By growing a thinner substrate to form a heat diffusion layer, the manufacturing cost of the semiconductor device can be reduced while achieving effective heat dissipation.

[0017] In some possible implementations, the edge of the protective layer may extend beyond the first semiconductor layer and form a stepped surface. The semiconductor device may also include a first passivation layer covering the surface and sidewalls of the semiconductor device. The surface of the semiconductor device may include the stepped surface and the surfaces of the source, drain, gate, and channel layers facing away from the substrate. The sidewalls of the semiconductor device may include the sidewalls of the first semiconductor layer, the first barrier layer, the second barrier layer, and the channel layer. The first passivation layer can isolate the semiconductor device from other semiconductor devices in its vicinity, reducing electrical interference from these other semiconductor devices.

[0018] In specific configurations, the first passivation layer can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0019] In addition, the semiconductor device may also include a second passivation layer, which may be disposed between the gate and the channel layer to ensure the gate's withstand voltage. Specifically, the second passivation layer may be formed by atomic layer deposition or chemical vapor deposition.

[0020] In some possible implementations, a slot may be provided at the position of the gate in the channel layer. In this case, the gate may include a body and a protrusion, and the protrusion may be filled in the slot. This design can reduce the distance between the gate and the two-dimensional electron gas and enhance the gate's control capability over the two-dimensional electron gas in high-frequency devices.

[0021] In some possible implementations, a via may be provided on the substrate at the location corresponding to the source electrode. This via may sequentially penetrate the protective layer, the first semiconductor layer, the barrier layer, and the channel layer, exposing the source electrode. The semiconductor device may also include a back electrode disposed on the side of the substrate away from the protective layer. The back electrode may extend into the via and be electrically connected to the source electrode, thereby reducing the number of bonding wires during the electrode packaging process and improving the reliability of the semiconductor device.

[0022] Secondly, this application also provides a packaging structure, which may include a substrate and a semiconductor device as described in any of the aforementioned possible embodiments. The semiconductor device may be disposed on the substrate. The semiconductor device uses a high thermal conductivity substrate, and through structural design, the substrate is made closer to a two-dimensional electron gas. Heat can be quickly transferred through the high thermal conductivity substrate to the packaging substrate and carried away, thereby improving the reliability of the packaging structure.

[0023] Thirdly, this application also provides an electronic device, which may include a circuit board and the packaging structure described above, with the packaging structure disposed on the circuit board. Because semiconductor devices have advantages such as high heat dissipation performance and high reliability, the performance stability of this electronic device is improved.

[0024] Fourthly, this application also provides a method for fabricating a semiconductor device, which may include the following steps:

[0025] An epitaxial structure is formed on the original substrate. The epitaxial structure may include a buffer layer, an intrinsic semiconductor layer and a first semiconductor layer disposed sequentially away from the original substrate.

[0026] A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate;

[0027] A substrate is formed on the side of the protective layer away from the original substrate, and the substrate material contains diamond.

[0028] Remove the original substrate, buffer layer, and intrinsic semiconductor layer to expose the first semiconductor layer;

[0029] A first barrier layer and a second barrier layer are sequentially formed on the side of the first semiconductor layer away from the substrate;

[0030] A channel layer is formed on the side of the second barrier layer away from the substrate, and a source, drain, and gate are fabricated on the channel layer, with the gate located between the source and drain.

[0031] The fabrication method provided in this application solves the problem of poor material quality caused by directly epitaxially growing a nitrogen polar surface on the substrate by growing a substrate with high thermal conductivity on the surface of the epitaxial structure. On the other hand, since there is no buffer layer and intrinsic semiconductor layer between the substrate and the two-dimensional electron gas located at the interface between the channel layer and the second barrier layer, the substrate is closer to the two-dimensional electron gas, thereby achieving near-junction heat dissipation. In this way, the heat generated by the semiconductor device can be efficiently and quickly transferred to the substrate. Combined with the high thermal conductivity of the substrate, the heat dissipation performance of the semiconductor device can be effectively improved.

[0032] In some possible implementations, the epitaxial structure may further include an etch stop layer disposed between the intrinsic semiconductor layer and the first semiconductor layer. After removing the original substrate, buffer layer, and intrinsic semiconductor layer, the fabrication method may further include removing the etch stop layer to expose the first semiconductor layer. By providing an etch stop layer, the etching interface can be accurately stopped at the etch stop layer after the buffer layer and intrinsic semiconductor layer are etched away, and then the etch stop layer can be removed by dry etching, which can reduce the impact on the channel layer and thus improve the surface quality of the channel layer.

[0033] In some possible implementations, after exposing the first semiconductor layer, the above fabrication method may further include:

[0034] A second semiconductor layer is formed on the side of the first semiconductor layer facing away from the substrate. The second semiconductor layer is an N-type semiconductor doped with silicon, wherein the silicon doping concentration can be 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

[0035] In some possible implementations, after the second semiconductor layer is formed on the side of the first semiconductor layer facing away from the substrate, the above fabrication method may further include:

[0036] A third semiconductor layer is formed on the side of the second semiconductor layer facing away from the substrate. The third semiconductor layer is an N-type semiconductor doped with silicon, wherein the silicon doping concentration can be 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

[0037] In some possible implementations, the above fabrication method may further include: sequentially etching the channel layer, the second barrier layer, the first barrier layer and the first semiconductor layer on the periphery of the channel layer to expose the edge of the protective layer, and forming a step surface at the edge of the protective layer;

[0038] A first passivation layer is formed on the surface and sidewalls of a semiconductor device. The surface of the semiconductor device may include a stepped surface and the side surface of the source, drain, gate and channel layers facing away from the substrate. The sidewalls of the semiconductor device may include the sidewalls of the first semiconductor layer, the first barrier layer, the second barrier layer and the channel layer.

[0039] Fifthly, this application also provides a method for fabricating a semiconductor device, which may include the following steps:

[0040] An epitaxial structure is formed on the original substrate. The epitaxial structure may include a buffer layer, an intrinsic semiconductor layer, an etch barrier layer, a channel layer, a barrier stack structure and a first semiconductor layer disposed sequentially away from the original substrate. The barrier stack structure may include a first barrier layer and a second barrier layer, with the second barrier layer located between the channel layer and the first barrier layer.

[0041] A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate;

[0042] A substrate is formed on the side of the protective layer away from the original substrate, and the substrate material contains diamond.

[0043] Remove the original substrate, buffer layer, intrinsic semiconductor layer and etch barrier layer to expose the channel layer;

[0044] The source, drain, and gate are fabricated on the channel layer, with the gate located between the source and drain.

[0045] The fabrication method provided in this application solves the problem of poor material quality caused by directly epitaxially growing a nitrogen polar surface on the substrate by growing a substrate with high thermal conductivity on the surface of the epitaxial structure. On the other hand, since there is no buffer layer and intrinsic semiconductor layer between the substrate and the two-dimensional electron gas located at the interface between the channel layer and the barrier layer, the substrate is closer to the two-dimensional electron gas, thereby achieving near-junction heat dissipation. In this way, the heat generated by the semiconductor device can be efficiently and quickly transferred to the substrate. Combined with the high thermal conductivity of the substrate, the heat dissipation performance of the semiconductor device can be effectively improved.

[0046] Sixthly, this application also provides a method for fabricating a semiconductor device, which may include the following steps:

[0047] An epitaxial structure is formed on the original substrate. The epitaxial structure may include a buffer layer, an intrinsic semiconductor layer, a first barrier layer and a first semiconductor layer disposed sequentially away from the original substrate.

[0048] A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate;

[0049] A substrate is formed on the side of the protective layer away from the original substrate, and the substrate material contains diamond.

[0050] Remove the original substrate, buffer layer and intrinsic semiconductor layer to expose the first barrier layer;

[0051] A second barrier layer is formed on the side of the first barrier layer that is away from the substrate;

[0052] A channel layer is formed on the side of the second barrier layer away from the substrate;

[0053] The source, drain, and gate are fabricated on the channel layer, with the gate located between the source and drain.

[0054] The fabrication method provided in this application solves the problem of poor material quality caused by directly epitaxially growing a nitrogen polar surface on the substrate by growing a substrate with high thermal conductivity on the surface of the epitaxial structure. On the other hand, since there is no buffer layer and intrinsic semiconductor layer between the substrate and the two-dimensional electron gas located between the channel layer and the barrier layer, the substrate is closer to the two-dimensional electron gas, thereby achieving near-junction heat dissipation. In this way, the heat generated by the semiconductor device can be efficiently and quickly transferred to the substrate. Combined with the high thermal conductivity of the substrate, the heat dissipation performance of the semiconductor device can be effectively improved. Attached Figure Description

[0055] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0056] Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0057] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0058] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0060] Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0061] Figure 7 A flowchart illustrating a method for fabricating a semiconductor device provided in an embodiment of this application;

[0062] Figure 8 for Figure 7 A schematic diagram of the semiconductor device structure during step 103 of the process;

[0063] Figure 9 for Figure 7 A schematic diagram of the semiconductor device structure during step 106 of the process;

[0064] Figure 10 A flowchart illustrating another method for fabricating a semiconductor device provided in an embodiment of this application;

[0065] Figure 11 for Figure 10 A schematic diagram of the structure of a semiconductor device in step 203 of the processing;

[0066] Figure 12 for Figure 10 A schematic diagram of the structure of a semiconductor device in step 204 of the process;

[0067] Figure 13 A flowchart illustrating another method for fabricating a semiconductor device provided in an embodiment of this application;

[0068] Figure 14 for Figure 13 A schematic diagram of the semiconductor device structure during step 303 of the process;

[0069] Figure 15 for Figure 13 A schematic diagram of the semiconductor device structure during step 306 of the processing;

[0070] Figure 16 This is a schematic diagram of the packaging structure provided in an embodiment of this application. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings.

[0072] HEMT is a heterojunction field-effect transistor, also known as a modulation-doped field-effect transistor (MODFET), two-dimensional electron gas field-effect transistor (2-DEGFET), and selectively-doped heterojunction transistor (SDHT). Nitride HEMTs feature high power density and high operating frequency (f). TWith features such as 225GHz, the power density at 4GHz can reach 40W / mm, which is about 10 times that of traditional semiconductor power devices. Therefore, nitride HEMTs are often used in high-power radio frequency devices and electronic power devices, including radio frequency power amplifiers, automotive power electronics and next-generation high-efficiency power conversion devices.

[0073] HEMTs are voltage-controlled devices. The gate voltage controls the depth of the heterojunction potential well, which in turn controls the areal density of the two-dimensional electron gas within the well, further controlling the device's operating current. It should be noted that if the movement of electrons in a three-dimensional solid is blocked in one direction, the electrons can only move freely in the other two directions; such free electrons with two degrees of freedom are called two-dimensional electron gases. Currently, commercially available gallium nitride (GaN) HEMTs are mainly Ga-face devices. When the device is turned off with a negative gate voltage, the wave function of the two-dimensional electron gas in the Ga-face device is no longer positionally restricted but moves towards the substrate, resulting in enhanced scattering and a decrease in the mobility of the two-dimensional electron gas, thus degrading device performance. In contrast, the N-face GaN heterojunction possesses a natural aluminum gallium nitride (AlGaN) back barrier, which can confine the wave function of the two-dimensional electron gas to the GaN / AlGaN interface, enhancing the confinement of electrons and thus weakening the short-channel effect, which is beneficial for realizing higher-frequency GaN HEMT devices. However, the current process for manufacturing N-face devices is not yet mature, the quality of N-face GaN crystals is poor, the surface morphology is rough and irregular, and the heat dissipation performance of the devices is also relatively poor.

[0074] In current GaN HEMT devices, GaN material is generally grown on sapphire, Si, or SiC substrates via heteroepitaxial growth. It's important to note that heteroepitaxial growth refers to the process of growing an epitaxial layer with a different film material than the substrate, or even a completely different chemical composition and physical structure. Sapphire and silicon substrates have low thermal conductivity; sapphire has a thermal conductivity of 30 W / (m·K), and silicon has a thermal conductivity of 150 W / (m·K). Using these two materials as substrates limits the performance of GaN HEMT devices at high power and high frequency. Silicon carbide substrates have a thermal conductivity of 450 W / (m·K), which is superior to sapphire and silicon substrates, alleviating heat dissipation issues to some extent. Therefore, most high-power GaN HEMT devices currently use silicon carbide substrates. However, with the further development of communication technology, GaN HEMT devices need to operate at higher frequencies and power densities, thus placing higher demands on heat dissipation.

[0075] Diamond has a thermal conductivity of up to 2000 W / (m·K), far exceeding that of silicon carbide. Using diamond as a substrate is a key technology for solving heat dissipation in high-frequency, high-power GaN devices. Currently, diamond substrate GaN devices are mainly realized through three methods. The first method involves directly growing GaN epitaxial structures on a diamond substrate. However, due to the lattice mismatch between GaN and diamond, the quality of GaN material grown on the diamond substrate is poor, failing to achieve good device performance. The second method involves growing GaN epitaxial structures on sapphire, silicon, or silicon carbide substrates, then completely or partially removing the original substrate and bonding the GaN epitaxial structure to a high thermal conductivity polycrystalline diamond substrate using a bonding process. However, the bonding layer formed by traditional bonding processes is relatively thick, resulting in a large interfacial thermal resistance between the GaN epitaxial structure and the diamond substrate, failing to leverage the heat dissipation advantages of diamond. While nanoscale bonding can significantly reduce interfacial thermal resistance, the bonding process places stringent requirements on the flatness and roughness of the diamond substrate surface. Furthermore, the bonding layer is prone to cracking after high and low temperature shocks, preventing this technology from being mass-produced. The third approach involves growing a GaN epitaxial structure on a sapphire, silicon, or silicon carbide substrate. Then, the side of the GaN epitaxial structure facing away from the original substrate is bonded to a temporary substrate using a bonding process. The original substrate of the GaN epitaxial structure is removed, and a polycrystalline diamond substrate is grown on the original substrate site using chemical vapor deposition. Finally, the temporary substrate is removed to fabricate the device. This technique requires bonding a temporary substrate first. During diamond growth, the process temperature is high (600–900°C). Under the high temperature and diamond growth stress conditions, the interface of the temporary bonding substrate is prone to failure and cracking. In addition, the removal of the temporary substrate can easily damage the surface of the epitaxial structure, increasing the risk of device defects.

[0076] In view of this, embodiments of this application provide a GaN HEMT device with a diamond substrate and a method for fabricating the same, so that the GaN HEMT device achieves good material quality and heat dissipation capability. The HEMT device and its fabrication method according to embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0077] Figure 1 This is a schematic diagram of a semiconductor device provided in an embodiment of this application. (Reference) Figure 1As shown in the embodiments of this application, the semiconductor device 1 can specifically be a GaN HEMT device. The GaN HEMT device may include a substrate 400, a protective layer 300, a first semiconductor layer 204, a first barrier layer 2071, a second barrier layer 2072, and a channel layer 208 stacked sequentially. The channel layer 208 has a source fabrication region and a drain fabrication region spaced apart. The source fabrication region and the drain fabrication region can be a recessed structure, that is, the source fabrication region and the drain fabrication region can be respectively formed in the channel layer 208. The semiconductor device 1 may also include a source 501 and a drain 502 respectively disposed in the source fabrication region and the drain fabrication region. A gate 503 is disposed on the side of the channel layer 208 away from the substrate. The gate 503 may specifically be located between the source 501 and the drain 502. When the device is working, the gate 503 can control the conduction or de-conduction of the source 501 and the drain 502 by receiving a control signal. Specifically, when a negative voltage is applied to the gate 503, the concentration of the two-dimensional electron gas at the corresponding position of the gate 503 is too low, and the source 501 and the drain 502 cannot conduct; as the voltage of the gate 503 gradually increases to a positive voltage, the concentration of the two-dimensional electron gas increases, and the source 501 and the drain 502 conduct.

[0078] The substrate 400 is made of a material containing diamond. For example, the substrate 400 can be a diamond substrate or a composite substrate containing diamond. Utilizing the high thermal conductivity of diamond, it helps improve the heat dissipation performance of the semiconductor device. The thickness of the substrate 400 can be between 30µm and 500µm. For example, the thickness of the substrate 400 can be 30µm, 100µm, 400µm, 500µm, etc.

[0079] The protective layer 300 can be a dielectric material, and the material of the protective layer 300 includes, but is not limited to, silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), or silicon dioxide (SiO2). The thickness of the protective layer 300 can be between 2nm and 100nm. For example, the thickness of the protective layer 300 can be 2nm, 10nm, 50nm, 80nm, 100nm, etc.

[0080] The material of the first semiconductor layer 204 includes, but is not limited to, GaN or AlGaN. When the material of the first semiconductor layer 204 is AlGaN, the Al content can be 0% to 30%. The thickness of the first semiconductor layer 204 can be between 0.005µm and 2µm. For example, the thickness of the first semiconductor layer 204 can specifically be 0.005µm, 0.1µm, 0.5µm, 1µm, 2µm, etc. The first semiconductor layer 204 can serve as a buffer structure to control the stress between the protective layers 300 subsequently formed in the epitaxial structure, reducing the impact of the protective layer 300 process on the interface layer. On the other hand, it can also adjust the thickness of the device to meet the withstand voltage performance requirements of different scenarios.

[0081] It should be noted that the component content of a certain component in the embodiments of this application can be understood as the percentage of the number of atoms of that component in a certain mass of all or part of the specific number of atoms of that material. For example, taking Al as the specific material of the first semiconductor layer. x Ga 1-x Taking N as an example, the Al content in the first semiconductor layer can be understood as the percentage of Al atoms in the total number of atoms of all metal elements in the etching barrier layer.

[0082] The first barrier layer 2071 can be made of indium aluminum gallium nitride (InAlGaN), wherein the aluminum (Al) content can be 10% to 50%, and the indium (In) content can be 0% to 20%. The thickness of the first barrier layer 2071 can be between 3 nm and 50 nm. For example, the thickness of the first barrier layer 2071 can be 3 nm, 10 nm, 20 nm, 40 nm, 50 nm, etc. The second barrier layer 2072 can be made of aluminum nitride (AlN), and the thickness can be between 0.5 nm and 10 nm. For example, the thickness of the second barrier layer 2072 can be 0.5 nm, 2 nm, 5 nm, 8 nm, 10 nm, etc.

[0083] The channel layer 208 can be a single-layer or multi-layer structure, such as two or three layers, and this application does not limit this. When the channel layer 208 is a single-layer structure, the material of the channel layer is GaN; when the channel layer 208 is a two-layer structure, the materials of the two layers of the channel layer 208 along the direction away from the substrate 400 can be GaN and AlGaN, respectively; when the channel layer 208 is a three-layer structure, the materials of the three layers of the channel layer 208 along the direction away from the substrate 400 can be GaN, AlGaN, and GaN, respectively. It should be noted that when the material of the channel layer 208 includes AlGaN, the content of Al can be 5% to 50%. The thickness of the channel layer 208 can be between 5nm and 50nm. For example, the thickness of the channel layer 208 can specifically be 5nm, 10nm, 20nm, 40nm, 50nm, etc.

[0084] Both source 501 and drain 502 can be four-layer alloy structures. Along the direction away from substrate 400, the materials of the four layers of source 501 and drain 502 can be titanium (Ti), Al, nickel (Ni), and gold (Au), respectively. For example, the thickness of each layer can be 22nm / 120nm / 55nm / 200nm, respectively. Gate 503 can be a two-layer alloy structure. Along the direction away from substrate 400, the materials of the two layers of gate 503 can be Ni and Au, respectively.

[0085] In this embodiment, the semiconductor device 1 may further include a second semiconductor layer 205 disposed between the first semiconductor layer 204 and the first barrier layer 2071. The material of the second semiconductor layer 205 includes, but is not limited to, GaN or AlGaN. It should be noted that when the material of the second semiconductor layer 205 is AlGaN, the Al content can be 0% to 20%. Specifically, the second semiconductor layer 205 may be an N-type semiconductor, and the dopant may be Si, wherein the Si doping concentration can be 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The thickness of the second semiconductor layer 205 can be between 5 nm and 100 nm. For example, the thickness of the second semiconductor layer 205 can specifically be 5 nm, 20 nm, 50 nm, 100 nm, etc. The second semiconductor layer 205 can provide a higher carrier concentration for the device, which helps to improve the performance of the device.

[0086] Furthermore, a third semiconductor layer 206 may be disposed between the second semiconductor layer 205 and the first barrier layer 2071. The third semiconductor layer 206 may be made of AlGaN, wherein the Al content may be 0% to 30%. In this embodiment, the Al content in the third semiconductor layer 206 may gradually increase from the direction away from the substrate 400. Specifically, the third semiconductor layer 206 may be an N-type semiconductor, and the dopant may be Si, wherein the Si doping concentration may be 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The thickness of the third semiconductor layer 206 can be between 5 nm and 50 nm. For example, the thickness of the third semiconductor layer 206 can specifically be 5 nm, 20 nm, 40 nm, 50 nm, etc. The third semiconductor layer 206 can adjust the stress between the second semiconductor layer 205 and the first barrier layer 2071, and can reduce the charge at the interface between the second semiconductor layer 205 and the first barrier layer 2071, thereby helping to further improve the performance of the device.

[0087] In some embodiments, the periphery of the substrate 400 and the protective layer 300 may extend beyond the layers above the protective layer, thereby forming a stepped structure at the edge of the protective layer 300. The semiconductor device 1 may also include a first passivation layer 600 disposed on the device surface and sidewalls. The material of the first passivation layer 600 includes, but is not limited to, Si3N4, Al2O3, or SiO2, and the thickness of the first passivation layer 600 may be between 10 nm and 200 nm. For example, the thickness of the protective layer may specifically be 10 nm, 50 nm, 100 nm, 200 nm, etc. The first passivation layer 600 can isolate the device from other semiconductor devices on its periphery, reducing electrical interference from other semiconductor devices on the semiconductor device. The device surface may include the stepped surface of the exposed protective layer 300 and the surfaces of the channel layer 208, source 501, drain 502 and gate 503. The device sidewalls include the sidewalls of the aforementioned channel layer 208, second barrier layer 2072, first barrier layer 2071, third semiconductor layer 206, second semiconductor layer 205, first semiconductor layer 204, source 501, drain 502 and gate 503. This achieves electrical isolation of the active region of the device, thereby reducing electrical interference between the device and other surrounding devices.

[0088] Additionally, the semiconductor device 1 may also include a second passivation layer 700, which may be disposed between the gate 503 and the channel layer 208 to ensure the voltage withstand capability of the gate 503. The material of the second passivation layer 700 includes, but is not limited to, Si3N4, Al2O3, or SiO2, and the thickness of the second passivation layer 700 may be between 1 nm and 10 nm. For example, the thickness of the second passivation layer 700 may specifically be 1 nm, 5 nm, 8 nm, 10 nm, etc.

[0089] Please continue to refer to this. Figure 1 In this embodiment of the application, the semiconductor device 1 may further include interconnect metal 800. In specific implementation, the first passivation layer 600 may be provided with openings at the positions corresponding to the gate 503, source 501 and drain 502 to expose the electrode metal. The interconnect metal 800 may be disposed on the first passivation layer 600 and filled in each opening, thereby realizing electrical connection with each electrode. Then, the corresponding electrodes of different devices can be interconnected through the interconnect metal 800 to form a multi-device unit structure.

[0090] In this embodiment, the substrate 400 of the semiconductor device 1 is relatively close to the two-dimensional electron gas located between the interface of the channel layer 208 and the second barrier layer 2072, thereby achieving near-junction heat dissipation. This allows the heat generated by the semiconductor device 1 to be efficiently and quickly transferred to the substrate 400. Combined with the high thermal conductivity of the substrate 400, this effectively improves the heat dissipation performance and reliability of the semiconductor device 1. Furthermore, in this embodiment, the GaN device is fabricated on an N-face GaN surface, and the barrier layer can form a natural back barrier structure, thereby enhancing the confinement of the two-dimensional electron gas, improving the device's high voltage withstand capability, and mitigating the short-channel effect.

[0091] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. (See reference...) Figure 2 As shown, in this embodiment, the semiconductor device 1 may further include a fifth semiconductor layer 209, which may be made of GaN. The fifth semiconductor layer 209 may include a first portion 2091 and a second portion 2092. The first portion 2091 may be disposed between the source 501 and the channel layer 208, and the second portion 2092 may be disposed between the drain 502 and the channel layer 208. Specifically, the fifth semiconductor layer 209 may be an N-type semiconductor. By providing the fifth semiconductor layer 209, the contact resistance between the source 501 and drain 502 and the channel layer 208 can be reduced, thereby improving the performance of the semiconductor device 1.

[0092] Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. (See reference...) Figure 3 As shown, in this embodiment, the channel layer 208 can be partially etched at the location where the gate 503 is disposed to form a slotted structure. When fabricating the gate 503, the bottom portion of the gate 503 can be filled into the slot 2081. That is, the gate 503 may include a body 5031 and a protrusion 5032 that matches the shape of the slot 2081. The protrusion 5032 is filled into the slot 2081. This design can reduce the distance between the gate 503 and the two-dimensional electron gas (between the interface of the second barrier layer 2072 and the channel layer 208), thereby enhancing the control capability of the high-frequency device gate over the two-dimensional electron gas.

[0093] It should be noted that when the semiconductor device 1 also includes a second passivation layer 700, the second passivation layer 700 also forms a groove-shaped structure corresponding to the slot of the channel layer 208. In this case, the protrusion 5032 of the gate 503 can be specifically disposed in the groove-shaped structure.

[0094] Figure 4 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. (See reference...) Figure 4 As shown, in this embodiment, the semiconductor device 1 may further include a back electrode 504, which may be disposed on the side of the substrate 400 away from the protective layer 300. A via is formed on the substrate 400 corresponding to the source electrode 501. This via sequentially penetrates the protective layer 300, the first semiconductor layer 204, the second semiconductor layer 205, the third semiconductor layer 206, the first barrier layer 2071, the second barrier layer 2072, and the channel layer 208 to expose a portion of the source electrode 501 facing the substrate 400. The back electrode 504 can extend into the via and be electrically connected to the source electrode 501, thereby reducing the number of bonding wires during the electrode packaging process and thus improving the reliability of the semiconductor device 1.

[0095] Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. (See reference...) Figure 5As shown, in this embodiment, the substrate 400 may include a three-layer structure. From the direction away from the protective layer 300, the three layers may be a diamond nucleation layer 410, a diamond heat homogenizing layer 420, and a diamond support layer 430, respectively. The thickness of the diamond nucleation layer 410 can be between 0.1 μm and 5 μm. For example, the thickness of the diamond nucleation layer 410 may specifically be 0.1 μm, 2 μm, 4 μm, 5 μm, etc. The thickness of the diamond heat homogenizing layer 420 can be between 2 μm and 50 μm. For example, the thickness of the diamond heat homogenizing layer 420 may specifically be 2 μm, 30 μm, 40 μm, 50 μm, etc. The thickness of the diamond support layer 430 can be between 30 μm and 500 μm. For example, the thickness of the diamond support layer 430 may specifically be 30 μm, 200 μm, 400 μm, 500 μm, etc.

[0096] In specific configurations, the SP in the diamond nucleation layer 410, the diamond heat homogenization layer 420, and the diamond support layer 430 3 The carbon content can vary. When preparing this three-layer structure, the amount of SP in different layers can be controlled by adjusting the ratio of hydrogen and methane during the vapor deposition process. 3 Carbon content, on the other hand, can also be controlled by adjusting the growth rate of diamond to affect SP. 3 Carbon content is controlled, for example, in diamonds prepared at high growth rates, SP content is controlled. 3 The carbon content will decrease. For example, in the various layers of the substrate, SP... 3 The carbon content is in the order of diamond uniform heat layer 420 > diamond support layer 430 > diamond nucleation layer 410, or it can also be diamond uniform heat layer 420 > diamond nucleation layer 410 > diamond support layer 430.

[0097] It should be noted that SP in diamond 3 The carbon content directly affects its thermal conductivity. Therefore, in the three-layer structure of substrate 400, the diamond heat-dampening layer 420 has the highest thermal conductivity. The heat source of GaN devices is mainly concentrated near the gate 503. By setting the high thermal conductivity diamond heat-dampening layer 420, the temperature of the gate 503 can be quickly reduced, improving the heat dissipation performance of the GaN device. As the thermally conductive support substrate for the entire device, the thermal conductivity requirement for the diamond support layer 430 can be relatively lower than that for the diamond heat-dampening layer 420. Therefore, the diamond support layer 430 can be fabricated at a high growth rate, which can minimize the manufacturing cost and improve the production efficiency of the device while ensuring its heat dissipation performance.

[0098] Figure 6 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. (See reference...) Figure 6As shown, in this embodiment, the semiconductor device 1 may further include a support substrate 900, which may be disposed on the back side of the substrate 400, that is, on the side of the substrate 400 opposite to the protective layer 300. In the fabrication process of the semiconductor device 1, the support substrate 900 may be formed after the substrate 400 is fabricated and before the original substrate is removed. Specifically, after the substrate 400 is formed, the side of the substrate 400 opposite to the protective layer 300 is polished, and then the support substrate 900 is bonded to the surface of the polished substrate 400. After that, the original substrate and part of the epitaxial structure are removed.

[0099] The supporting substrate 900 is made of materials including, but not limited to, Si or SiC. The thickness of the supporting substrate 900 can be between 30µm and 500µm; for example, the thickness of the supporting substrate 900 can be 30µm, 100µm, 400µm, 500µm, etc. The thickness of the substrate 400 is also relatively thinner compared to the aforementioned embodiments. In specific implementations, the thickness of the substrate 400 can be between 2µm and 100µm; for example, the thickness of the substrate 400 can be 2µm, 50µm, 80µm, 100µm, etc. This embodiment forms a heat diffusion layer by growing a thinner substrate 400, which can effectively dissipate heat from the device while also reducing the manufacturing cost of the device.

[0100] In the embodiments of this application, the above-mentioned semiconductor device can be fabricated by a variety of different manufacturing methods, which will be described below. Figure 1 Taking the semiconductor device shown as an example, several possible fabrication methods for the semiconductor device are explained in detail.

[0101] Figure 7 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 8 for Figure 7 A schematic diagram of the semiconductor device structure during step 103 of the process. Figure 9 for Figure 7 A schematic diagram of the semiconductor device structure during step 106 of the process. (See also...) Figure 1 as well as Figures 7 to 9 As shown, the method for fabricating a semiconductor device provided in this application embodiment may include the following steps:

[0102] Step 101: Grow an epitaxial structure on the original substrate 100. The original substrate 100 includes, but is not limited to, a Si substrate, a SiC substrate, a sapphire substrate, or a GaN substrate. The thickness of the original substrate can be between 600 μm and 1200 μm. For example, the thickness of the original substrate 100 can be 600 μm, 800 μm, 1000 μm, 1200 μm, etc. The epitaxial structure includes a buffer layer 201, an intrinsic semiconductor layer 202, and a first semiconductor layer 204 sequentially grown on the original substrate.

[0103] The buffer layer 201 can be a single-layer structure or a multi-layer structure, and this application does not impose any restrictions on this. When the buffer layer 201 is a single-layer structure, the material of the buffer layer 201 includes, but is not limited to, AlN, GaN, AlGaN, etc.; when the buffer layer 201 is a multi-layer structure, the materials of each layer of the buffer layer 201 can be different, and each layer can be one of AlN, GaN, and AlGaN. The thickness of the buffer layer 201 can be between 0.2um and 3um. For example, the thickness of the buffer layer 201 can specifically be 0.2um, 0.5um, 1um, 2um, 3um, etc.

[0104] The intrinsic semiconductor layer 202 can be made of GaN and its thickness can be between 0.1um and 10um. For example, the thickness of the intrinsic semiconductor layer 202 can be 0.1um, 0.5um, 1um, 5um, 10um, etc.

[0105] Step 102: A protective layer 300 is formed on the side of the first semiconductor layer 204 facing away from the original substrate 100. In a specific implementation, the protective layer 300 can be formed by a vapor deposition process.

[0106] Step 103: Form substrate 400 on the side of protective layer 300 opposite to the original substrate 100. In specific implementation, substrate 400 can be formed by chemical vapor deposition (CVD), such as microwave plasma chemical vapor deposition (MPCVD) or hot filament chemical vapor deposition (HFCVD).

[0107] Step 104: Remove the original substrate 100, buffer layer 201, and intrinsic semiconductor layer 202 to expose the first semiconductor layer 204. In specific implementations, the original substrate 100 can be removed by dry etching or wet etching; this application does not limit this. In some embodiments, the original substrate 100 can be thinned first using a grinding and polishing process, for example, to about 200 μm, before performing dry or wet etching, which can reduce the difficulty of removing the original substrate 100.

[0108] The buffer layer 201 and the intrinsic semiconductor layer 202 can be removed by dry etching. It should be noted that in some embodiments, the epitaxial structure may further include an etch stop layer 203, located between the aforementioned intrinsic semiconductor layer 202 and the first semiconductor layer 204. The etch stop layer 203 can be made of AlGaN, with an Al content of 5% to 50%. The thickness of the etch stop layer 203 can be between 2 nm and 50 nm. For example, the thickness of the etch stop layer 203 can be 2 nm, 5 nm, 20 nm, 30 nm, 50 nm, etc. By setting the etch stop layer 203, after etching away the buffer layer 201 and the intrinsic semiconductor layer 202, the etching interface can accurately stop at the etch stop layer 203, and then dry etching can continue to remove the etch stop layer 203, reducing the impact on the channel layer 204 and thus improving the surface quality of the channel layer 204.

[0109] Step 105: On the side of the first semiconductor layer 204 away from the substrate 400, the first barrier layer 2071 and the second barrier layer 2072 are epitaxially grown sequentially.

[0110] Step 106: Form a channel layer 208 on the side of the second barrier layer 2072 away from the substrate 400.

[0111] In some embodiments of this application, after removing the buffer layer 201 and the intrinsic semiconductor layer 202, and before forming the first barrier layer 2071 and the second barrier layer 2072, the method of fabricating the semiconductor device 1 may further include forming a second semiconductor layer 205 on the side of the first semiconductor layer 204 facing away from the substrate. By providing the second semiconductor layer 205, a higher carrier concentration can be provided, which helps to improve the performance of the device.

[0112] Furthermore, after forming the second semiconductor layer 205 and before forming the first barrier layer 2071 and the second barrier layer 2072, the method for fabricating the semiconductor device 1 may further include forming a third semiconductor layer 206 on the side of the second semiconductor layer 205 facing away from the substrate 400. The third semiconductor layer 206 can adjust the stress between the second semiconductor layer 205 and the first barrier layer 2071 and can reduce the load at the interface between the second semiconductor layer 205 and the first barrier layer 2071, thereby helping to further improve the performance of the device.

[0113] Step 107: A source electrode 501 and a drain electrode 502 are formed on the side of the channel layer 208 facing away from the substrate 400, with the source electrode 501 and drain electrode 502 spaced apart. The channel layer 208 has a source electrode fabrication region for pre-forming the source electrode and a drain electrode fabrication region for pre-forming the drain electrode. In specific implementation, the source electrode fabrication region and the drain electrode fabrication region can be partially etched, and then the source electrode 501 and drain electrode 502 can be formed in the etched source electrode fabrication region and drain electrode fabrication region, respectively. In this embodiment, the source electrode 501 and drain electrode 502 can be formed by electron beam evaporation. It should be noted that after forming the source electrode 501 and drain electrode 502, the device can be placed in a rapid annealing furnace for high-temperature annealing to form a high-performance ohmic contact.

[0114] Step 108: A gate 503 is formed on the side of the first semiconductor layer 204 away from the substrate. The gate 503 is located between the source 501 and the drain 502. The gate 503 can also be formed by electron beam evaporation.

[0115] Step 109: A first passivation layer 600 is formed on the surface and sidewalls of the device to isolate the device from other semiconductor devices in the surrounding area and reduce electrical interference from other semiconductor devices in the surrounding area. In specific implementation, the first passivation layer 600 can be formed by atomic layer deposition or by chemical vapor deposition, and this application does not limit it in this way.

[0116] In some embodiments of this application, before depositing the first passivation layer 600, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204 may be sequentially etched around the periphery of the channel layer 208, thereby forming a stepped structure at the edge of the protective layer. In this case, the device surface covered by the first passivation layer 600 may include the exposed stepped surface of the protective layer 300, as well as the surfaces of the channel layer 208, source 501, drain 502, and gate 503. The device sidewalls covered by the first passivation layer 600 include the sidewalls of the aforementioned channel layer 208, second barrier layer 2072, first barrier layer 2071, first semiconductor layer 204, source 501, drain 502, and gate 503.

[0117] Step 110: Interconnect metals 800 are formed on the surfaces of gate 503, source 501, and drain 502, respectively. In practice, the passivation layers on the surfaces of gate 503, source 501, and drain 502 can be removed first to expose the electrode metals. Then, interconnect metals 800 are deposited on each electrode. Subsequently, the corresponding electrodes of different devices can be interconnected through the interconnect metals 800 to form a multi-device unit structure.

[0118] It should be noted that, before forming the gate, the fabrication method of the semiconductor device 1 may further include: forming a second passivation layer 700 on the device surface and sidewalls. Specifically, after forming the source 501 and drain 502, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204 are sequentially etched around the active region of the channel layer 208, forming a step structure at the edge of the protective layer 300. Then, the second passivation layer 700 is formed on the device surface, including the step surface of the protective layer 300 and the surfaces of the channel layer 208, the source 501, the drain 502, and the gate 503, and on the device sidewalls, including the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204. Subsequently, when the first passivation layer 600 is formed, the first passivation layer 600 may cover the second passivation layer 700 on the step surface of the protective layer 300, the surface of the channel layer 208, the source 501, the drain 502 and the gate 503, and the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071 and the first semiconductor layer 204.

[0119] The second passivation layer 700 can be formed by atomic layer deposition or by chemical vapor deposition, and this application does not limit the formation of the passivation layer 700.

[0120] It should be noted that the material, thickness, and other parameters of the substrate 400, protective layer 300, first semiconductor layer 204, second semiconductor layer 205, third semiconductor layer 206, first barrier layer 2071, second barrier layer 2072, channel layer 208, source 501, drain 502, gate 503, first passivation layer 600, and second passivation layer 700 in this embodiment can be referred to the configuration method of the aforementioned embodiment, and will not be repeated here.

[0121] The semiconductor device fabrication method provided in this application provides an N-face GaN device fabrication method that grows a highly thermally conductive substrate 400 on the surface of an epitaxial structure and removes the original substrate 100 and buffer layer 201. This method addresses the issue of poor material quality caused by directly epitaxially growing N-face GaN on the substrate 400. Furthermore, since there is no buffer layer 201 or intrinsic semiconductor layer 202 between the substrate 400 and the two-dimensional electron gas, the substrate is closer to the two-dimensional electron gas, achieving near-junction heat dissipation. This allows the heat generated by the device to be efficiently and quickly transferred to the substrate 400. Combined with the high thermal conductivity of the substrate 400, this effectively improves the heat dissipation performance of the GaN HEMT device. Additionally, in existing GaN HEMT devices, the GaN heteroepitaxial growth results in a high dislocation density in the buffer layer 201, which can easily cause leakage current and reduce device reliability. However, the GaN HEMT device in this application completely removes the buffer layer 201 during fabrication, thus reducing the risk of device failure.

[0122] Furthermore, the GaN device in this embodiment is fabricated on an N-face GaN surface, and the barrier layer can form a natural back barrier structure, thereby enhancing the confinement of the two-dimensional electron gas, improving the high voltage withstand capability of the device, and weakening the short-channel effect of the device.

[0123] Figure 10 This is a flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of this application. Figure 11 for Figure 10 A schematic diagram of the structure of a semiconductor device in step 203 of the process. Figure 12 for Figure 10 A schematic diagram of the semiconductor device used in step 204 of the process. (See also...) Figure 1 as well as Figures 10 to 12 As shown, the method for fabricating the semiconductor device 1 may include the following steps:

[0124] Step 201: Grow an epitaxial structure on the original substrate 100. The original substrate 100 includes, but is not limited to, a Si substrate, a SiC substrate, a sapphire substrate, or a GaN substrate. The thickness of the original substrate 100 can be between 600 μm and 1200 μm. For example, the thickness of the original substrate 100 can be 600 μm, 800 μm, 1000 μm, 1200 μm, etc. The epitaxial structure includes a buffer layer 201, an intrinsic semiconductor layer 202, an etch stop layer 203, a channel layer 208, a barrier stack structure, and a first semiconductor layer 204, which are sequentially grown on the original substrate 100.

[0125] The buffer layer 201 can be a single-layer structure or a multi-layer structure, and this application does not impose any restrictions on this. When the buffer layer 201 is a single-layer structure, the material of the buffer layer 201 includes, but is not limited to, AlN, GaN, AlGaN, etc.; when the buffer layer 201 is a multi-layer structure, the materials of each layer of the buffer layer 201 can be different, and each layer can be one of AlN, GaN, and AlGaN. The thickness of the buffer layer 201 can be between 0.2um and 3um. For example, the thickness of the buffer layer 201 can specifically be 0.2um, 0.5um, 1um, 2um, 3um, etc.

[0126] The intrinsic semiconductor layer 202 can be made of GaN and its thickness can be between 0.1um and 10um. For example, the thickness of the intrinsic semiconductor layer 202 can be 0.1um, 0.5um, 1um, 5um, 10um, etc.

[0127] The etching barrier layer 203 can be made of AlGaN, wherein the Al content can be 5% to 50%. The thickness of the etching barrier layer 203 can be between 2nm and 50nm. For example, the thickness of the etching barrier layer 203 can be 2nm, 5nm, 20nm, 30nm, 50nm, etc.

[0128] The barrier stack structure includes a first barrier layer 2071 and a second barrier layer 2072, wherein the second barrier layer 2072 is disposed between the first barrier layer 2071 and the channel layer 208.

[0129] In some embodiments of this application, the epitaxial structure may further include a second semiconductor layer 205, which may be located between the first semiconductor layer 204 and the first barrier layer 2071. By providing the second semiconductor layer 205, a higher carrier concentration can be provided, which helps to improve the performance of the device.

[0130] Furthermore, the epitaxial structure may also include a third semiconductor layer 206, which may be located between the second semiconductor layer 205 and the first barrier layer 2071. The third semiconductor layer 206 can adjust the stress between the second semiconductor layer 205 and the first barrier layer 2071, and can reduce the load at the interface between the second semiconductor layer 205 and the first barrier layer 2071, thereby helping to further improve the performance of the device.

[0131] Step 202: A protective layer 300 is formed on the side of the first semiconductor layer 204 opposite to the original substrate 100. In a specific implementation, the protective layer 300 can be formed by a vapor deposition process.

[0132] Step 203: Form substrate 400 on the side of protective layer 300 opposite to the original substrate 100. In specific implementation, substrate 400 can be formed by chemical vapor deposition.

[0133] Step 204: Remove the original substrate 100, buffer layer 201, intrinsic semiconductor layer 202, and etch barrier layer 203 to expose the channel layer 208. In specific implementations, the original substrate 100 can be removed by dry etching or wet etching; this application does not limit this. In some embodiments, the original substrate 100 can be thinned first using a grinding and polishing process, for example, to about 200 μm, before performing dry or wet etching, which can reduce the difficulty of removing the original substrate 100.

[0134] The buffer layer 201, the intrinsic semiconductor layer 202, and the etch barrier layer 203 can be removed by dry etching. By setting the etch barrier layer 203, after etching away the buffer layer 201 and the intrinsic semiconductor layer 202, the etching interface can be accurately stopped at the etch barrier layer 203, and then the etch barrier layer 203 can be removed by dry etching, thereby reducing the impact on the channel layer 208 and improving the surface quality of the channel layer 208.

[0135] Step 205: A source electrode 501 and a drain electrode 502 are formed on the side of the channel layer 208 facing away from the substrate 400, with the source electrode 501 and drain electrode 502 spaced apart. The channel layer 208 has a source electrode fabrication region for pre-forming the source electrode and a drain electrode fabrication region for pre-forming the drain electrode. In specific implementation, the source electrode fabrication region and the drain electrode fabrication region can be partially etched, and then the source electrode 501 and drain electrode 502 can be formed in the etched source electrode fabrication region and drain electrode fabrication region, respectively. In this embodiment, the source electrode 501 and drain electrode 502 can be formed by electron beam evaporation. It should be noted that after forming the source electrode 501 and drain electrode 502, the device can be placed in a rapid annealing furnace for high-temperature annealing to form a high-performance ohmic contact.

[0136] Step 206: A gate 503 is formed on the side of the first semiconductor layer 204 facing away from the substrate 400. The gate 503 is located between the source 501 and the drain 502. The gate 503 can also be formed by electron beam evaporation.

[0137] Step 207: A first passivation layer 600 is formed on the surface and sidewalls of the device to isolate the device from other semiconductor devices in the surrounding area and reduce electrical interference from other semiconductor devices in the surrounding area. In specific implementation, the first passivation layer 600 can be formed by atomic layer deposition or by vapor deposition, and this application does not limit it in this way.

[0138] In some embodiments of this application, before depositing the first passivation layer 600, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204 may be sequentially etched around the periphery of the channel layer 208, thereby forming a stepped structure at the edge of the protective layer. In this case, the device surface covered by the first passivation layer 600 may include the exposed stepped surface of the protective layer 300, as well as the surfaces of the channel layer 208, source 501, drain 502, and gate 503. The device sidewalls covered by the first passivation layer 600 include the sidewalls of the aforementioned channel layer 208, second barrier layer 2072, first barrier layer 2071, third semiconductor layer 206, second semiconductor layer 205, first semiconductor layer 204, source 501, drain 502, and gate 503.

[0139] Step 208: Interconnect metals 800 are formed on the surfaces of gate 503, source 501, and drain 502, respectively. In practice, the passivation layers on the surfaces of gate 503, source 501, and drain 502 can be removed first to expose the electrode metals. Then, interconnect metals 800 are deposited on each electrode. Subsequently, the corresponding electrodes of different devices can be interconnected through the interconnect metals 800 to form a multi-device unit structure.

[0140] It should be noted that, prior to forming the gate, the fabrication method of the semiconductor device 1 may further include forming a second passivation layer 700 on the device surface and sidewalls. Specifically, after forming the source 501 and drain 502, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, the third semiconductor layer 206, the second semiconductor layer 205, and the first semiconductor layer 204 are sequentially etched around the active region of the channel layer 208, forming a step structure at the edge of the protective layer 300. Then, the second passivation layer 700 is formed on the device surface, including the step surface of the protective layer 300 and the surfaces of the channel layer 208, the source 501, the drain 502, and the gate 503, as well as on the device sidewalls, including the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204. Subsequently, when the first passivation layer 600 is formed, the first passivation layer 600 may cover the second passivation layer 700 on the step surface of the protective layer 300, the surface of the channel layer 208, the source 501, the drain 502 and the gate 503, as well as on the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, the third semiconductor layer 206, the second semiconductor layer 205 and the first semiconductor layer 204.

[0141] The second passivation layer 700 can be formed by atomic layer deposition or by vapor deposition, and this application does not limit the formation of the passivation layer 700.

[0142] Similarly, the material, thickness, and other parameters of the substrate 400, protective layer 300, first semiconductor layer 204, second semiconductor layer 205, third semiconductor layer 206, first barrier layer 2071, second barrier layer 2072, channel layer 208, source 501, drain 502, gate 503, first passivation layer 600, and second passivation layer 700 in this embodiment can be referred to the configuration method of the aforementioned embodiment, and will not be repeated here.

[0143] The semiconductor device fabrication method provided in this application provides an N-face GaN device fabrication method that grows a highly thermally conductive substrate 400 on the surface of an epitaxial structure and removes the original substrate 100 and buffer layer 201. This method addresses the issue of poor material quality caused by directly epitaxially growing N-face GaN on the substrate 400. Furthermore, since there is no buffer layer 201 or intrinsic semiconductor layer 202 between the substrate 400 and the two-dimensional electron gas, the substrate is closer to the two-dimensional electron gas, achieving near-junction heat dissipation. This allows the heat generated by the device to be efficiently and quickly transferred to the substrate 400. Combined with the high thermal conductivity of the substrate 400, this effectively improves the heat dissipation performance of the GaN HEMT device. Additionally, in existing GaN HEMT devices, the GaN heteroepitaxial growth results in a high dislocation density in the buffer layer 201, which can easily cause leakage current and reduce device reliability. However, the GaN HEMT device in this application completely removes the buffer layer 201 during fabrication, thus reducing the risk of device failure.

[0144] Furthermore, the GaN device in this embodiment is fabricated on an N-face GaN surface, and the barrier layer can form a natural back barrier structure, thereby enhancing the confinement of the two-dimensional electron gas, improving the high voltage withstand capability of the device, and weakening the short-channel effect of the device.

[0145] Figure 13 This is a flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of this application. Figure 14 for Figure 13 A schematic diagram of the semiconductor device structure during step 303 of the process. Figure 15 for Figure 13 A schematic diagram of the semiconductor device structure during step 306 of the processing. Figure 1 as well as Figures 13 to 15 As shown, the method for fabricating the semiconductor device 1 may include the following steps:

[0146] Step 301: Grow an epitaxial structure on the original substrate 100. The original substrate 100 includes, but is not limited to, a Si substrate, a SiC substrate, a sapphire substrate, or a GaN substrate. The thickness of the original substrate 100 can be between 600 μm and 1200 μm. For example, the thickness of the original substrate 100 can be 600 μm, 800 μm, 1000 μm, 1200 μm, etc. The epitaxial structure includes a buffer layer 201, an intrinsic semiconductor layer 202, a first barrier layer 2071, and a first semiconductor layer 204 sequentially grown on the original substrate 100.

[0147] The buffer layer 201 can be a single-layer structure or a multi-layer structure, and this application does not impose any restrictions on this. When the buffer layer 201 is a single-layer structure, the material of the buffer layer 201 includes, but is not limited to, AlN, GaN, AlGaN, etc.; when the buffer layer 201 is a multi-layer structure, the materials of each layer of the buffer layer 201 can be different, and each layer can be one of AlN, GaN, and AlGaN. The thickness of the buffer layer 201 can be between 0.2um and 3um. For example, the thickness of the buffer layer 201 can specifically be 0.2um, 0.5um, 1um, 2um, 3um, etc.

[0148] The intrinsic semiconductor layer 202 can be made of GaN and its thickness can be between 0.1um and 10um. For example, the thickness of the intrinsic semiconductor layer 202 can be 0.1um, 0.5um, 1um, 5um, 10um, etc.

[0149] In some embodiments of this application, the epitaxial structure may further include a second semiconductor layer 205, which may be located between the first semiconductor layer 204 and the first barrier layer 2071. By providing the second semiconductor layer 205, a higher carrier concentration can be provided, which helps to improve the performance of the device.

[0150] Furthermore, the epitaxial structure may also include a third semiconductor layer 206, which may be located between the second semiconductor layer 205 and the first barrier layer 2071. The third semiconductor layer 206 can adjust the stress between the second semiconductor layer 205 and the first barrier layer 2071, and can reduce the load at the interface between the second semiconductor layer 205 and the first barrier layer 2071, thereby helping to further improve the performance of the device.

[0151] Step 302: A protective layer 300 is formed on the side of the first semiconductor layer 204 opposite to the original substrate 100. In a specific implementation, the protective layer 300 can be formed by a vapor deposition process.

[0152] Step 303: Form substrate 400 on the side of protective layer 300 opposite to the original substrate 100. In specific implementation, substrate 400 can be formed by chemical vapor deposition.

[0153] Step 304: Remove the original substrate 100, buffer layer 201, and intrinsic semiconductor layer 202 to expose the first barrier layer 2071. In specific implementations, the original substrate 100 can be removed by dry etching or wet etching; this application does not limit this. In some embodiments, the original substrate 100 can be thinned first using a grinding and polishing process, for example, to about 200 μm, before performing dry or wet etching, which can reduce the difficulty of removing the original substrate 100.

[0154] The buffer layer 201 and the intrinsic semiconductor layer 202 can be removed by dry etching.

[0155] Step 305: Form a second barrier layer 2072 on the side of the first barrier layer 2071 that is away from the substrate.

[0156] Step 306: Form a channel layer on the side of the second barrier layer 2072 away from the substrate.

[0157] Step 307: A source electrode 501 and a drain electrode 502 are formed on the side of the channel layer 208 facing away from the substrate 400, with the source electrode 501 and drain electrode 502 spaced apart. The channel layer 208 has a source electrode fabrication region for pre-forming the source electrode and a drain electrode fabrication region for pre-forming the drain electrode. In specific implementation, the source electrode fabrication region and the drain electrode fabrication region can be partially etched, and then the source electrode 501 and drain electrode 502 can be formed in the etched source electrode fabrication region and drain electrode fabrication region, respectively. In this embodiment, the source electrode 501 and drain electrode 502 can be formed by electron beam evaporation. It should be noted that after forming the source electrode 501 and drain electrode 502, the device can be placed in a rapid annealing furnace for high-temperature annealing to form a high-performance ohmic contact.

[0158] Step 308: A gate 503 is formed on the side of the first semiconductor layer 204 away from the substrate. The gate 503 is located between the source 501 and the drain 502. The gate 503 can also be formed by electron beam evaporation.

[0159] Step 309: A first passivation layer 600 is formed on the surface and sidewalls of the device to isolate the device from other semiconductor devices on its periphery and reduce electrical interference from other semiconductor devices on the device. In specific implementation, the first passivation layer 600 can be formed by atomic layer deposition or by chemical vapor deposition, and this application does not limit it in this way.

[0160] In some embodiments of this application, before depositing the first passivation layer 600, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204 may be sequentially etched around the periphery of the channel layer 208, thereby forming a stepped structure at the edge of the protective layer. In this case, the device surface covered by the first passivation layer 600 may include the exposed stepped surface of the protective layer 300, as well as the surfaces of the channel layer 208, source 501, drain 502, and gate 503. The device sidewalls covered by the first passivation layer 600 include the sidewalls of the aforementioned channel layer 208, second barrier layer 2072, first barrier layer 2071, first semiconductor layer 204, source 501, drain 502, and gate 503.

[0161] Step 310: Interconnect metals 800 are formed on the surfaces of gate 503, source 501, and drain 502, respectively. In specific implementation, the passivation layers on the surfaces of gate 503, source 501, and drain 502 can be removed first to expose the electrode metals. Then, interconnect metals 800 are deposited on each electrode. Subsequently, the corresponding electrodes of different devices can be interconnected through the interconnect metals 800 to form a multi-device unit structure.

[0162] It should be noted that, before forming the gate, the fabrication method of the semiconductor device 1 may further include: forming a second passivation layer 700 on the device surface and sidewalls. Specifically, after forming the source 501 and drain 502, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204 are sequentially etched around the active region of the channel layer 208, forming a step structure at the edge of the protective layer 300. Then, the second passivation layer 700 is formed on the device surface, including the step surface of the protective layer 300 and the surfaces of the channel layer 208, the source 501, the drain 502, and the gate 503, and on the device sidewalls, including the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071, and the first semiconductor layer 204. Subsequently, when the first passivation layer 600 is formed, the first passivation layer 600 may cover the second passivation layer 700 on the step surface of the protective layer 300, the surface of the channel layer 208, the source 501, the drain 502 and the gate 503, and the sidewalls of the source 501, the drain 502, the gate 503, the channel layer 208, the second barrier layer 2072, the first barrier layer 2071 and the first semiconductor layer 204.

[0163] The second passivation layer 700 can be formed by atomic layer deposition or by chemical vapor deposition, and this application does not limit the formation of the passivation layer 700.

[0164] Similarly, the material, thickness, and other parameters of the substrate 400, protective layer 300, first semiconductor layer 204, second semiconductor layer 205, third semiconductor layer 206, first barrier layer 2071, second barrier layer 2072, channel layer 208, source 501, drain 502, gate 503, first passivation layer 600, and second passivation layer 700 in this embodiment can be referred to the configuration method of the aforementioned embodiment, and will not be repeated here.

[0165] The semiconductor device fabrication method provided in this application provides an N-face GaN device fabrication method that grows a highly thermally conductive substrate 400 on the surface of an epitaxial structure and removes the original substrate 100 and buffer layer 201. This method addresses the issue of poor material quality caused by directly epitaxially growing N-face GaN on the substrate 400. Furthermore, since there is no buffer layer 201 or intrinsic semiconductor layer 202 between the substrate 400 and the two-dimensional electron gas, the substrate is closer to the two-dimensional electron gas, achieving near-junction heat dissipation. This allows the heat generated by the device to be efficiently and quickly transferred to the substrate 400. Combined with the high thermal conductivity of the substrate 400, this effectively improves the heat dissipation performance of the GaN HEMT device. Additionally, in existing GaN HEMT devices, the GaN heteroepitaxial growth results in a high dislocation density in the buffer layer 201, which can easily cause leakage current and reduce device reliability. However, the GaN HEMT device in this application completely removes the buffer layer 201 during fabrication, thus reducing the risk of device failure.

[0166] Furthermore, the GaN device in this embodiment is fabricated on an N-face GaN surface, and the barrier layer can form a natural back barrier structure, thereby enhancing the confinement of the two-dimensional electron gas, improving the high voltage withstand capability of the device, and weakening the short-channel effect of the device.

[0167] refer to Figure 16As shown in the embodiments of this application, a packaging structure is also provided. This packaging structure may include a substrate 2, leads 3, and a semiconductor device 1 as described in any of the aforementioned possible embodiments. The semiconductor device 1 may be disposed on one side of the substrate 2, and the leads 3 are disposed on the same side of the substrate 2 as the semiconductor device 1, surrounding the semiconductor device 1. One end of the leads 3 is electrically connected to the semiconductor device 1. In some embodiments, the semiconductor device 1 may specifically be a GaN HEMT device. The semiconductor device 1 uses a high thermal conductivity substrate, and through structural design, the substrate is made closer to a two-dimensional electron gas, thereby effectively improving heat dissipation performance. Furthermore, by fabricating the semiconductor device 1 on an N-face GaN surface, the barrier layer can form a natural back barrier structure, thereby enhancing the confinement of the two-dimensional electron gas, improving the high voltage withstand capability of the semiconductor device 1, and weakening the short-channel effect of the semiconductor device 1, thus improving the reliability of the packaging structure.

[0168] This application also provides an electronic device, which can be a communication device, server, supercomputer, router, switch, or other device in the prior art. The electronic device may include a circuit board and the packaging structure described in the foregoing embodiments. The packaging structure can be fixed to the circuit board by means of soldering or other methods. Signal pins can be provided on the circuit board in areas avoiding the packaging structure. These signal pins can be electrically connected to the other end of a lead, allowing the packaging structure to connect to other devices through traces on the circuit board, thereby realizing the connection between the semiconductor device and external circuits. Because semiconductor devices have advantages such as high heat dissipation performance and high reliability, the performance stability of this electronic device is improved.

[0169] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The device includes a substrate and a protective layer, a first semiconductor layer, a first barrier layer, a second barrier layer, and a channel layer sequentially disposed on the substrate. A source, a drain, and a gate are disposed on the side of the channel layer away from the substrate, and the gate is located between the source and the drain. The substrate is made of a material containing diamond. The first barrier layer is made of indium aluminum gallium nitride, and the second barrier layer is made of aluminum nitride. Along a direction away from the protective layer, the substrate comprises a diamond nucleation layer, a diamond heat homogenization layer, and a diamond support layer stacked sequentially, wherein the SP in the diamond heat homogenization layer 3 The carbon content is higher than that of SP in the diamond nucleation layer and the diamond support layer. 3 Carbon content.

2. The semiconductor device as claimed in claim 1, characterized in that, The aluminum content in the first barrier layer is 10% to 50%, and the indium content is 0% to 20%.

3. The semiconductor device as described in claim 1, characterized in that, The thickness of the second barrier layer is less than the thickness of the first barrier layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The channel layer has a single-layer structure, and the material of the channel layer is gallium nitride; or... The channel layer has a two-layer structure, and along the direction away from the substrate, the two layers of the channel layer are made of gallium nitride and aluminum gallium nitride, respectively; or, The channel layer has a three-layer structure, and the materials of the three layers along the direction away from the substrate are gallium nitride, aluminum gallium nitride, and gallium nitride, respectively.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes a second semiconductor layer disposed between the first semiconductor layer and the first barrier layer. The second semiconductor layer is an N-type semiconductor doped with silicon, and the silicon doping concentration in the second semiconductor layer is 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

6. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes a third semiconductor layer disposed between the second semiconductor layer and the first barrier layer. The third semiconductor layer is an N-type semiconductor doped with silicon, and the silicon doping concentration in the third semiconductor layer is 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

7. The semiconductor device as claimed in claim 6, characterized in that, The third semiconductor layer is made of aluminum gallium nitride, and the aluminum content in the third semiconductor layer gradually increases from the direction away from the substrate.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes a fifth semiconductor layer, which is an N-type semiconductor. The fifth semiconductor layer includes a first portion and a second portion, wherein the first portion is disposed between the source and the channel layer, and the second portion is disposed between the drain and the channel layer.

9. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes a support substrate disposed on the side of the substrate opposite to the protective layer, and the support substrate is made of silicon or silicon carbide.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that, The edge of the protective layer extends beyond the first semiconductor layer and forms a stepped surface; The semiconductor device further includes a first passivation layer covering the surface and sidewalls of the semiconductor device. The surface of the semiconductor device includes the stepped surface, the source, the drain, the gate, and the side surface of the channel layer facing away from the substrate. The sidewalls of the semiconductor device include the first semiconductor layer, the first barrier layer, the second barrier layer, and the sidewalls of the channel layer.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes a second passivation layer disposed between the gate and the channel layer.

12. The semiconductor device according to any one of claims 1 to 3, characterized in that, The channel layer has a slot corresponding to the position of the gate. The gate includes a body and a protrusion, and the protrusion fills the slot.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that, The substrate has a via hole at the position corresponding to the source electrode. The via hole sequentially penetrates the protective layer, the first semiconductor layer, the first barrier layer, the second barrier layer, and the channel layer, and exposes the source electrode. The semiconductor device further includes a back electrode, which is disposed on the side of the substrate away from the protective layer, and extends into the via and is electrically connected to the source electrode.

14. A packaging structure, characterized in that, It includes a substrate and a semiconductor device as described in any one of claims 1 to 13, wherein the semiconductor device is disposed on the substrate.

15. An electronic device, characterized in that, It includes a circuit board and a packaging structure as described in claim 14, the packaging structure being disposed on the circuit board.

16. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial structure is formed on a primary substrate, the epitaxial structure comprising a buffer layer, an intrinsic semiconductor layer, and a first semiconductor layer disposed sequentially away from the primary substrate; A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate; A substrate is formed on the side of the protective layer opposite to the original substrate, and the substrate is made of a material containing diamond. Remove the original substrate, buffer layer, and intrinsic semiconductor layer to expose the first semiconductor layer; A first barrier layer and a second barrier layer are sequentially formed on the side of the first semiconductor layer away from the substrate; A channel layer is formed on the side of the second barrier layer away from the substrate, and a source, drain and gate are fabricated on the channel layer, with the gate located between the source and the drain; Along a direction away from the protective layer, the substrate comprises a diamond nucleation layer, a diamond heat homogenization layer, and a diamond support layer stacked sequentially, wherein the SP in the diamond heat homogenization layer 3 The carbon content is higher than that of SP in the diamond nucleation layer and the diamond support layer. 3 Carbon content.

17. The manufacturing method as described in claim 16, characterized in that, The epitaxial structure further includes an etch barrier layer disposed between the intrinsic semiconductor layer and the first semiconductor layer; After removing the original substrate, buffer layer, and intrinsic semiconductor layer, the fabrication method further includes: Remove the etch barrier layer to expose the first semiconductor layer.

18. The manufacturing method as described in claim 16 or 17, characterized in that, After exposing the first semiconductor layer, the fabrication method further includes: A second semiconductor layer is formed on the side of the first semiconductor layer facing away from the substrate. The second semiconductor layer is an N-type semiconductor doped with silicon, and the silicon doping concentration in the second semiconductor layer is 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

19. The manufacturing method as described in claim 18, characterized in that, After forming a second semiconductor layer on the side of the first semiconductor layer facing away from the substrate, the fabrication method further includes: A third semiconductor layer is formed on the side of the second semiconductor layer facing away from the substrate. The third semiconductor layer is disposed between the second semiconductor layer and the first barrier layer. The third semiconductor layer is an N-type semiconductor doped with silicon, and the silicon doping concentration in the third semiconductor layer is 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

20. The manufacturing method as described in claim 16 or 17, characterized in that, The manufacturing method further includes: The channel layer, the second barrier layer, the first barrier layer and the first semiconductor layer are sequentially etched around the periphery of the channel layer to expose the edge of the protective layer and form a stepped surface at the edge of the protective layer. A first passivation layer is formed on the surface and sidewalls of the semiconductor device. The surface of the semiconductor device includes the stepped surface, the source, the drain, the gate, and the side surface of the channel layer facing away from the substrate. The sidewalls of the semiconductor device include the first semiconductor layer, the first barrier layer, the second barrier layer, and the sidewalls of the channel layer.

21. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial structure is formed on a primary substrate. The epitaxial structure includes a buffer layer, an intrinsic semiconductor layer, an etch barrier layer, a channel layer, a barrier stack structure, and a first semiconductor layer disposed sequentially away from the primary substrate. The barrier stack structure includes a first barrier layer and a second barrier layer, with the second barrier layer located between the channel layer and the first barrier layer. A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate; A substrate is formed on the side of the protective layer opposite to the original substrate, and the substrate is made of a material containing diamond. Remove the original substrate, the buffer layer, the intrinsic semiconductor layer, and the etch barrier layer to expose the channel layer; A source, a drain, and a gate are fabricated on the channel layer, with the gate located between the source and the drain; Along a direction away from the protective layer, the substrate comprises a diamond nucleation layer, a diamond heat homogenization layer, and a diamond support layer stacked sequentially, wherein the SP in the diamond heat homogenization layer 3 The carbon content is higher than that of SP in the diamond nucleation layer and the diamond support layer. 3 Carbon content.

22. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial structure is formed on a primary substrate, the epitaxial structure comprising a buffer layer, an intrinsic semiconductor layer, a first barrier layer, and a first semiconductor layer disposed sequentially away from the primary substrate; A protective layer is formed on the side of the first semiconductor layer that faces away from the original substrate; A substrate is formed on the side of the protective layer opposite to the original substrate, and the substrate is made of a material containing diamond. Remove the original substrate, the buffer layer, and the intrinsic semiconductor layer to expose the first barrier layer; A second barrier layer is formed on the side of the first barrier layer that is away from the substrate; A channel layer is formed on the side of the second barrier layer away from the substrate; A source, a drain, and a gate are fabricated on the channel layer, with the gate located between the source and the drain; Along a direction away from the protective layer, the substrate comprises a diamond nucleation layer, a diamond heat homogenization layer, and a diamond support layer stacked sequentially, wherein the SP in the diamond heat homogenization layer 3 The carbon content is higher than that of SP in the diamond nucleation layer and the diamond support layer. 3 Carbon content.

Images