Display panel and display device

Abstract

The present invention discloses a display panel and a display device, wherein the display panel includes a plurality of shift registers arranged and cascaded along a first direction, the shift register includes a first output transistor and a second output transistor connected to its output end, the first output transistor and the second output transistor are arranged along a second direction, the first direction and the second direction intersect, and are both perpendicular to the thickness direction of the display panel. In the technical solution provided by the present invention, there is no upper and lower structure along the first direction between the first output transistor and the second output transistor, and there is no problem of uneven distribution of the corresponding gate number under process limit compression, which is conducive to improving the stability of the gate signal output from the output end of the shift register.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, medium and large-sized display panels have broad application prospects in the fields of automotive, tablets, laptops, televisions, etc.

[0003] The display panel generally includes a gate drive circuit for providing a scanning signal to the pixel circuit. The gate drive circuit generally includes a pull-up module and a pull-down module. The gate signal in the existing medium and large-sized display panels has an unstable problem, which affects the display effect. Summary of the invention

[0004] The present invention provides a display panel and a display device to solve the problem of unstable gate signals in existing medium and large-sized display panels.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising a plurality of shift registers arranged in a first direction and connected in cascade, the shift register comprising a first output transistor and a second output transistor, both of which are connected to an output end of the shift register;

[0006] The first output transistor and the second output transistor are arranged along a second direction, wherein the first direction and the second direction intersect and are both perpendicular to a thickness direction of the display panel.

[0007] Optionally, the active layer of the first output transistor and the active layer of the second output transistor are arranged along the second direction; and the gate connection line of the second output transistor bypasses the active layer of the first output transistor and is connected to the gate of the second output transistor.

[0008] Optionally, the gate of the first output transistor includes a first wiring portion extending along the first direction and a second wiring portion extending along the second direction, and the second wiring portion overlaps the active layer of the first output transistor;

[0009] The gate of the second output transistor includes a third wiring portion extending along the first direction and a fourth wiring portion extending along the second direction, and the fourth wiring portion overlaps the active layer of the second output transistor;

[0010] The third routing portion is located at a side of the fourth routing portion away from the first routing portion, and the second routing portion and the fourth routing portion are arranged at intervals;

[0011] Optionally, there are multiple second wiring portions in the gate of the first output transistor, and the multiple second wiring portions are arranged at intervals along the first direction; there are multiple fourth wiring portions in the gate of the second output transistor, and the multiple fourth wiring portions are arranged at intervals along the first direction;

[0012] Optionally, the number of the second routing portions is equal to the number of the fourth routing portions;

[0013] Optionally, the gate of the first output transistor and the gate of the second output transistor are arranged in the same layer;

[0014] Optionally, the number of the second routing portions and the number of the fourth routing portions are both odd-numbered rows.

[0015] Optionally, along the second direction, a length of an overlapping portion of the second routing portion and the active layer of the first output transistor is equal to a length of an overlapping portion of the fourth routing portion and the active layer of the second output transistor.

[0016] Optionally, it further includes a preset signal line extending along the first direction, the preset signal line includes a first preset signal line and a second preset signal line;

[0017] The first preset signal line is connected to the first electrode of the first output transistor through the first adapter line, the second electrode of the first output transistor is connected to the output end of the shift register, and the first output transistor is used to transmit the voltage on the first preset signal line to the output end of the shift register when it is turned on;

[0018] A first electrode of the second output transistor is connected to a second preset signal line through a second adapter line, a second electrode of the second output transistor is connected to an output end of the shift register, and the second output transistor is used to transmit a voltage on the second preset signal line to the output end of the shift register when it is turned on;

[0019] The second electrode of the first output transistor is connected to the second electrode of the second output transistor through a third switching line;

[0020] Optionally, there are a plurality of first adapter wires, a plurality of third adapter wires, and the first adapter wires, the third adapter wires, and the second routing portion are alternately arranged along the first direction;

[0021] There are multiple second adapter cables, and the second adapter cables, the third adapter cables, and the fourth routing portion are alternately arranged along the first direction;

[0022] Two opposite sides of the third switching line along the second direction overlap and connect with the active layer of the first output transistor and the active layer of the second output transistor respectively;

[0023] Optionally, one of the first preset signal line and the second preset signal line is a high potential signal line, and the other is a low potential signal line; or, one of the first preset signal line and the second preset signal line is a fixed potential signal line, and the other is a clock signal line.

[0024] Optionally, the third wiring portion overlaps with a third switching line connected to the second electrode of the second output transistor to form a first capacitor.

[0025] Optionally, it further includes an output signal line, the output signal line and the second preset signal line have the same extension direction, and the output signal line is connected to a third adapter line connected to the second electrode of the second output transistor through a via hole;

[0026] Preferably, the display panel further comprises a pixel circuit and a gate signal line extending along the second direction, the pixel circuit is connected to the output signal line via the gate signal line, and the gate signal line is located on a side of the second output transistor away from the first output transistor.

[0027] Optionally, the display panel further comprises a substrate and a plurality of conductive layers stacked in layers, the active layer of the first output transistor and the active layer of the second output transistor are arranged in the same layer and are both located on one side of the substrate;

[0028] The multi-layer conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer, the gate of the first output transistor and the gate of the second output transistor are located in the first conductive layer, the preset signal line and the switching line are located in the second conductive layer, and the output signal line is located in the third conductive layer;

[0029] Among them, along the thickness direction of the display panel, the vertical projection of the output signal line on the substrate is located between the vertical projection of the third routing portion on the substrate and the vertical projection of the second potential signal line on the substrate, and there is a gap between the vertical projections of the output signal line, the third routing portion and the second preset signal line on the substrate.

[0030] Optionally, one of the first preset signal line and the second preset signal line is a high potential signal line, and the other is a low potential signal line; the shift register further includes a first input transistor, a second input transistor, a first control transistor, a second control transistor, a third control transistor, a fourth control transistor and a fifth control transistor;

[0031] The first electrode of the first input transistor is connected to the third preset signal line, the second electrode of the first input transistor is connected to the gate of the first control transistor, the first electrode of the first control transistor is connected to the second clock signal line, the second electrode of the first control transistor is connected to the first electrode of the second control transistor, the second electrode of the second control transistor is connected to the gate of the first output transistor, the gate of the first input transistor is connected to the first clock signal line, and the gate of the second control transistor is connected to the second clock signal line;

[0032] The first electrode of the second input transistor is the trigger signal input terminal of the shift register, the second electrode of the second input transistor is connected to the gate of the second output transistor, and the gate of the second input transistor is connected to the first clock signal line; the first electrode of the third control transistor is connected to the first clock signal line, the second electrode of the third control transistor is connected to the second electrode of the first input transistor, and the gate of the third control transistor is connected to the second electrode of the second input transistor; the first electrode of the fourth control transistor is connected to the first preset signal line, the second electrode of the fourth control transistor is connected to the first electrode of the fifth control transistor, the second electrode of the fifth control transistor is connected to the second clock signal line, the gate of the fourth control transistor is connected to the second electrode of the first input transistor, and the gate of the fifth control transistor is connected to the gate of the second output transistor;

[0033] The second preset signal line and the third preset signal line have the same potential.

[0034] According to another aspect of the present invention, a display device is provided, comprising the display panel provided by any embodiment of the present invention.

[0035] The embodiment of the present invention provides a display panel and a display device, wherein the display panel includes a plurality of shift registers arranged and cascaded along a first direction, the shift register includes a first output transistor and a second output transistor, and the first output transistor and the second output transistor are both connected to the output end of the shift register; the first output transistor and the second output transistor are arranged along the second direction, thereby forming a layout structure of the first output transistor and the second output transistor arranged horizontally along the second direction. In the layout structure of this embodiment, there is no upper and lower structure along the first direction between the first output transistor and the second output transistor, so the problem of uneven distribution of the corresponding number of gates will not be involved in the case of process limit compression. Even when applied to medium and large-sized display panels, the number of gates of the first output transistor and the second output transistor can be guaranteed to be the same, which is conducive to improving the stability of the gate signal outputted from the output end of the shift register. In addition, the first output transistor and the second output transistor are arranged horizontally, so that the number of gates of the corresponding transistors can be arranged in odd rows. Compared with the structure in which the number of gates of transistors in the related art is arranged in even rows, this solution can reduce the occupied space of the transistors, thereby facilitating the realization of a narrower frame.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 It is a schematic diagram of a partial layout structure of a gate drive circuit in the related art;

[0039] Figure 2 A schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0043] Figure 6 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0044] Figure 7 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0045] Figure 8 A schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0046] Fig. 9 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0047] Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0048] Fig.11 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] As described in the background technology, the gate signal in the existing medium and large-sized display panels has an unstable problem. The inventors have found that the reason for the above problem is that when designing the layout of the medium and large-sized display panels, the pull-up transistors and pull-down transistors of the gate drive circuit are unevenly distributed, resulting in insufficient pull-up or pull-down of the gate signal, and thus unstable gate signal. For example, Figure 1 A schematic diagram of a partial layout structure of a gate drive circuit in the related art, refer to Figure 1 , the pull-up transistor Q1 and the pull-down transistor Q2 in the gate drive circuit are designed in an up-down arrangement, and the number of gates 1 of the pull-up transistor Q1 and the number of gates 2 of the pull-down transistor Q2 are both in an even number of rows (e.g., 4 rows each, a total of 8 rows). However, in medium and large-sized display panels, as the size of the panel is getting larger and larger, the driving capability of the gate drive circuit is also required to be higher and higher. The driving capability is proportional to the aspect ratio of the transistor, and the size of the corresponding transistor is also getting larger and larger. Due to the limitation of process limit compression, the pull-up transistor Q1 and the pull-down transistor Q2 cannot be arranged according to Figure 1The layout is carried out in an arrangement manner, and the extreme compression of the device size and the extreme compression of the layout space cannot meet the design requirement that the number of gates 1 of the pull-up transistor Q1 and the number of gates 2 of the pull-down transistor Q2 are both an even number of rows, so that the overall number of gates of the pull-up transistor Q1 and the pull-down transistor Q2 is an odd number of rows (e.g., 7 rows). In this way, the number of gates of one transistor is 3 rows, and the number of gates of the other transistor is 4 rows, which causes the problem of uneven distribution between the upper and lower parts, affects the stability of the gate signal, and thus affects the display effect.

[0052] In view of the above problems, an embodiment of the present invention provides a display panel, which solves the problem that transistors with odd-numbered rows of gates cannot be evenly distributed by changing the layout, thereby improving the stability of the gate signal.

[0053] Figure 2 A schematic diagram of a top view of a display panel provided by an embodiment of the present invention is shown. Figure 3 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention, Figure 4 A schematic diagram of a display panel layout structure provided by an embodiment of the present invention, referring to Figure 2-Figure 4 , the display panel 100 includes a plurality of shift registers 10 arranged and cascaded along a first direction. The output terminal out of the previous shift register 10 is connected to the input terminal IN of the next shift register 10, and can also be connected to the gate signal line 20 of this level. Among them, the input terminal IN of the first-level shift register 10 is connected to the start signal line to receive the start signal SIN transmitted on the start signal line. The shift register 10 can shift and output the input signal of the input terminal IN through the output terminal out, and the gate signal output from the output terminal out can be transmitted to the gate of the switching transistor in the pixel circuit through the corresponding gate signal line 20 to drive the switching transistor to work. Here, the gate signal can be used as a scanning signal Scan such as a data writing transistor and an initialization transistor in the pixel circuit, and can also be used as a light-emitting control signal EM of a light-emitting control transistor.

[0054] The shift register 10 includes a first output transistor T1 and a second output transistor T2, and the first output transistor T1 and the second output transistor T2 are both connected to the output terminal out of the shift register 10. The shift register 10 also includes a control module 110 connected to the gate of the first output transistor T1 and the gate of the second output transistor T2. Among them, the first output transistor T1 can be a pull-up transistor, and the second output transistor T2 can be a pull-down transistor. The first output transistor T1 and the second output transistor T2 can jointly realize the output of the gate signal under the control of the control module 110. The control module 110 can be located on the side of the first output transistor T1 away from the second output transistor T2. The control module 110, the first output transistor T1, and the second output transistor T2 can be arranged along the second direction.

[0055] in, Figure 4 Only partial structures of the first output transistor T1 and the second output transistor T2 are shown. Figure 4 As shown, the first output transistor T1 and the second output transistor T2 are arranged along the second direction. The active layer 11 of the first output transistor T1 and the active layer 21 of the second output transistor T2 may be arranged along the second direction. The first direction and the second direction intersect and are both perpendicular to the thickness direction of the display panel 100. In this embodiment, the first direction may be the Y direction and the second direction may be the X direction. The first direction and the second direction may be perpendicular.

[0056] Specifically, the gate connection line 23 of the second output transistor T2 bypasses the active layer 11 of the first output transistor T1 and is connected to the gate 22 of the second output transistor T2. The gate 22 of the second output transistor T2 overlaps with the orthographic projection of the active layer 21 of the second output transistor T2 on the substrate. The gate 22 of the second output transistor T2 does not overlap with the orthographic projection of the active layer 11 of the first output transistor T1 on the substrate. The gate 12 of the first output transistor T1 overlaps with the orthographic projection of the active layer 11 of the first output transistor T1 on the substrate. The gate 12 of the first output transistor T1 does not overlap with the orthographic projection of the active layer 21 of the second output transistor T2 on the substrate. Here, the gate connection line 23 of the second output transistor T2 bypasses the active layer 11 of the first output transistor T1, which means that the gate connection line 23 of the second output transistor T2 does not overlap with the orthographic projection of the active layer 11 of the first output transistor T1 on the substrate. For example, the second side of the active layer 11 of the first output transistor T1 (the side close to the active layer 21 of the second output transistor T2) is adjacent to (not in contact with) the first side of the active layer 21 of the second output transistor T2 (the side close to the active layer 11 of the first output transistor T1), and the gate 12 of the first output transistor T1 extends into from the first side of its active layer 11 (the side away from the active layer 21 of the second output transistor T2) to overlap with the active layer 11; and the gate 22 of the second output transistor T2 bypasses the active layer 21 of the first output transistor T1 via the gate connection line 23 and enters from the second side of the active layer 21 of the second output transistor T2 (the side away from the active layer 11 of the first output transistor T1). That is to say, by setting up two active layers arranged along the second direction, the gate of one of the transistors is directly extended to the top of the corresponding active layer and overlaps with the orthographic projection of the active layer on the substrate, and the gate of the other transistor enters through the winding and extends to the top of the corresponding active layer and overlaps with the orthographic projection of the active layer on the substrate, thereby forming two transistors arranged laterally, which structurally avoids the problem that the overall number of gates in an odd number of rows cannot be evenly distributed.

[0057] The display panel provided by the embodiment of the present invention includes a plurality of shift registers arranged and cascaded along a first direction, the shift register includes a first output transistor and a second output transistor, and the first output transistor and the second output transistor are both connected to the output end of the shift register; the first output transistor and the second output transistor are arranged along the second direction, thereby forming a layout structure of the first output transistor and the second output transistor arranged horizontally along the second direction. In the layout structure of this embodiment, there is no upper and lower structure along the first direction between the first output transistor and the second output transistor, so the problem of uneven distribution of the corresponding number of gates will not be involved in the case of process limit compression. Even when applied to medium and large-sized display panels, while ensuring that the first output transistor and the second output transistor have a sufficiently large channel width-to-length ratio, the number of gates of the first output transistor and the second output transistor can be ensured to be the same, which is conducive to improving the stability of the gate signal output from the output end of the shift register. In addition, the first output transistor and the second output transistor are arranged horizontally, so that the number of gates of the corresponding transistors can be arranged in odd rows. Compared with the structure in which the number of gates of the output transistors in the related art is arranged in even rows, this solution can reduce the occupied space of the transistors, thereby facilitating the realization of a narrower frame.

[0058] Optionally, the display panel 100 includes a display area AA and a non-display area NA arranged around the display area AA. The shift register 10 may be located in the non-display area NA. The pixel circuit may be located in the display area AA. The first output transistor T1 may be located on a side of the second output transistor T2 away from the display area AA. The active layer 11 of the first output transistor T1 may be located on a side of the active layer 21 of the second output transistor T2 away from the display area AA.

[0059] Here, "upper and lower structures" refer to upper and lower structures in the same plane. To facilitate the understanding of the above beneficial effects, this embodiment is explained as follows: Figure 1 In the layout structure design shown, the total number of gates of the two transistors is 8 rows. As the aspect ratio of the transistor increases, the 8-row design cannot be continued due to the limitation of process capability. Under the extreme compression of process, transistor volume and space size, only 7 rows of gates can be set in the same layout space, which leads to uneven distribution of the number of gates of the upper and lower transistors. In this embodiment, the two transistors are arranged horizontally instead of vertically. In the same layout space, since there is no upper and lower structure between the two transistors, the problem of uneven distribution of the number of gates of the two transistors can be fundamentally avoided. The number of gates of each transistor can be an odd number of rows, for example Figure 4 7 lines shown. Figure 1The structure shown in the figure shows that the present solution can reduce the number of gates of the transistor in the first direction, thereby reducing the space occupied by the transistor, which is conducive to the realization of a narrower frame. It should be noted that although the present solution has two transistor structures in the second direction, their overall width is very small and does not occupy too much layout space. Compared with the reduced layout space in the first direction, the overall layout space of the present solution is actually reduced.

[0060] Optionally, continue to refer to Figure 4 , the gate 12 of the first output transistor T1 and the gate 22 of the second output transistor T2 are arranged in the same layer, which is beneficial to reducing the overall film thickness of the display panel. The gate 12 of the first output transistor T1 includes a first routing portion 121 extending along the first direction and a second routing portion 122 extending along the second direction, and the second routing portion 122 overlaps with the active layer 11 of the first output transistor T1. The second routing portion 122 overlaps with the orthographic projection of the active layer 11 of the first output transistor T1 on the substrate. The orthographic projection of the first routing portion 121 on the substrate may be located outside the orthographic projection of the active layer 11 of the first output transistor T1 on the substrate, that is, not overlapping. The first routing portion 121 may be located on the side of the second routing portion 122 away from the second output transistor T2. The active layer 11 of the first output transistor T1 overlaps with the second wiring portion 122 to form a channel layer of the first output transistor T1. The second wiring portion 122 has multiple rows, and each row of the second wiring portion 122 is connected to the first wiring portion 121 to form a whole, so as to form a first output transistor T1 with a larger channel width-to-length ratio. The multiple second wiring portions 122 are arranged at intervals along the first direction.

[0061] The gate of the second output transistor T2 includes a third routing portion 221 extending along the first direction and a fourth routing portion 222 extending along the second direction, and the fourth routing portion 222 overlaps with the active layer 21 of the second output transistor T2. The fourth routing portion 222 overlaps with the orthographic projection of the active layer 21 of the second output transistor T2 on the substrate. The orthographic projection of the third routing portion 221 on the substrate may be located outside the orthographic projection of the active layer 21 of the second output transistor T2 on the substrate, that is, not overlapping. The third routing portion 221 may be located on the side of the fourth routing portion 222 away from the first output transistor T1. The overlapping position of the active layer 21 of the second output transistor T2 and the fourth routing portion 222 forms the channel layer of the second output transistor T2. The fourth routing portion 222 is also provided with multiple rows, and the multiple rows of fourth routing portions 222 are arranged at intervals along the first direction. Each row of the fourth routing portion 222 is connected to the third routing portion 221 to form a whole, so that a second output transistor T2 with a larger channel width-to-length ratio can be formed. The third wiring portion 221 is located on the side of the fourth wiring portion 222 away from the first wiring portion 121, that is, the gate connection line 23 (extending along the second direction) of the second output transistor T2 must bypass the active layer 11 of the first output transistor T1 and connect to the third wiring portion 221 extending in the first direction, so as to avoid electrical connection between the gate 12 of the first output transistor T1 and the gate 22 of the second output transistor T2. The second wiring portion 122 and the fourth wiring portion 222 are arranged at intervals and do not contact each other, so that the channel of the first output transistor T1 and the channel of the second output transistor T2 are disconnected.

[0062] The second electrode of the first output transistor T1 is connected to the second electrode of the second output transistor T2 via the third switching line 303 , wherein the third switching line 303 connects the second electrode of the first output transistor T1 and the second electrode of the second output transistor T2 in a via manner.

[0063] Due to the limitation of process limit compression, the overall number of gates in the first direction cannot be designed according to the conventional even-numbered rows. Therefore, in this embodiment, the number of the second routing portion 122 and the fourth routing portion 222 is equal, and both can be odd-numbered rows, and the second routing portion 122 and the fourth routing portion 222 are arranged along the second direction, which structurally avoids the problem of uneven distribution of the number of gates of the first output transistor T1 and the second output transistor T2, and at the same time can reduce the occupied area of ​​the transistors with odd-numbered gates, which is conducive to achieving a narrow frame.

[0064] Optionally, along the second direction, the length of the overlapping portion of the second wiring portion 122 and the active layer 11 of the first output transistor T1 is equal to the length of the overlapping portion of the fourth wiring portion 222 and the active layer 21 of the second output transistor T2, which can simplify the design difficulty and help ensure that the channel width-to-length ratio of the first output transistor T1 and the second output transistor T2 is the same, thereby ensuring the stability of the gate signal. Optionally, along the first direction, the second wiring portion 122 and the fourth wiring portion 222 are equal in size.

[0065] Figure 5 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention, referring to Figure 5 On the basis of the above technical solution, optionally, the display panel 100 further includes preset signal lines extending along the first direction, the preset signal lines including a first preset signal line 31 and a second preset signal line 32; the first preset signal line 31 is connected to the first electrode of the first output transistor T1 through the first adapter line 301, the second electrode of the first output transistor T2 is connected to the output end out of the shift register 10, and the first output transistor T1 is used to transmit the voltage on the first potential signal line 31 to the output end out of the shift register 10 when it is turned on; the first electrode of the second output transistor T2 is connected to the second preset signal line 32 through the second adapter line 302, the second electrode of the second output transistor T2 is connected to the output end out of the shift register 10, and the second output transistor T2 is used to transmit the voltage on the second preset signal line 32 to the output end out of the shift register 10 when it is turned on.

[0066] Among them, optionally, there are multiple first transfer lines 301, multiple third transfer lines 303, and the first transfer lines 301, the third transfer lines 303, and the second routing portion 122 are alternately arranged along the first direction. Optionally, there are multiple second transfer lines 302, and the second transfer lines 302, the third transfer lines 303, and the fourth routing portion 222 are alternately arranged along the first direction. Optionally, the third transfer line 303 overlaps and is connected to the active layer 11 of the first output transistor T1 and the active layer 21 of the second output transistor T2 on two opposite sides along the second direction (for example, they can be connected through vias).

[0067] Specifically, one of the first preset signal line 31 and the second preset signal line 32 is a high potential signal line, and the other is a low potential signal line. Figure 3In the shift register 10 shown, the first preset signal line 31 can be used to transmit a first potential signal VGH (for example, a high potential signal), and the second preset signal line 32 can be used to transmit a second potential signal VGL (for example, a low potential signal). The first output transistor T1 is used to transmit the first potential signal VGH to the output end out of the shift register 10 when it is turned on, and the second output transistor T2 is used to transmit the second potential signal VGL to the output end out of the shift register 10 when it is turned on, thereby forming a gate signal output. The gate signal can be a scanning signal or a light emitting control signal.

[0068] Of course, in other embodiments, one of the first preset signal line 31 and the second preset signal line 32 can also be a fixed potential signal line, and the other can be a clock signal line. For example, the first preset signal line 31 can be used to transmit a fixed potential signal line (e.g., a first potential signal VGH), and the second preset signal line 32 can be used to transmit a clock signal. The first output transistor T1 is used to transmit the first potential signal VGH to the output end out of the shift register 10 when it is turned on, and the second output transistor T2 is used to transmit the level corresponding to the clock signal to the output end out of the shift register 10 when it is turned on, thereby forming a gate signal output.

[0069] Continue to refer Figure 5 , optionally, the third routing portion 221 overlaps with the third transfer line 303 connected to the second pole of the second output transistor T2 (it can be that the third routing portion 221 and the third transfer line 303 overlap in the orthographic projection on the substrate, and the different layers are insulated) to form a first capacitor C1. Among them, the third routing portion 221 and the third transfer line 303 are arranged in different layers, the third routing portion 221 is the lower plate of the first capacitor C1, and the third transfer line 303 is the upper plate of the first capacitor C1. In other words, through the lateral layout, the first capacitor C1 can be formed between the gate 22 of the second output transistor T2 and the second pole to improve the stability of the output signal of the output terminal out of the shift register 10. Compared with the related technical solution, this solution can directly adopt the existing film layer structure to realize the layout of the first capacitor C1 without adding other film layers.

[0070] Continue to refer Figure 5 Optionally, the display panel 100 further includes an output signal line 40, and the output signal line 40 has the same extension direction as the second preset signal line 32; the output signal line 40 is connected to a third adapter line 303 connected to the second electrode of the second output transistor through a via hole, thereby connecting the second electrode of the first output transistor T1 and the second electrode of the second output transistor T2 together to form an output terminal out of the shift register 10, and the output signal line 40 is also connected to the gate signal line 20 (such as Figure 2As shown) is connected to transmit the gate signal output by the shift register 10 to the pixel circuit through the gate signal line 20.

[0071] Figure 6 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention may be specifically Figure 5 The cross-sectional view of the display panel cut along the section line BB' is combined with Figure 5 and Figure 6 On the basis of the above technical solutions, optionally, the display panel 100 further includes a substrate 101 and a plurality of conductive layers stacked in layers, and the active layer 11 of the first output transistor T1 and the active layer 21 of the second output transistor T2 are arranged in the same layer and are both located on one side of the substrate 101. The material of the substrate 101 can provide buffering, protection or support for the display panel. The material of the active layer can include P-Si and / or metal oxide semiconductor. The conductive layer includes a metal layer, and the following description takes the metal layer as an example.

[0072] The conductive layer is located on the side of the active layer 11 of the first output transistor T1 away from the substrate 101. The multi-layer conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer, and an insulating layer is provided between each conductive layer. The gate 12 of the first output transistor T1 and the gate 22 of the second output transistor T2 are located in the first conductive layer, the first preset signal line 31, the second preset signal line 32, the first transfer line 301, the second transfer line 302 and the third transfer line 303 are located in the second conductive layer, and the output signal line 40 is located in the third conductive layer. Figure 6 In the structure, the drain region or source region of the active layer 11 of the first output transistor T1 is connected through corresponding adapters (i.e., the first adapter 301 and the third adapter 303) to form the first electrode or the second electrode of the first output transistor T1; the drain region or source region of the active layer 21 of the second output transistor T2 is connected through corresponding adapters (i.e., the second adapter 302 and the third adapter 303) to form the first electrode or the second electrode of the second output transistor T2, and the second electrode of the second output transistor T2 is connected to the second electrode of the first output transistor T1 through the third adapter 303. The first conductive layer, the second conductive layer and the third conductive layer may be metal layers. An insulating layer may be provided between the first conductive layer, the second conductive layer and the third conductive layer.

[0073] The third routing portion 221 of the second output transistor T2 and the third adapter line 303 overlap each other at the position where the orthographic projections on the substrate overlap each other to form a first capacitor C1, and the third routing portion 221 is located at the first conductive layer as the lower plate of the first capacitor C1, and the third adapter line 303 is located at the second conductive layer as the upper plate of the first capacitor C1. In addition, the first routing portion 121 of the first output transistor T1 and the first potential signal line 31 overlap each other at the position where the projections overlap each other (the first routing portion 121 and the first potential signal line 31 overlap in the orthographic projections on the substrate, and are insulated in different layers) can form a second capacitor C2, and the first routing portion 121 is located at the first conductive layer as the lower plate of the second capacitor C2, and the first potential signal line 31 is located at the second conductive layer as the upper plate of the second capacitor C2. Wherein, the second capacitor C2 is connected between the gate and the second pole of the first output transistor T1.

[0074] In this embodiment, along the thickness direction of the display panel, the vertical projection of the output signal line 40 on the substrate 101 is located between the vertical projection of the third wiring portion 221 on the substrate 10 and the vertical projection of the second preset signal line 32 on the substrate 10, and there is a gap between the vertical projections of the output signal line 40, the third wiring portion 221 and the second preset signal line 32 on the substrate 10, and they do not overlap each other. Such a layout is conducive to reducing the overlap between the film layers, thereby reducing the parasitic capacitance, and is conducive to improving the stability of the gate signal.

[0075] Figure 7 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention, Figure 8 A schematic diagram of another display panel layout structure provided by an embodiment of the present invention, referring to Figure 7 and Figure 8 On the basis of the above technical solutions, optionally, the display panel 100 further includes a clock signal line, and the clock signal line, the potential signal line and the output signal line 40 extend in the same direction; wherein the clock signal line includes a first clock signal line 51 and a second clock signal line 52. The first clock signal line 51 and the second clock signal line 52 may both be located on the side of the first preset signal line 31 away from the display area AA. The first clock signal line 51 and the second clock signal line 52 may both be located on the side of the control module 110 away from the first preset signal line 31. The first clock signal line 51 is used to transmit the first clock signal SCK1 to the corresponding transistor in the shift register 10, and the second clock signal 52 is used to transmit the second clock signal SCK2 to the corresponding transistor in the shift register 10. The first clock signal line 51 and the second clock signal line 52 are both located in the second conductive layer, and are arranged on the same layer as the first preset signal line 31. The periods of the first clock signal SCK1 and the second clock signal SCK2 may be the same, and the phases may be opposite.

[0076] Exemplarily, one of the first preset signal line 31 and the second preset signal line 32 is a high potential signal line, and the other is a low potential signal line. The control module 110 of the shift register 10 may include a first input transistor T3, a second input transistor T4, a first control transistor T5, a second control transistor T6, a third control transistor T7, a fourth control transistor T8 and a fifth control transistor T9; the first electrode of the first input transistor T3 is connected to the third preset signal line 32' (for example, a low potential signal VGL can be transmitted), the second electrode of the first input transistor T3 is connected to the gate of the first control transistor T5, the first electrode of the first control transistor T5 is connected to the second clock signal line 52, the second electrode of the first control transistor T5 is connected to the first electrode of the second control transistor T6, the second electrode of the second control transistor T6 is connected to the gate of the first output transistor T1, the gate of the first input transistor T3 is connected to the first clock signal line 51, and the gate of the second control transistor T6 is connected to the second clock signal line 52; the first electrode of the second input transistor T4 is connected to the gate of the shift register The input terminal IN of the device 10 (for receiving the trigger signal), the second electrode of the second input transistor T4 is connected to the gate of the second output transistor T2, and the gate of the second input transistor T4 is connected to the first clock signal line 51; the first electrode of the third control transistor T7 is connected to the first clock signal line 51, the second electrode of the third control transistor T7 is connected to the second electrode of the first input transistor T3, and the gate of the third control transistor T7 is connected to the second electrode of the second input transistor T4; the first electrode of the fourth control transistor T8 is connected to the first preset signal line 31 (for example, a high potential signal VGH can be transmitted), the second electrode of the fourth control transistor T8 is connected to the first electrode of the fifth control transistor T9, the second electrode of the fifth control transistor T9 is connected to the second clock signal line 52, the gate of the fourth control transistor T8 is connected to the second electrode of the first input transistor T3, and the gate of the fifth control transistor T9 is connected to the gate of the second output transistor T2. A third capacitor C3 is connected between the gate of the fifth control transistor T9 and the second electrode of the fourth control transistor T8. The potentials of the second preset signal line 32 and the third preset signal line 32' can be the same, or, they are the same signal line. The second preset signal line 32 and the third preset signal line 32' may be different signal lines, and the third preset signal line 32' may be located at a side of the control module 110 away from the first output transistor T1. The third preset signal line 32' and the first preset signal line 31 are located at two opposite sides of the control module 110 along the second direction.

[0077] Fig. 9 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 8 and Fig. 9The control module further includes a reset signal line 61, which is arranged at the same layer as the clock signal line and is used to transmit a reset signal RST to the corresponding transistor. For example, the control module further includes a reset transistor T13, a gate of the reset transistor T13 is connected to the reset signal line 61, a first electrode of the reset transistor T13 is connected to the first preset signal line 31, and a second electrode of the reset transistor T13 is connected to the second electrode of the second input transistor T4.

[0078] Alternatively, if Fig. 9 As shown, the control module 110 further includes a fourth capacitor C4, and the fourth capacitor C4 is connected between the second electrode and the gate of the first control transistor T5.

[0079] Alternatively, if Fig. 9 As shown, the control module 110 also includes a sixth control transistor T12, a gate of the sixth control transistor T12 is connected to the second electrode of the second input transistor T4, a first electrode of the sixth control transistor T12 is connected to the first preset signal line 31, and a second electrode of the sixth control transistor T12 is connected to the gate of the first output transistor T1.

[0080] Alternatively, if Fig. 9 As shown, the control module 110 further includes a first protection transistor T10 and a second protection transistor T11, the gate of the first protection transistor T10 is connected to the third preset signal line 32', the first electrode of the first protection transistor T10 is connected to the second electrode of the first input transistor T3, and the second electrode of the first protection transistor T10 is connected to the gate of the first control transistor T5. The gate of the second protection transistor T11 is connected to the third preset signal line 32', the first electrode of the second protection transistor T11 is connected to the second electrode of the second input transistor T4, and the second electrode of the second protection transistor T11 is connected to the gate of the second output transistor T2.

[0081] in, Fig. 9 The middle shift register 10 may be an EM circuit with a 13T4C structure. The specific working principle thereof may refer to the relevant description in the prior art, which will not be described in detail here. Fig. 9 The transistors in the shift register 10 are shown as P-type transistors by way of example. The transistors may also be N-type transistors, which can be configured as required.

[0082] The above embodiment only schematically illustrates a structure of the shift register 10. In another embodiment of the present invention, one of the first preset signal line 31 and the second preset signal line 32 can also be a fixed potential signal line, and the other is a clock signal line. For example, the first preset signal line 31 is a first potential signal line (for example, it can transmit a high potential signal VGH), and the second preset signal line 32 is a second clock signal line (for example, it can transmit a second clock signal SCK2). Fig.10 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig.10 The control module 110 of the shift register 10 may include a first input transistor T3, a second input transistor T4, a third control transistor T7, a fourth control transistor T8, a fifth control transistor T9 and a second protection transistor T11. The first electrode of the first input transistor T3 is connected to the first preset signal line 31 (for example, a high potential signal VGH can be transmitted), the second electrode of the first input transistor is connected to the second electrode of the second input transistor T4 via the third control transistor T7, the first electrode of the second input transistor T4 is the input terminal IN of the shift register 10 (for receiving a trigger signal), the gate of the third control transistor T7 is connected to the third preset signal line (wherein the third preset signal line may be the same as the signal of the second preset signal line 32, or, is the second preset signal line), the gate of the second input transistor T4 is connected to the first clock signal line; the first electrode of the fourth control transistor T8 is connected to the second potential signal line (for example, a low potential signal VGL can be transmitted), the second electrode of the fourth control transistor T8 is connected to the gate of the first output transistor T1, and the gate of the fourth control transistor T8 is connected to the first clock signal line. The first electrode of the fifth control transistor T9 is connected to the first clock signal line, the second electrode of the fifth control transistor T9 is connected to the gate of the first output transistor T1, and the gate of the fifth control transistor T9 is connected to the second electrode of the second input transistor T4; the gate of the second protection transistor T11 is connected to the second potential signal line (for example, it can transmit the low potential signal VGL), the first electrode of the second protection transistor T11 is connected to the second electrode of the second input transistor T4, and the second electrode of the second protection transistor T11 is connected to the gate of the second output transistor T2. The shift register is a scan circuit of 8T2C structure, and the layout of the first output transistor T1 and the second output transistor T2 is the same as the technical solution provided in the above embodiment. The specific working principle can refer to the description in the relevant prior art and will not be repeated. Fig.10 The transistors in the shift register 10 are shown as P-type transistors by way of example. The transistors may also be N-type transistors, which can be configured as required.

[0083] Optionally, an embodiment of the present invention further provides a display device, Fig.11 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. The display device may be a mobile phone, a computer, a tablet computer, a smart wearable device, or other electronic devices with a display function. Fig.11 The display device provided by the embodiment of the present invention includes the display panel provided by any of the above embodiments of the present invention, and thus has the corresponding structure and beneficial effects of the display panel, which will not be described in detail here.

[0084] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0085] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: A plurality of shift registers are arranged and cascaded along a first direction, wherein the shift register comprises a first output transistor and a second output transistor, wherein the first output transistor and the second output transistor are both connected to an output end of the shift register; The first output transistor and the second output transistor are arranged along a second direction, wherein the first direction and the second direction intersect and are both perpendicular to a thickness direction of the display panel; Also included are preset signal lines extending along the first direction, the preset signal lines including a first preset signal line and a second preset signal line; The first preset signal line is connected to the first electrode of the first output transistor through a first adapter line, the second electrode of the first output transistor is connected to the output end of the shift register, and the first output transistor is used to transmit the voltage on the first preset signal line to the output end of the shift register when it is turned on; The first electrode of the second output transistor is connected to the second preset signal line through a second adapter line, the second electrode of the second output transistor is connected to the output end of the shift register, and the second output transistor is used to transmit the voltage on the second preset signal line to the output end of the shift register when it is turned on; The second electrode of the first output transistor is connected to the second electrode of the second output transistor through a third switching line.

2. The display panel according to claim 1, characterized in that: The active layer of the first output transistor and the active layer of the second output transistor are arranged along a second direction; The gate connection line of the second output transistor bypasses the active layer of the first output transistor and is connected to the gate of the second output transistor.

3. The display panel according to claim 1, characterized in that: The gate of the first output transistor includes a first wiring portion extending along a first direction and a second wiring portion extending along a second direction, wherein the second wiring portion overlaps with the active layer of the first output transistor; The gate of the second output transistor includes a third wiring portion extending along the first direction and a fourth wiring portion extending along the second direction, and the fourth wiring portion overlaps the active layer of the second output transistor; The third routing portion is located at a side of the fourth routing portion away from the first routing portion, and the second routing portion and the fourth routing portion are spaced apart.

4. The display panel according to claim 3, characterized in that: There are multiple second wiring portions in the gate of the first output transistor, and the multiple second wiring portions are arranged at intervals along the first direction; there are multiple fourth wiring portions in the gate of the second output transistor, and the multiple fourth wiring portions are arranged at intervals along the first direction.

5. The display panel according to claim 4, characterized in that: The number of the second routing portions is equal to the number of the fourth routing portions.

6. The display panel according to claim 5, characterized in that: The number of the second routing portions and the number of the fourth routing portions are both odd.

7. The display panel according to claim 3, characterized in that: The gate of the first output transistor and the gate of the second output transistor are arranged on the same layer.

8. The display panel according to claim 3, characterized in that: Along the second direction, a length of a portion where the second routing portion overlaps with an active layer of the first output transistor is equal to a length of a portion where the fourth routing portion overlaps with an active layer of the second output transistor.

9. The display panel according to claim 3, characterized in that: There are a plurality of first adapter wires, there are a plurality of third adapter wires, and the first adapter wires, the third adapter wires, and the second routing parts are alternately arranged along the first direction; There are a plurality of second adapter wires, and the second adapter wires, the third adapter wires, and the fourth routing portion are alternately arranged along the first direction; Two opposite sides of the third switching line along the second direction overlap and are connected to the active layer of the first output transistor and the active layer of the second output transistor respectively.

10. The display panel according to claim 9, characterized in that: One of the first preset signal line and the second preset signal line is a high potential signal line, and the other is a low potential signal line; or one of the first preset signal line and the second preset signal line is a fixed potential signal line, and the other is a clock signal line.

11. The display panel according to claim 9, characterized in that: The third wiring portion overlaps with the third transfer line connected to the second electrode of the second output transistor to form a first capacitor.

12. The display panel according to claim 9, characterized in that: It also includes an output signal line, the output signal line and the second preset signal line extend in the same direction, and the output signal line is connected to the third switching line connected to the second electrode of the second output transistor through a via.

13. The display panel according to claim 12, characterized in that: The display panel further includes a pixel circuit and a gate signal line extending along a second direction, the pixel circuit is connected to the output signal line via the gate signal line, and the gate signal line is located on a side of the second output transistor away from the first output transistor.

14. The display panel according to claim 13, characterized in that: The display panel further comprises a substrate and a plurality of conductive layers stacked in layers, wherein the active layer of the first output transistor and the active layer of the second output transistor are arranged in the same layer and are both located on one side of the substrate; The multi-layer conductive layer comprises a first conductive layer, a second conductive layer and a third conductive layer, the gate of the first output transistor and the gate of the second output transistor are located in the first conductive layer, the preset signal line and the switching line are located in the second conductive layer, and the output signal line is located in the third conductive layer; Among them, along the thickness direction of the display panel, the vertical projection of the output signal line on the substrate is located between the vertical projection of the third routing portion on the substrate and the vertical projection of the second preset signal line on the substrate, and there is a gap between the vertical projections of the output signal line, the third routing portion and the second preset signal line on the substrate.

15. The display panel according to claim 14, characterized in that: One of the first preset signal line and the second preset signal line is a high potential signal line, and the other is a low potential signal line; The shift register further includes a first input transistor, a second input transistor, a first control transistor, a second control transistor, a third control transistor, a fourth control transistor and a fifth control transistor; The first electrode of the first input transistor is connected to the third preset signal line, the second electrode of the first input transistor is connected to the gate of the first control transistor, the first electrode of the first control transistor is connected to the second clock signal line, the second electrode of the first control transistor is connected to the first electrode of the second control transistor, the second electrode of the second control transistor is connected to the gate of the first output transistor, the gate of the first input transistor is connected to the first clock signal line, and the gate of the second control transistor is connected to the second clock signal line; The first electrode of the second input transistor is the trigger signal input terminal of the shift register, the second electrode of the second input transistor is connected to the gate of the second output transistor, and the gate of the second input transistor is connected to the first clock signal line; the first electrode of the third control transistor is connected to the first clock signal line, the second electrode of the third control transistor is connected to the second electrode of the first input transistor, and the gate of the third control transistor is connected to the second electrode of the second input transistor; the first electrode of the fourth control transistor is connected to the first preset signal line, the second electrode of the fourth control transistor is connected to the first electrode of the fifth control transistor, the second electrode of the fifth control transistor is connected to the second clock signal line, the gate of the fourth control transistor is connected to the second electrode of the first input transistor, and the gate of the fifth control transistor is connected to the gate of the second output transistor; The second preset signal line and the third preset signal line have the same potential.

16. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-15.

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