A chip detection method and control device and storage medium thereof

Abstract

The present invention provides a chip detection method, comprising the following steps: obtaining the distribution of the optoelectronic properties of the epitaxial wafer of the semiconductor; checking the appearance of the epitaxial wafer, marking the defective area, and generating the appearance data of the epitaxial wafer; completing the production of the chip on the epitaxial wafer; obtaining the optoelectronic data of the sampled chip; checking the appearance of the chip, marking the defective area, and generating the appearance data of the chip; merging the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip, marking the area with the epitaxial wafer defect, the chip appearance defect, and the chip optoelectronic sampling poor, and not assigning a value; obtaining the optoelectronic performance distribution map of the sampled chip on the wafer, and assigning a value to the chip whose optoelectronic property is not sampled in combination with the AI ​​algorithm; closing the file after the assignment, and obtaining all the optoelectronic performance parameters of the chip on the wafer. In the present invention, by integrating the AI ​​algorithm, the test efficiency of the test system is improved in a breakthrough way, and the test problem is solved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing method and a control device and a storage medium thereof. Background Art

[0002] In recent years, with the continuous attention and investment of the industry chain and the accelerated layout of terminal manufacturers, Mini / Micro LED terminal products have continued to emerge and gradually opened up a broad application space. MiniLED products in the field of micro-pitch outdoor / indoor full-color direct display and LCD backlight applications are relatively mature and have entered a period of rapid growth; MicroLED display is popular in the industry and is unanimously regarded as the best solution for AR and VR display after entering the metaverse era.

[0003] However, in the LED front-end process, complex processing steps such as cleaning, evaporation, yellow light, and chemical etching will inevitably cause defects in the chip. For example, during the evaporation process, the chip will have clip marks due to the use of spring clips to fix it; during the yellow light operation, if the development is incomplete or there are holes in the mask, there will be residual metal in the chip's light-emitting area. Therefore, the quality of the LED chip directly determines the performance of the LED.

[0004] The LED chip detection system is one of the key steps in LED production. It can well realize production automation, effectively classify chips, and provide indispensable information for the next step of process production, saving a lot of time, manpower and material resources, and improving detection accuracy.

[0005] Therefore, after the LED chip is manufactured, in order to obtain the optoelectronic performance parameters (VF, WLD, Lop, IR, etc.) of each chip, so that the chips on the wafer can be classified by performance level according to different customer needs. Prober equipment will be used to power on each chip on the wafer to obtain its performance parameters. It is understandable that the optoelectronic performance parameters that need to be tested for each chip and the test time (cycle time) of each parameter are basically the same. The smaller the chip size, the longer the time it takes to test a single wafer. The cost (time, manpower, equipment) of testing mini / microLED chips has increased exponentially, and the output efficiency has been greatly reduced. For the three mainstream sizes of MiniLED chips, 6mil×20mil, 5mil×8mil, and 3mil×5mil, the cumulative time for multiple parameter tests of a single chip by an 8-probe test module is 80ms; the test time for a single wafer of a 3mil×5mil miniLED chip is close to 5 hours. It can be seen from this that the existing testing methods occupy a large amount of testing resources and have low production efficiency. Summary of the invention

[0006] The main purpose of the present invention is to provide a chip detection method and its control device and storage medium, aiming to improve the technical problems in the prior art of extremely large occupation of test resources and low production efficiency.

[0007] To achieve the above object, the present invention provides a chip detection method, comprising the following steps:

[0008] Obtaining the distribution of optoelectronic properties of semiconductor epitaxial wafers;

[0009] Inspecting the appearance of the epitaxial wafer, marking defective areas, and generating appearance data of the epitaxial wafer;

[0010] Finishing the production of chips on the epitaxial wafer;

[0011] Obtaining photoelectric data of the sampled chip;

[0012] Inspecting the appearance of the chip, marking defective areas, and generating appearance data of the chip;

[0013] The appearance data of the epitaxial wafer, the optoelectronic data of the chip and the appearance data of the chip are combined, and the areas with epitaxial wafer defects, chip appearance defects and poor optoelectronic sampling of the chip are marked without assigning values;

[0014] Obtain a map of the distribution of the optoelectronic properties of the chips sampled on the wafer, and assign values ​​to the chips whose optoelectronic properties have not been sampled in combination with an AI algorithm;

[0015] After the values ​​are assigned, the files are merged to obtain all the optoelectronic performance parameters of the chips on the wafer.

[0016] Optionally, the steps of inspecting the appearance of the epitaxial wafer, marking defective areas, and generating appearance data of the epitaxial wafer include:

[0017] Establish the starting point and coordinate system, and mark the coordinate values ​​of all chips;

[0018] Establish standard graphics files for single chips;

[0019] Perform a global scan of the chips on the wafer to obtain the appearance of the epitaxial material growth and generate a scanned image;

[0020] Compare the scanned image with the template in the standard image file to obtain the position coordinates of the abnormal points, locate the abnormal points and mark the defective areas.

[0021] Optionally, the step of obtaining the optoelectronic data of the sampled chip includes:

[0022] Obtain the optoelectronic performance parameters of the chip at the specified coordinate position according to the set ratio;

[0023] The photoelectric performance parameters of the chip are input into a pre-set table template to generate the photoelectric data of the chip.

[0024] Optionally, the step of merging the appearance data of the epitaxial wafer, the optoelectronic data of the chip and the appearance data of the chip, marking areas with epitaxial wafer defects, chip appearance defects and poor optoelectronic sampling of the chip, and not assigning values ​​comprises:

[0025] Generate a map with different color levels according to the distribution of the optoelectronic characteristics of the epitaxial wafer, the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip;

[0026] The maps displayed in different color levels are superimposed and matched, and the chip corresponding to the mark point in the defective area is marked as abnormal and no value is assigned.

[0027] Optionally, the step of assigning a value to the chip whose photoelectric properties have not been sampled in combination with an AI algorithm includes:

[0028] Obtaining the optoelectronic performance parameters A1 (x, y) and A2 (x, y+n) of the two test chips located in the same row;

[0029] Performing a primary assignment on the chip adjacent to the sampled chip to obtain the optoelectronic performance parameter of the chip adjacent to the sampled chip as B(x, y);

[0030] A second-level assignment is performed on the chip adjacent to the chip with the first-level assignment, so as to obtain the optoelectronic performance parameter of the chip adjacent to the chip with the first-level assignment as C(x, y).

[0031] Optionally, the step of performing primary assignment on the chip adjacent to the sampled chip to obtain the optoelectronic performance parameter of the chip adjacent to the sampled chip as B(x, y) satisfies the following relationship:

[0032] B(x,y+1)=0.67A(x,y)+0.33A(x,y+n)

[0033] Optionally, the step of performing secondary assignment on the chip adjacent to the primary assigned chip to obtain the optoelectronic performance parameter of the chip adjacent to the primary assigned chip as C(x, y) satisfies the following relationship:

[0034] C(x+1,y+1)=0.5B(x,y+1)+0.5B(x+1,y)

[0035] In addition, to achieve the above-mentioned purpose, the present invention also proposes a chip detection device, including a storage device, a processor, and a chip detection program stored on the storage device and executable on the processor, wherein the chip detection program is configured to implement the steps of the chip detection method as described above.

[0036] In addition, to achieve the above-mentioned purpose, the present invention also proposes a storage medium, on which a chip detection program is stored, and when the chip detection program is executed by a processor, the steps of the chip detection method described above are implemented.

[0037] In the technical solution provided by the present invention, the following steps are included: obtaining the distribution of the optoelectronic properties of the epitaxial wafer of the semiconductor; checking the appearance of the epitaxial wafer, marking the defective area, and generating the appearance data of the epitaxial wafer; completing the production of the chip on the epitaxial wafer; obtaining the optoelectronic data of the sampled chip; checking the appearance of the chip, marking the defective area, and generating the appearance data of the chip; merging the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip, marking the areas with epitaxial wafer defects, chip appearance defects, and poor chip optoelectronic sampling, and not assigning values; obtaining a map of the optoelectronic performance distribution of the sampled chips on the wafer, and assigning values ​​to the chips whose optoelectronic properties have not been sampled in combination with the AI ​​algorithm; closing the files after the assignment to obtain all the optoelectronic performance parameters of the chips on the wafer. In the present invention, by integrating the AI ​​algorithm, the test efficiency of the test system is improved in a breakthrough way, and the test problem is solved. The algorithm assignment method has the following advantages: improving the test efficiency of small-size chips; increasing the test accuracy by extending the cycle time of random testing and increasing the integrating sphere; and reducing the hardware cost investment for small-size chip testing by replacing hardware with software algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of a process flow of an embodiment of a chip detection method provided by the present invention;

[0040] Figure 2 A schematic diagram of a process flow of an embodiment of a chip detection method provided by the present invention;

[0041] Figure 3 and Figure 4 The chip-level wavelength distribution map of the wafer probe test results;

[0042] Figure 5 and Figure 6 Map of the wafer-level wavelength distribution of the test results of the PL test equipment;

[0043] Figure 7 It is a schematic diagram of the chip arrangement structure;

[0044] Figure 8 It is a schematic diagram of the structure of the horizontal arrangement of chips;

[0045] Fig. 9 It is a schematic diagram of the structure of a chip detection device in a hardware operating environment involved in an embodiment of the present invention.

[0046] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that if a directional indication is involved in the embodiment of the present invention, the directional indication is only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0049] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel solutions. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0050] It is understandable that the optoelectronic performance parameters that need to be tested for each chip and the test time (cycle time) for each parameter are basically the same. The smaller the chip size, the longer it takes to test a single wafer. The cost (time, manpower, equipment) of testing mini / microLED chips has doubled, and the output efficiency has been greatly reduced. For the three mainstream sizes of MiniLED chips, 6mil×20mil, 5mil×8mil, and 3mil×5mil, the cumulative time for multiple parameter tests of a single chip with an 8-probe test module is 80ms; the test time for a single wafer of a 3mil×5mil miniLED chip is close to 5 hours. It can be seen that the existing test methods occupy a large amount of test resources and have low production efficiency.

[0051] In view of this, the present application provides a chip detection method, which aims to solve the problem of low chip testing efficiency by integrating AI algorithms to improve the testing efficiency of the testing system and solve the testing problems that plague the industry.

[0052] See also Figure 1 , Figure 1 The schematic diagram of the process of an embodiment of the chip detection method of the present invention includes the following steps:

[0053] Step S10: Obtaining the distribution of the optoelectronic characteristics of the semiconductor epitaxial wafer.

[0054] Step S20: inspecting the appearance of the epitaxial wafer, marking defective areas, and generating appearance data of the epitaxial wafer.

[0055] Step S30: completing chip manufacturing on the epitaxial wafer.

[0056] Step S40: obtaining the photoelectric data of the randomly tested chip.

[0057] Step S50: Check the appearance of the chip, mark the defective area, and generate appearance data of the chip.

[0058] Step S60: Merge the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip, and mark the areas with epitaxial wafer defects, chip appearance defects, and poor chip optoelectronic sampling without assigning values.

[0059] Step S70: Obtain a map of the distribution of the optoelectronic properties of the chips sampled on the wafer, and assign values ​​to the chips whose optoelectronic properties have not been sampled using an AI algorithm.

[0060] Step S80: After the values ​​are assigned, the files are closed to obtain all the optoelectronic performance parameters of the chips on the wafer.

[0061] It can be understood that a wafer can also be called a wafer, which can refer to a silicon chip used to make silicon semiconductor circuits. Its original material is silicon. There can be multiple chips on the wafer, among which the multiple chips on the wafer can be called chip bare chips, and the chip bare chips are also called grain dies.

[0062] Electroluminescence / photoluminescence tester (i.e. PL testing equipment) can systematically describe the electroluminescence (EL) and photoluminescence (PL) properties of unprocessed luminescent materials, such as EL spectrum, LIV, output, slope quantum efficiency characteristics, wavelength and FWHM shift curve, wafer-level uniformity, emission intensity, peak / dominant wavelength (WLP / WLD), FWHM shift curve, driving voltage / current, etc., with non-destructive testing and fast measurement.

[0063] AOI (Automated Optical Inspection) is the full name of automatic optical inspection, which is a device based on optical principles to detect common defects encountered in semiconductor chip production. AOI is a new emerging testing technology. When automatically inspecting, the machine automatically scans the wafer through a camera, collects images and compares them with qualified parameters in the database, and checks the defects on the wafer through image processing. The defects are displayed / marked through a display or automatic mark for maintenance personnel to repair. High-speed and high-precision visual processing technology is used to automatically detect various defects on the wafer to improve production efficiency and production quality.

[0064] Wafer probe testing (Probe) is an important part of integrated circuit production. It is not only a way to save the cost of waste chip packaging, but now it has become a key factor in process control, yield management, product quality and reducing total testing costs. The purpose of wafer probe testing should be to obtain test results with a certain degree of credibility under reasonable cost control. The result of wafer probe testing is a map of yield and binning. Wafer probe testing (Probe) uses a probe test bench and a probe test card to test each die on the wafer to ensure that the electrical characteristics and performance of the die are manufactured according to the design specifications. Assignment is the process of assigning a value to a variable, which is called assignment.

[0065] In this embodiment, the distribution of the photoelectric characteristics of the optoelectronic semiconductor epitaxial wafer, such as wavelength, half-width, and intensity, is obtained by using a PL detection device. Then, an automatic optical inspection device is used to perform AOI inspection on the epitaxial wafer to check the appearance of the epitaxial wafer, mark defective areas such as fogging, pinholes, and particles, and generate appearance data of the epitaxial wafer.

[0066] Then the LED chip is produced on the epitaxial wafer. The production of LED chips includes but is not limited to the following process flow: epitaxial wafer → cleaning → plating of transparent electrode layer → transparent electrode pattern lithography → corrosion → degumming → platform pattern lithography → dry etching → degumming → annealing → SiO2 deposition → window pattern lithography → SiO2 corrosion → degumming → N-pole pattern lithography → pre-cleaning → coating → peeling → annealing → P-pole pattern lithography → coating → peeling → grinding → cutting → chip → finished product testing.

[0067] The probe sampling test obtains the optoelectronic data of the LED chip, such as the forward operating voltage (VF1), forward turn-on voltage (VF4), main wavelength (WLD), peak wavelength (WLP), half-width (HW), optical power (LOP), reverse leakage current (IR), reverse withstand voltage (VZ), etc. Then the appearance of the chip is checked by AOI, and defective areas such as scratches, missing patterns, damage, residual pollution, and residual gold are marked to generate the appearance data of the chip. The above data are combined and merged, and the areas with epitaxial wafer defects, chip appearance defects, and poor optoelectronic sampling are marked and not assigned values. Finally, the map of the optoelectronic performance distribution of LED chips on the wafer is obtained through PL testing and Prober optoelectronic sampling. The chips that have not been tested for optoelectronic properties are assigned values ​​through AI algorithms and combined with the distribution map. After the assignment is completed, the full test data file is synthesized, and all optoelectronic performance parameters of the chips on the wafer are obtained by combining the files.

[0068] See also Figure 2 Further, in this embodiment, step S20 includes the following steps:

[0069] Step S201: Establish a starting point and a coordinate system, and mark coordinate values ​​for all chips.

[0070] Step S202: Create a standard image file of a single chip.

[0071] Step S203: perform a global scan on the chips on the wafer to obtain the appearance of the epitaxial material growth and generate a scan image.

[0072] Step S204: Compare the scanned image with the template in the standard image file, obtain the position coordinates of the abnormal point, locate the abnormal point, and mark the defect area.

[0073] In this embodiment, before the wafer probe test (Probe), a global scan of the chips on the wafer is performed, and the coordinate values ​​of all chips are marked by setting the starting point (0,0), and a coordinate system is established; before scanning, a standard image file of a single chip is established, and the imaging system compares the scanned image with the template in the standard image file after scanning to obtain the position coordinates and locate the abnormal points.

[0074] Further, in this embodiment, step S40 includes the following steps:

[0075] Step S401: Obtaining the optoelectronic performance parameters of the chip at the specified coordinate position according to a set ratio.

[0076] Step S402: inputting the photoelectric performance parameters of the chip into a pre-set table template to generate the photoelectric performance data of the chip.

[0077] In this embodiment, after the wafer probe test (Probe) scans, a global map of the wafer will be generated. The machine will set the sampling interval (an integer multiple of the length and width of the chip) to perform optoelectronic performance tests on the chips at the specified coordinate positions. The test conditions (current size, voltage size, reverse parameters, etc.) are defined by themselves, and the sampling data is written into a pre-set table template to generate the optoelectronic data file of the chip.

[0078] Furthermore, in this embodiment, step S60 includes:

[0079] Step S601: Generate a map with different color levels according to the distribution of the optoelectronic characteristics of the epitaxial wafer, the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip.

[0080] Step S602: Maps displayed in different color levels are superimposed and matched, and the chip corresponding to the defect area mark point is marked as abnormal and no value is assigned.

[0081] See also Figure 3-Figure 6 In this embodiment, a Map displayed in different color scales is generated through PL inspection, Prober test, and AOI inspection. By superimposing and fitting the Map, the chip corresponding to the defect area mark point is marked as abnormal and no value is assigned. Taking the WLD parameter as an example, the color scale distribution of PLWLDMap is linearly related to the color scale distribution of WLDMap sampled by Prober. The PL long wave corresponds to the Prober long wave, the PL short wave corresponds to the Prober short wave, and the span (Range) △WLD of the distribution is basically equal. Taking the WLD parameter as an example, assuming that the difference between PLWLD-ProberWLD is 0.3nm, the color scale (PLWLD) corresponding to the chip position not sampled by Prober is found by referring to the Map color scale diagram of PLWLD, and the WLD of the untested chip is equal to PLWLD+0.3nm.

[0082] Further, in this embodiment, step S70 includes the following steps:

[0083] Step S701: Obtain the optoelectronic performance parameters A1 (x, y) and A2 (x, y+n) of the two test chips located in the same row.

[0084] Step S702: performing primary assignment on the chip adjacent to the chip under random test to obtain the optoelectronic performance parameter of the chip adjacent to the chip under random test as B(x, y).

[0085] Step S703: Perform secondary assignment on the chip adjacent to the chip assigned with primary assignment, so as to obtain the optoelectronic performance parameter of the chip adjacent to the chip assigned with primary assignment as C(x, y).

[0086] In this embodiment, the first-level assignment is an assignment based on the chip photoelectric property combination algorithm of the Prober sampling test, and the second-level assignment is an assignment based on the chip photoelectric property combination algorithm of the first-level assignment.

[0087] Furthermore, in step S702, the following relationship is satisfied: B(x, y+1)=0.67A(x, y)+0.33A(x, y+n). In step S703, the following relationship is satisfied: C(x+1, y+1)=0.5B(x, y+1)+0.5B(x+1, y).

[0088] It should be noted that A1(x, y) represents the coordinate position of the chip A1, x represents the horizontal coordinate, and y represents the vertical coordinate; similarly, the coordinate positions of the other chips mentioned above also follow the same rules, which will not be repeated here.

[0089] See also Figure 7 and Figure 8 Taking WLD parameters as an example, Chip1.1 (Prober sampling chip 1) WLD is 450nm, Chip1.2 (Prober sampling chip 2) is 450.6nm, Chip1.1→Chip1.2 shows a WLD red shift trend (wavelength becomes longer), Chip1.2-Chip1.1=0.6nm, there are two chips Chip2.1 and Chip2.3 in the middle, Chip2.1 and Chip2.3 are assigned values ​​according to the increasing trend, Chip2.1 WLD is 450.2nm, Chip2.3 WLD is 450.4nm.

[0090] In this embodiment, the weight of the assignment is determined based on the distance between the assigned chip and the assignment source chip sampled by the Prober. The smaller the distance between the assigned chip and the assignment source chip sampled by the Prober, the greater the weight. The weight is calculated according to the Pitch value.

[0091] Pitch is the unit horizontal spacing of chip arrangement. The spacing between the assigned source chips Chip1.1 and Chip1.2 of the probe sampling is 3×pitch, the spacing between the assigned chips Chip2.1 and Chip1.1 is 1×pitch, and the spacing between Chip2.1 and Chip1.2 is 2×pitch.

[0092] Chip2.1=Chip1.1*0.67(assignment weight 1)+Chip1.2*0.33(assignment weight 2).

[0093] Assign weight 1 = (3×pitch-1×pitch) / 3×pitch = 2 / 3.

[0094] Assign weight 1 = (3×pitch-2×pitch) / 3×pitch = 1 / 3.

[0095] Level 1 assignment: Chip2.1 = Chip1.1*0.67+Chip1.2*0.33. The assignment comes from two coaxial sampling chips. The assignment weight is determined by the distance between the assigned chip and the assigning chip. The larger the distance, the smaller the weight. The same applies to other level 1 assigned chips.

[0096] Second-level assignment: Chip3.1 = Chip2.1*0.5 + Chip2.2*0.5. The assignment comes from two adjacent chips with level 1 assignments, and the assignment weights are the same.

[0097] Reference Fig. 9 , Fig. 9 FIG. 1 is a schematic diagram of the structure of a chip detection device in a hardware operating environment according to an embodiment of the present invention. Figure 1 As shown, the chip detection device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The wired interface of the user interface 1003 may be a USB interface in the present invention. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (WIreless-FIdelity, WI-FI) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM) memory, or a stable memory (Non-volatile Memory, NVM), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0098] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the chip detection device, and may include more or less components than those shown in the figure, or combine certain components, or arrange the components differently.

[0099] like Fig. 9 As shown, the memory 1005 identified as a computer storage medium may include an operating system, a network communication module, a user interface module, and a control program of the mobile robot path control device.

[0100] exist Fig. 9 In the chip detection device shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the user equipment; the chip detection device calls the chip detection program stored in the memory 1005 through the processor 1001, and executes the chip detection method steps provided in the embodiment of the present invention.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory image (ReadOnlyMemoryimage, ROM) / random access memory (RandomAccessMemory, RAM), a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0102] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip detection method, characterized in that: The steps include: Obtaining the distribution of optoelectronic properties of semiconductor epitaxial wafers; Inspecting the appearance of the epitaxial wafer, marking defective areas, and generating appearance data of the epitaxial wafer; Finishing the production of chips on the epitaxial wafer; Obtaining photoelectric data of the sampled chip; Inspecting the appearance of the chip, marking defective areas, and generating appearance data of the chip; The appearance data of the epitaxial wafer, the optoelectronic data of the chip and the appearance data of the chip are combined, and the areas with epitaxial wafer defects, chip appearance defects and poor optoelectronic sampling of the chip are marked without assigning values; Obtain a map of the distribution of the optoelectronic properties of the chips sampled on the wafer, and assign values ​​to the chips whose optoelectronic properties have not been sampled in combination with an AI algorithm; After the values ​​are assigned, the files are combined to obtain all the optoelectronic performance parameters of the chips on the wafer; The step of merging the appearance data of the epitaxial wafer, the optoelectronic data of the chip and the appearance data of the chip, marking the areas with epitaxial wafer defects, chip appearance defects and poor optoelectronic sampling of the chip, and not assigning values ​​comprises: Generate a map with different color levels according to the distribution of the optoelectronic characteristics of the epitaxial wafer, the appearance data of the epitaxial wafer, the optoelectronic data of the chip, and the appearance data of the chip; The maps displayed in different color levels are superimposed and matched, and the chip corresponding to the mark point in the defective area is marked as abnormal and no value is assigned.

2. The chip detection method according to claim 1, characterized in that: The steps of inspecting the appearance of the epitaxial wafer and marking defective areas, and generating appearance data of the epitaxial wafer include: Establish the starting point and coordinate system, and mark the coordinate values ​​of all chips; Establish standard graphics files for single chips; Perform a global scan of the chips on the wafer to obtain the appearance of the epitaxial material growth and generate a scanned image; Compare the scanned image with the template in the standard image file to obtain the position coordinates of the abnormal points, locate the abnormal points and mark the defective areas.

3. The chip detection method according to claim 1, characterized in that: The step of obtaining the optoelectronic data of the sampled chip comprises: Obtain the optoelectronic performance parameters of the chip at the specified coordinate position according to the set ratio; The photoelectric performance parameters of the chip are input into a pre-set table template to generate the photoelectric data of the chip.

4. The chip detection method according to claim 1, characterized in that: The step of assigning a value to the chip whose photoelectric properties have not been sampled by combining the AI ​​algorithm includes: Obtain the optoelectronic performance parameters A1(x, y) and A2(x, y+n) of two test chips located in the same row; Performing a primary assignment on the chip adjacent to the sampled chip to obtain the optoelectronic performance parameter of the chip adjacent to the sampled chip as B(x, y); A second-level assignment is performed on the chip adjacent to the chip with the first-level assignment, so as to obtain the optoelectronic performance parameter of the chip adjacent to the chip with the first-level assignment as C(x, y).

5. The chip detection method according to claim 4, characterized in that: The step of performing primary assignment on the chip adjacent to the sampled chip to obtain the optoelectronic performance parameter of the chip adjacent to the sampled chip as B(x, y) satisfies the following relationship: B(x,y+1)=0.67A(x,y)+0.33A(x,y+n).

6. The chip detection method according to claim 4, characterized in that: The step of performing secondary assignment on the chip adjacent to the primary assigned chip to obtain the optoelectronic performance parameter of the chip adjacent to the primary assigned chip as C(x, y) satisfies the following relationship: C(x+1,y+1)=0.5B(x,y+1)+0.5B(x+1,y).

7. A chip detection device, characterized in that: It comprises a storage, a processor, and a chip detection program stored in the storage and running on the processor, wherein the chip detection program is configured to implement the steps of the chip detection method according to any one of claims 1 to 6.

8. A storage medium, characterized in that: The storage medium stores a chip detection program, which, when executed by a processor, implements the steps of the chip detection method according to any one of claims 1 to 6.

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