Test structure of semiconductor device, test structure layout and test method thereof

Abstract

The application provides a test structure of a semiconductor device, a test structure layout and a test method thereof. In the test structure, third sub-metal lines on the surface of a shared metal plug in the same row or column in the X direction and / or the Y direction are connected in series, then the ends of the connected multiple rows or columns of first sub-metal lines are connected in series as a first test chain (assuming M2 of odd rows or odd columns), then fourth sub-metal lines spaced apart from the third sub-metal lines in the same row or column in the X direction or the Y direction are connected in series by the same method (M2 of even rows or even columns relative to the first test chain) to form a second test chain, and then whether there is a current between the second layer metal lines of the odd rows and the second layer metal lines of the even rows by testing the first test chain and the second test chain, whether the metal layer M1 on the surface of the shared metal plug and the normal metal plug adjacent to the shared metal plug is short-circuited is determined.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a test structure, test structure layout and test method for a semiconductor device. Background Technology

[0002] In existing chip designs, SRAM, as a logic device, such as the F90 SRAM device, often shares a metal plug CT (referred to as a shared metal plug) with the source or drain of one MOSFET and the gate of another MOSFET in order to reduce the device size. Since the shared metal plug is longer than the normal metal plug, the metal layer M1 on the surface of the shared metal plug and the adjacent normal metal plug often short-circuit, which can cause the flash memory device to fail.

[0003] Therefore, in order to avoid the aforementioned flash memory device failure problem, finding a suitable shared metal plug and the size of metal layer M1 (or the nth metal line) has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a test structure, test structure layout and test method for semiconductor devices, so as to determine the optimal size by testing the test structure with shared metal plugs and metal lines of different sizes, and to quickly discover failure problems in semiconductor devices through the test structure.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a test structure for a semiconductor device, the test structure comprising:

[0006] A semiconductor substrate on which a device isolation structure is formed;

[0007] Multiple shared metal plugs are located on the device isolation structure, and each of the shared metal plugs is used as a conductive plug in an equivalent SRAM device to electrically connect the source or drain of one MOS transistor to the gate of another MOS transistor.

[0008] The first layer of metal wires includes multiple first sub-metal wires and multiple second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug and is electrically connected to the shared metal plug, while multiple second sub-metal wires are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the multiple first sub-metal wires.

[0009] The second layer of metal wires includes multiple third sub-metal wires and multiple fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire. The third sub-metal wires in the same row or column along the X or Y direction are connected in series to form a first test chain, and the fourth sub-metal wires in the same row or column along the X or Y direction are connected in series to form a second test chain.

[0010] Furthermore, the test structure may also include multiple through holes, which are specifically located in the intermetallic medium between the first metal layer and the second metal layer, for electrically connecting corresponding sub-metal lines between the first metal layer and the second metal layer, respectively.

[0011] Furthermore, the test structure may also include a first test pad electrically connected to the first test chain and a second test pad electrically connected to the second test chain.

[0012] Secondly, based on the same inventive concept as the test structure of the aforementioned semiconductor device, the present invention also provides a test structure layout for forming the test structure of the aforementioned semiconductor device. Specifically, the test structure layout provided by the present invention may include:

[0013] The first contact hole test layout may include a shared metal plug test pattern of multiple conductive plugs for electrically connecting the source or drain of one MOS transistor and the gate of another MOS transistor in an equivalent SRAM device.

[0014] The first metal test layout may include a plurality of first metal patterns and a plurality of second metal patterns arranged at intervals therebetween. The plurality of first metal patterns respectively cover the plurality of shared metal plug test patterns, and along the direction perpendicular to the test structure layout, the projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns respectively have partial or complete overlap.

[0015] The second contact hole test layout may include a plurality of second contact hole patterns, which correspond to a plurality of first metal patterns and a plurality of second metal patterns respectively.

[0016] The second metal test pattern may include a first test chain pattern and a second test chain pattern. The first test chain pattern may include multiple first sub-test chain patterns extending along the X or Y direction and all being in the shape of a straight strip. Each first sub-test chain pattern may include multiple third metal patterns that cover multiple second contact hole patterns in the same row or column along the X or Y direction. The second test chain pattern may include multiple second sub-test chain patterns extending along the X or Y direction and all being in the shape of a straight strip. Each second sub-test chain pattern includes multiple fourth metal patterns that cover multiple second contact hole patterns in the same row or column along the X or Y direction.

[0017] Furthermore, the plurality of third metal patterns and the plurality of fourth metal patterns are arranged at intervals, and one of the third metal patterns or one of the fourth metal patterns covers one of the second contact hole patterns.

[0018] Furthermore, the test structure layout may also include an isolation structure test layout, which may specifically include a shallow trench isolation structure pattern, and the shallow trench isolation structure pattern is located below the multiple shared metal plug test patterns.

[0019] Furthermore, the test structure layout may also include a pad test layout, which may include a first pad pattern and a second pad pattern, wherein the first pad pattern is located on the first test chain pattern and the second pad pattern is located on the second test chain pattern.

[0020] Thirdly, based on the same inventive concept as the test structure of the aforementioned semiconductor device, the present invention also provides a method for fabricating the test structure of the aforementioned semiconductor device using the test structure layout provided by the present invention, which specifically includes the following steps:

[0021] Provide a semiconductor substrate;

[0022] An isolation structure test layout is provided, and a device isolation structure is formed on the semiconductor substrate using the isolation structure test layout;

[0023] A first contact hole test layout is provided, and a plurality of shared metal plugs are formed on the device isolation structure through the first contact hole test layout;

[0024] A first metal test pattern is provided, and a first layer metal wire structure is formed by the first metal test pattern. The first layer metal wire structure includes a plurality of first sub-metal wires and a plurality of second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug and is electrically connected to the shared metal plug. The plurality of second sub-metal wires are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the plurality of first sub-metal wires.

[0025] A second contact hole test layout is provided, and a plurality of through holes are formed through the second contact hole test layout, wherein the plurality of through holes respectively cover a plurality of first sub-metal lines and a plurality of second sub-metal lines;

[0026] A second metal test pattern is provided, and a second layer metal wire structure is formed by the second metal test pattern. The second layer metal wire structure includes a plurality of third sub-metal wires and a plurality of fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire.

[0027] Fourthly, based on the same inventive concept as the test structure of the aforementioned semiconductor device, the present invention also provides a test method for testing the test structure of the aforementioned semiconductor device, which may specifically include the following steps:

[0028] Provide a test structure for the semiconductor device as described above;

[0029] Voltages are applied to the first test pad and the second test pad respectively, and the current between the first test chain and the second test chain is measured.

[0030] Fifthly, based on the same inventive concept as the test structure of the aforementioned semiconductor device, the present invention also provides a method for defect detection of the semiconductor device corresponding to the test structure of the aforementioned semiconductor device, which may specifically include the following steps:

[0031] Provide a test structure for the semiconductor device as described above;

[0032] Voltages are applied to the first test pad and the second test pad respectively, and the current between the first test chain and the second test chain is measured to determine whether the test structure has a shared metal plug and a short circuit between the second sub-metal line adjacent to the first sub-metal line that is electrically connected to it.

[0033] Furthermore, the step of determining whether the test structure has a shared metal plug and a short circuit between a second sub-metal wire adjacent to the first sub-metal wire electrically connected to it may include:

[0034] Determine whether the measured current between the first test chain and the second test chain is greater than zero. If not, determine that the test structure has a shared metal plug and a short circuit between the second sub-metal line adjacent to the first sub-metal line that is electrically connected to it.

[0035] Sixthly, based on the same inventive concept, the present invention also provides an electronic device, specifically including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0036] Memory, used to store computer programs;

[0037] When a processor executes a program stored in memory, it implements the test steps of the test method described above, or the defect detection method steps of the semiconductor device described above.

[0038] In a seventh aspect, based on the same inventive concept, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the test steps of the test method described above, or the defect detection method steps of the semiconductor device.

[0039] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0040] This invention provides a novel test structure for semiconductor devices. In this test structure, third sub-metal lines on the surface of a shared metal plug in the same row or column along the X and / or Y directions are connected in series. Then, the ends of the multiple rows or columns of third sub-metal lines are connected in series to form a first test chain (assuming it is M2 in an odd-numbered row or column). Then, using the same method, fourth sub-metal lines in the same row or column along the X or Y directions, spaced apart from the third sub-metal lines (which can also be understood as M2 used for electrical connection of the normal shared metal plug), are connected in series (M2 in an even-numbered row or column relative to the first test chain) to form a second test chain. Then, by testing the first test chain and the second test chain, that is, by testing whether there is current between the second layer metal lines in the odd-numbered rows and the second layer metal lines in the even-numbered rows, it can be determined whether the metal layer M1 on the surface of the shared metal plug and its adjacent normal metal plug is short-circuited.

[0041] Furthermore, since the test structure provided by the present invention can determine whether the metal layer M1 on the surface of the shared metal plug and its adjacent normal metal plug is short-circuited, by changing the size of the shared metal plug and the first layer of metal line in the test structure provided by the present invention, and then testing the test structure, the optimal size of the two can be determined, and the performance of the SRAM device can be monitored in real time, thereby ensuring the yield of the semiconductor device. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of a portion of the test layout in a test structure layout that includes the test structure of the semiconductor device provided by the present invention, provided in one embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of the complete test structure layout of all components of the test structure of the semiconductor device provided by the present invention, provided in one embodiment of the present invention.

[0044] Figure 3 This is a schematic flowchart illustrating the fabrication method of the test structure of a semiconductor device according to a specific embodiment of the present invention. Detailed Implementation

[0045] As described in the background section, in existing flash memory devices, such as the F90 SRAM device, to reduce device size, the source or drain of one MOS transistor in the memory cell and the gate of another MOS transistor often share a metal plug CT (referred to as a shared metal plug). Because the shared metal plug is longer than a normal metal plug, it often short-circuits with the metal layer M1 on the surface of its adjacent normal metal plug, leading to flash memory device failure. Therefore, to avoid such flash memory device failure, finding suitable dimensions for the shared metal plug and metal layer M1 (or the nth metal line) has become an urgent problem to be solved in this field.

[0046] To address this problem, the inventors of this invention first propose a special test structure. Specifically, third sub-metal wires formed on the surface of shared metal plugs in the same row or column along the X and / or Y directions are connected in series. Then, the ends of the multiple rows or columns of third sub-metal wires are connected in series as a first test chain (assumed to be M2 of odd-numbered rows or columns). Subsequently, using the same method, a fourth sub-metal wire (spaced apart from the third sub-metal wires in the same row or column along the X or Y direction, which can also be understood as M2 used for electrically connecting normal shared metal plugs) is connected. Metal wires are connected in series (M2 in even-numbered rows or columns relative to the first test chain) to form a second test chain. Then, voltage is applied to the first and second test chains in the unique test structure of this structure to detect whether there is current between the first and second test chains, i.e., between the second layer metal wires in odd-numbered rows and the second layer metal wires in even-numbered rows. This determines whether the metal layer M1 on the surface of the shared metal plug and its adjacent normal metal plug is short-circuited, thereby achieving the purpose of defect detection of semiconductor devices using the test structure provided by this invention.

[0047] Furthermore, by changing the dimensions of the shared metal plug and the first layer of metal lines in the test structure provided by this invention, and then testing the test structure, the optimal dimensions of the two can be determined, and the performance of the SRAM device can be monitored in real time, thereby ensuring the yield of the semiconductor device.

[0048] Therefore, the purpose of this invention is to provide a test structure, test structure layout and test method for semiconductor devices, so as to determine the optimal size by testing a test structure that can be configured with shared metal plugs and metal lines of different sizes, and to quickly discover failure problems in semiconductor devices through the test structure.

[0049] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the test structure, test structure layout, and test method for the semiconductor device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0050] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] The test structure layout provided by this invention will be described below. (See also...) Figures 1-3 ,in, Figure 1 A schematic diagram of a portion of the test layout in a test structure layout that includes the test structure of the semiconductor device provided by the present invention, provided in one embodiment of the present invention; Figure 2 This is a schematic diagram of the complete test structure layout of all components of the test structure of the semiconductor device provided by the present invention, provided in one embodiment of the present invention.

[0052] like Figures 1-2 As shown, the test structure layout provided by this invention may specifically include:

[0053] The first contact hole test layout includes a shared metal plug test pattern CT1 for multiple conductive plugs that electrically connect the source or drain of one MOS transistor to the gate of another MOS transistor in an equivalent SRAM device.

[0054] The first metal test layout M1 includes a plurality of first metal patterns and a plurality of second metal patterns arranged at intervals therebetween. The plurality of first metal patterns respectively cover the plurality of shared metal plug test patterns CT1, and along the direction perpendicular to the test structure layout, the projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns CT1 respectively partially or completely overlap.

[0055] The second contact hole test pattern includes a plurality of second contact hole patterns CT2, which correspond to a plurality of first metal patterns and a plurality of second metal patterns respectively.

[0056] The second metal test pattern includes a first test chain pattern S1 and a second test chain pattern S2. The first test chain pattern S1 includes a plurality of first sub-test chain patterns S11 extending along the X or Y direction and all being in the shape of a straight strip. Each of the first sub-test chain patterns S11 includes a plurality of third metal patterns that cover the plurality of second contact hole patterns CT2 in the same row or column along the X or Y direction. The second test chain pattern S2 includes a plurality of second sub-test chain patterns S22 extending along the X or Y direction and all being in the shape of a straight strip. Each of the second sub-test chain patterns S22 includes a plurality of fourth metal patterns that cover the plurality of second contact hole patterns CT2 in the same row or column along the X or Y direction.

[0057] It should be noted that, in this embodiment of the invention, since the test pattern of the second contact hole pattern CT2 located on the test pattern of the first metal test pattern M1 is located below the patterns of the first test chain pattern S1 and the second test chain pattern S2, therefore, in the exemplary embodiment provided by the present invention... Figure 2 In the diagram, the test pattern of the second contact hole pattern CT2 is not visible below the first test chain pattern S1 and the second test chain pattern S2. Therefore, in order to identify the test pattern of the second contact hole pattern CT2, the present invention exemplarily uses... Figure 2 In other places where the test pattern of the second contact hole pattern CT2 is formed, the test pattern of the second contact hole pattern CT2 is marked, but the test pattern of the second contact hole pattern CT2 located below the pattern of the first test chain pattern S1 and the second test chain pattern S2 is not marked.

[0058] The plurality of third metal patterns and the plurality of fourth metal patterns are different second-layer metal lines that respectively cover the first metal pattern and the second metal pattern in the second-layer metal line structure of the test structure layout provided by the present invention. Therefore, the plurality of third metal patterns and the plurality of fourth metal patterns are arranged at intervals, and one of the third metal patterns or one of the fourth metal patterns covers one of the second contact hole patterns.

[0059] Furthermore, the test structure layout provided by the present invention also includes an isolation structure test layout, which includes a shallow trench isolation structure pattern STI, and the shallow trench isolation structure pattern is located under a plurality of shared metal plug test patterns CT1.

[0060] Furthermore, the test structure layout provided by the present invention may also include a pad test layout (not shown), the pad test layout including a first pad pattern (not shown) and a second pad pattern (not shown), the first pad pattern being located on the first test chain pattern S1, and the second pad pattern being located on the second test chain pattern S2.

[0061] Specifically, it can be like Figure 2 The second metal test pattern in the test structure is differentiated into odd-numbered and even-numbered rows along the X direction to form a first test chain pattern S1 and a second test chain pattern S2. Alternatively, the second metal test pattern in the test structure can also be differentiated into odd-numbered and even-numbered columns along the Y direction to form a first test chain pattern and a second test chain pattern (i.e., ...). Figure 2 The layout of the test structure is rotated 90 degrees. The difference between the first test chain pattern S1 and the second test chain pattern S2 is that one is a second layer of metal lines connected to the first metal pattern electrically connected to the shared metal plug test pattern CT1, and the other is a second layer of metal lines connected to the first layer of metal lines electrically connected to the non-shared metal plug test pattern (a common metal plug in SRAM devices that is electrically connected to the source or drain of the MOS transistor, which can also be called a common metal plug). The present invention does not specifically limit which one is the first test chain pattern and which one is the second test chain pattern.

[0062] Based on the test structure layout described above, this invention also provides a method for fabricating a test structure for a semiconductor device, specifically as follows: Figure 3 As shown, the method for fabricating the test structure of the semiconductor device provided by the present invention may specifically include the following steps:

[0063] Step S301: Provide a semiconductor substrate.

[0064] Step S302: Provide an isolation structure test layout, and form a device isolation structure on the semiconductor substrate using the isolation structure test layout;

[0065] Step S303: Provide a first contact hole test layout, and form a plurality of shared metal plugs on the device isolation structure using the first contact hole test layout;

[0066] Step S304: Provide a first metal test pattern and form a first layer metal wire structure through the first metal test pattern. The first layer metal wire structure includes a plurality of first sub-metal wires and a plurality of second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug and is electrically connected to the shared metal plug. The plurality of second sub-metal wires are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the plurality of first sub-metal wires.

[0067] Step S305: Provide a second contact hole test layout, and form a plurality of through holes through the second contact hole test layout, wherein the plurality of through holes respectively cover a plurality of first sub-metal lines and a plurality of second sub-metal lines;

[0068] Step S306: Provide a second metal test pattern and form a second layer metal wire structure using the second metal test pattern. The second layer metal wire structure includes a plurality of third sub-metal wires and a plurality of fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire.

[0069] In this embodiment, a semiconductor substrate can be provided first. Then, a device isolation structure for isolating device units can be formed on the semiconductor substrate using processes such as etching and deposition. For example, the device isolation structure in the test structure proposed in this invention can be a shallow trench isolation structure (STI). Then, with the shallow trench isolation structure (STI) as the bottom, various test patterns are formed layer by layer on its surface. Specifically, the order is to first form the first contact hole test pattern, and then form the first metal test pattern, the second contact hole test pattern, and the second metal test pattern. This is prior art and is not specifically limited by this invention.

[0070] Based on such Figure 2 The test structure layout shown above and Figure 3 The present invention also provides a test structure for a semiconductor device formed using the test structure layout and the manufacturing method, specifically including:

[0071] A semiconductor substrate on which a device isolation structure (STI) is formed;

[0072] Multiple shared metal plugs (CTs) are located on the device isolation structure (STI), and each of the shared metal plugs (CTs) is used as a conductive plug in an equivalent SRAM device to electrically connect the source or drain of one MOS transistor to the gate of another MOS transistor.

[0073] The first layer of metal wires includes multiple first sub-metal wires and multiple second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug CT1 and is electrically connected to the shared metal plug CT1. The multiple second sub-metal wires M1b are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the multiple first sub-metal wires.

[0074] The second layer of metal wires includes multiple third sub-metal wires and multiple fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire. The third sub-metal wires in the same row or column along the X or Y direction are connected in series to form a first test chain S1, and the fourth sub-metal wires in the same row or column along the X or Y direction are connected in series to form a second test chain S2.

[0075] Furthermore, the test structure provided by the present invention may also include a first test pad (not shown) electrically connected to the first test chain and a second test pad (not shown) electrically connected to the second test chain.

[0076] Obviously, in the test structure provided by the present invention, the third sub-metal wires formed on the surface of the shared metal plug in the same row or column along the X and / or Y directions are connected in series. Then, the ends of the first sub-metal wires in the multiple rows or columns are connected in series as a first test chain (assuming it is M2 in odd-numbered rows or columns). Then, using the same method, the fourth sub-metal wires on the surface of the non-shared metal plug in the same row or column along the X or Y directions are connected in series (M2 in even-numbered rows or columns relative to the first test chain) to form a second test chain. Then, by testing the first test chain and the second test chain, that is, by testing whether there is current between the second layer metal wires in odd-numbered rows and the second layer metal wires in even-numbered rows, it can be determined whether the metal layer M1 on the surface of the shared metal plug and its adjacent normal metal plug is short-circuited.

[0077] The semiconductor substrate can be any suitable substrate known in the art, such as at least one of the following materials: silicon, germanium, germanium silicon, silicon carbon, silicon carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors.

[0078] Based on the same inventive concept, the present invention also provides a testing method based on the test structure described above, which may specifically include the following steps:

[0079] Provide a test structure for the semiconductor device as described above;

[0080] Voltages are applied to the first test pad and the second test pad respectively, and the current between the first test chain and the second test chain is measured.

[0081] Furthermore, based on the aforementioned test structure, the present invention also provides a defect detection method for semiconductor devices based on this test structure, specifically including the following steps:

[0082] Provide a test structure for the semiconductor device as described above;

[0083] Voltages are applied to the first test pad and the second test pad respectively, and the current between the first test chain and the second test chain is measured to determine whether the test structure has a shared metal plug and a short circuit between the second sub-metal line adjacent to the first sub-metal line that is electrically connected to it.

[0084] Further, the step of determining whether the test structure has a shared metal plug and a short circuit between a second sub-metal wire adjacent to the first sub-metal wire electrically connected to it includes:

[0085] Determine whether the measured current between the first test chain and the second test chain is greater than zero. If not, determine that the test structure has a shared metal plug and a short circuit between the second sub-metal line adjacent to the first sub-metal line that is electrically connected to it.

[0086] In summary, this invention provides a novel test structure for semiconductor devices. In this test structure, third sub-metal lines on the surface of a shared metal plug in the same row or column along the X and / or Y directions are connected in series. Then, the ends of the multiple rows or columns of first sub-metal lines are connected in series to form a first test chain (assuming it is M2 in an odd-numbered row or column). Then, using the same method, fourth sub-metal lines on the surface of a non-shared metal plug in the same row or column along the X or Y directions are connected in series (M2 in an even-numbered row or column relative to the first test chain) to form a second test chain. Then, by testing the first and second test chains—that is, by testing whether there is current between the second layer metal lines in odd-numbered rows and the second layer metal lines in even-numbered rows—it can be determined whether the shared metal plug is short-circuited with the metal layer M1 on the surface of its adjacent normal metal plug.

[0087] Furthermore, since the test structure provided by the present invention can determine whether the metal layer M1 on the surface of the shared metal plug and its adjacent normal metal plug is short-circuited, by changing the size of the shared metal plug and the first layer of metal line in the test structure provided by the present invention, and then testing the test structure, the optimal size of the two can be determined, and the performance of the SRAM device can be monitored in real time, thereby ensuring the yield of the semiconductor device.

[0088] It should be noted that, in the embodiments of the present invention provided, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus. The processor, the communication interface, and the memory communicate with each other through the communication bus. The memory is used to store computer programs. When the processor executes the program stored in the memory, it implements the testing method or the defect detection method for semiconductor devices provided in the embodiments of the present invention.

[0089] Furthermore, other implementations of the test method implemented by the processor executing the program stored in the memory, or the defect detection method for the semiconductor device, are the same as those mentioned in the foregoing method embodiment section, and will not be repeated here.

[0090] In another embodiment of the present invention, a computer-readable storage medium is provided, which stores instructions that, when executed on a computer, cause the computer to perform any of the test methods described in the above embodiments, or the defect detection method for the semiconductor device.

[0091] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium (e.g., solid-state drive), etc.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0093] Similar parts can be referred to interchangeably, and each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, so the description is relatively simple, and relevant parts can be referred to the description of the method embodiments.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A test structure for a semiconductor device, characterized in that, include: A semiconductor substrate on which a device isolation structure is formed; Multiple shared metal plugs are located on the device isolation structure, and each of the shared metal plugs is used as a conductive plug in an equivalent SRAM device to electrically connect the source or drain of one MOS transistor to the gate of another MOS transistor. The first layer of metal wires includes multiple first sub-metal wires and multiple second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug and is electrically connected to the shared metal plug, while multiple second sub-metal wires are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the multiple first sub-metal wires. The second layer of metal wires includes multiple third sub-metal wires and multiple fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire. The third sub-metal wires in the same row or column along the X or Y direction are connected in series to form a first test chain, and the fourth sub-metal wires in the same row or column along the X or Y direction are connected in series to form a second test chain.

2. The test structure for the semiconductor device as described in claim 1, characterized in that, The test structure also includes multiple through holes, which are located in the intermetallic medium between the first metal layer and the second metal layer, for electrically connecting corresponding sub-metal lines between the first metal layer and the second metal layer, respectively.

3. The test structure for the semiconductor device as described in claim 1, characterized in that, The test structure further includes a first test pad electrically connected to the first test chain and a second test pad electrically connected to the second test chain.

4. A test structure layout, characterized in that, The test architecture layout includes: The first contact hole test layout includes a shared metal plug test pattern of multiple conductive plugs for electrically connecting the source or drain of one MOS transistor to the gate of another MOS transistor in an equivalent SRAM device. The first metal test layout includes a plurality of first metal patterns and a plurality of second metal patterns arranged at intervals therebetween. The plurality of first metal patterns respectively cover the plurality of shared metal plug test patterns, and along the direction perpendicular to the test structure layout, the projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns respectively partially or completely overlap. The second contact hole test layout includes a plurality of second contact hole patterns, which correspond to a plurality of first metal patterns and a plurality of second metal patterns, respectively. The second metal test pattern includes a first test chain pattern and a second test chain pattern. The first test chain pattern includes multiple first sub-test chain patterns extending along the X or Y direction and all being in the shape of a straight strip. Each first sub-test chain pattern includes multiple third metal patterns that cover multiple second contact hole patterns in the same row or column along the X or Y direction. The second test chain pattern includes multiple second sub-test chain patterns extending along the X or Y direction and all being in the shape of a straight strip. Each second sub-test chain pattern includes multiple fourth metal patterns that cover multiple second contact hole patterns in the same row or column along the X or Y direction.

5. The test structure layout as described in claim 4, characterized in that, The plurality of third metal patterns and the plurality of fourth metal patterns are arranged at intervals, and one of the third metal patterns or one of the fourth metal patterns covers one of the second contact hole patterns.

6. The test structure layout as described in claim 4, characterized in that, The test structure layout also includes an isolation structure test layout, which includes a shallow trench isolation structure pattern, and the shallow trench isolation structure pattern is located below the plurality of shared metal plug test patterns.

7. The test structure layout as described in claim 4, characterized in that, The test structure layout also includes a pad test layout, which includes a first pad pattern and a second pad pattern. The first pad pattern is located on the first test chain pattern, and the second pad pattern is located on the second test chain pattern.

8. A method for preparing a test structure, characterized in that, The method for preparing the test structure uses the test structure layout according to any one of claims 4 to 7, and the method includes the following steps: Provide a semiconductor substrate; An isolation structure test layout is provided, and a device isolation structure is formed on the semiconductor substrate using the isolation structure test layout; A first contact hole test layout is provided, and a plurality of shared metal plugs are formed on the device isolation structure through the first contact hole test layout; A first metal test pattern is provided, and a first layer metal wire structure is formed by the first metal test pattern. The first layer metal wire structure includes a plurality of first sub-metal wires and a plurality of second sub-metal wires. A first sub-metal wire covers the surface of a shared metal plug and is electrically connected to the shared metal plug. The plurality of second sub-metal wires are respectively located between two adjacent first sub-metal wires, that is, they are arranged at intervals with the plurality of first sub-metal wires. A second contact hole test layout is provided, and a plurality of through holes are formed through the second contact hole test layout, wherein the plurality of through holes respectively cover a plurality of first sub-metal lines and a plurality of second sub-metal lines; A second metal test pattern is provided, and a second layer metal wire structure is formed by the second metal test pattern. The second layer metal wire structure includes a plurality of third sub-metal wires and a plurality of fourth sub-metal wires. One of the third sub-metal wires covers the surface of a first sub-metal wire, and one of the fourth sub-metal wires covers the surface of a second sub-metal wire.

9. A testing method, characterized in that, Includes the following steps: Provide a test structure for the semiconductor device as described in any one of claims 1-3; Voltages are applied to the first test pad and the second test pad respectively, and the current between the first test chain and the second test chain is measured.

10. A defect detection method for a semiconductor device, characterized in that, Includes the following steps: Provide a test structure for the semiconductor device as described in any one of claims 1-3; Voltages are applied to the first test pad and the second test pad respectively, and the presence of a shared metal plug and a short circuit between the first test chain and the second test chain is determined by measuring the current between them.

11. The defect detection method for a semiconductor device as described in claim 10, characterized in that, The step of determining whether the test structure has a shared metal plug and a short circuit between a second sub-metal wire adjacent to a first sub-metal wire electrically connected to it includes: Determine whether the measured current between the first test chain and the second test chain is greater than zero. If not, determine that the test structure has a shared metal plug and a short circuit between the second sub-metal line adjacent to the first sub-metal line that is electrically connected to it.

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