Gate driving circuit, display panel and display device

Abstract

The present application discloses a gate drive circuit, a display panel and a display device. The gate drive circuit includes: n shift register units arranged along a first direction; the shift register unit includes an input module, a first node control module, a second node control module and an output control module; wherein the input module, the first node control module and the second node control module are all electrically connected to the third node, the first node control module is used to control the level of the first node, the second node control module is used to control the level of the second node, the output control module is electrically connected to the scan signal output terminal, the first node and the second node, and is used to control the scan signal output terminal to output a scan signal according to the level of the first node and the level of the second node; along the first direction, the control end of the input module of the mth shift register unit is electrically connected to the scan signal output terminal of the m+1th shift register unit and the scan signal output terminal of the m-1th shift register unit, respectively, m∈n.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a gate driving circuit, a display panel and a display device. Background Art

[0002] With the development of technology, display panels are also constantly being innovated. At present, active-matrix organic light-emitting diode (AMOLED) has gradually become the mainstream. When the AMOLED display panel is running, it needs the driving control of the source driving circuit, gate driving circuit and light driving circuit to ensure the normal light emission of the light-emitting pixels. Summary of the invention

[0003] The embodiments of the present application provide a gate driving circuit, a display panel and a display device, which can provide a gate driving control solution supporting multiple modes.

[0004] In a first aspect, an embodiment of the present application provides a gate driving circuit, comprising:

[0005] n shift register units arranged along a first direction;

[0006] The shift register unit includes an input module, a first node control module, a second node control module and an output control module;

[0007] Wherein, the input module, the first node control module and the second node control module are all electrically connected to the third node;

[0008] The first node control module is used to control the level of the first node, and the second node control module is used to control the level of the second node;

[0009] The output control module is electrically connected to the scan signal output terminal, the first node and the second node; the output control module is used to control the scan signal output terminal to output the scan signal according to the level of the first node and the level of the second node;

[0010] Along the first direction, the control end of the input module of the mth shift register unit is electrically connected to the scan signal output end of the m+1th shift register unit and the scan signal output end of the m-1th shift register unit respectively, m∈n.

[0011] In a second aspect, an embodiment of the present application provides a display panel, comprising a gate driving circuit as described above.

[0012] In a third aspect, an embodiment of the present application provides a display device, which includes a display panel, and the display panel is configured as the display panel of the above aspect.

[0013] Compared with the prior art, the gate drive circuit, display panel and display device provided in the embodiments of the present application are provided with n shift register units arranged along the first direction in the gate drive circuit, the shift register units include an input module, a first node control module, a second node control module and an output control module, and the input module, the first node control module and the second node control module are all electrically connected to the third node. And because along the first direction, the control end of the input module of the mth shift register unit is electrically connected to the scan signal output end of the m+1th shift register unit and the scan signal output end of the m-1th shift register unit, respectively, m∈n. Thus, along the first direction, the input module of the shift register unit can simultaneously receive the signal control of the scan signal output ends of two adjacent shift register units, so that the gate drive circuit is suitable for the forward scanning mode and the reverse scanning mode, thereby providing a gate drive control scheme in at least two modes, which is suitable for various requirements and improves the compatibility of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 This is a schematic diagram of an optional module structure of a gate drive circuit provided in an embodiment of the present application;

[0016] Figure 2 This is a schematic diagram of an optional module structure of a single shift register unit in a gate drive circuit provided by an embodiment of the present application;

[0017] Figure 3 This is a schematic diagram of an optional module structure of three cascaded shift register units in a gate drive circuit provided by another embodiment of the present application;

[0018] Figure 4 This is a schematic diagram of an optional module structure of a gate drive circuit provided in an embodiment of the present application;

[0019] Figure 5 is a schematic diagram of an optional module structure of a single shift register unit in a gate drive circuit provided by another embodiment of the present application;

[0020] Figure 6 is a signal timing diagram of a gate driving circuit provided by an embodiment of the present application when working in a forward scanning mode;

[0021] Figure 7is a signal timing diagram of a gate driving circuit provided by an embodiment of the present application when operating in a reverse scanning mode;

[0022] Figure 8 This is a schematic diagram of an optional circuit structure of a single shift register unit in a gate drive circuit provided by an embodiment of the present application;

[0023] Fig. 9 This is a schematic diagram of an optional circuit structure of three cascaded shift register units in a gate drive circuit provided by the present application;

[0024] Fig.10 is an optional schematic diagram of a display panel provided by the present application;

[0025] Fig.11 This is a schematic diagram of an optional module structure of a display panel provided by the present application;

[0026] Fig.12 This is a schematic diagram of an optional module structure of a display panel provided by the present application;

[0027] Fig.13 This is a schematic diagram of an optional module structure of a pixel circuit in a display panel provided by the present application;

[0028] Fig.14 This is a schematic diagram of an optional module structure of a display panel provided by the present application;

[0029] Fig.15 This is a schematic diagram of an optional circuit structure of a pixel circuit in a display panel provided by the present application;

[0030] Fig.16 It is a signal timing diagram involved in a pixel circuit when a gate driving circuit in a display panel provided by the present application works in a forward scanning mode;

[0031] Fig.17 It is a signal timing diagram involved in a pixel circuit when a gate driving circuit in a display panel provided by the present application works in a reverse scanning mode;

[0032] Fig.18 This is a schematic diagram of a module structure of a pixel circuit in a display panel provided by the present application;

[0033] Fig.19 It is a circuit structure schematic diagram of a pixel circuit in a display panel provided by the present application;

[0034] Fig. 20 It is a signal timing diagram involved in a pixel circuit when a gate driving circuit in a display panel provided by the present application works in a forward scanning mode;

[0035] Fig.21It is a signal timing diagram involved in a pixel circuit when a gate driving circuit in a display panel provided by the present application works in a reverse scanning mode;

[0036] Fig. 22 is a schematic diagram of a module structure of a pixel circuit in a display panel provided by another embodiment of the present application;

[0037] Fig.23 is a circuit structure diagram of a pixel circuit in a display panel provided by another embodiment of the present application;

[0038] Fig.24 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application.

[0039] In the attached figure:

[0040] 1. Gate drive circuit; 10. Shift register unit; X, first direction; Y, row direction; SCAN, scan signal; XCK, first clock signal line; CK, second clock signal line; STV, start transmission signal line; STV1, first start transmission signal line; STV2, second start transmission signal line; S1, first selection switch; S2, second selection switch; 11, first node control module; 12, second node control module; 13, output control module; 14, input module; 15, first input selection unit; 16, second input selection unit; N1, first node; N2, The second node; N3, the third node; OUT, the scan signal output terminal; L1, the first signal line; L2, the second signal line; IN1, the first input terminal; IN2, the second input terminal; SW, the control terminal of the input module; SW1, the first control terminal; SW2, the second control terminal; OUT1, the first output terminal; OUT2, the second output terminal; T1, the first period; T2, the second period; T3, the third period; MA, the first switch; MB, the second switch; M1, the first transistor; M2, the second transistor; M3, the third transistor; M4, the fourth transistor; M5, the fifth transistor; M6 , sixth transistor; M7, seventh transistor; C1, first capacitor; C2, second capacitor; 100, pixel row 100; 110, forward and reverse scan selection module; 111, first scan selection unit; 112, second scan selection unit; 113, forward and reverse scan selection output terminal; 114, forward and reverse scan selection input terminal; P, sub-pixel; 120, pixel circuit; 130, light-emitting element; 141, driving transistor; 142, first initialization module; 143, data writing module; 144, threshold compensation module; Vref, reset voltage signal; Vdata, data signal; PVDD, electric Source signal line; EM, light-emitting control signal line; T01, first initialization transistor; T02, data writing transistor T03, first light-emitting control transistor; T04, second light-emitting control transistor; T05, second initialization transistor; T06, threshold compensation transistor; M8, first scan selection switch; M9, second scan selection switch; A1, first scan input terminal; A2, first scan control terminal; A3, first scan output terminal; B1, second scan input terminal; B2, second scan control terminal, B3, second scan output terminal; L3, first control signal line; L4, second control signal line. DETAILED DESCRIPTION

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0042] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0043] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments will be described in detail below in conjunction with the accompanying drawings.

[0044] In order to realize normal light-emitting display, the current display panel requires coordinated control of various driving circuits, which may include a gate driving circuit.

[0045] At present, the gate driving circuit in the related art is mainly used to output scanning signals to each sub-pixel in the display area. The gate driving circuit includes a plurality of shift register units, and the gate driving circuit composed of each shift register unit has only one fixed scanning signal level transmission direction.

[0046] For example, a shift register unit close to the driving chip can be used as the starting stage, and starting from the starting stage, the direction away from the driving chip can be used as the fixed stage transmission direction of the scanning signal. Then, according to the fixed stage transmission direction, the shift register unit is controlled to output the scanning signal to the sub-pixels in the display area step by step.

[0047] For another example, the gate driving circuit may also take a shift register unit in a direction away from the driving chip as the starting stage, and starting from the starting stage, take the direction close to the driving chip as the fixed stage transmission direction of the scanning signal, and then control the shift register unit to output the scanning signal to the sub-pixels in the display area step by step according to the fixed stage transmission direction.

[0048] For some special requirements, such as requiring the display panel to be able to display normally in both the forward and reverse directions, the display panel needs to be compatible with these two different modes in the scanning direction.

[0049] However, under the premise that the related technology only sets a fixed scanning signal level transmission direction, the panel layout of the display panel is fixed, and the relative position of the shift register unit in the gate driving circuit is fixed, so the gate driving circuit is difficult to support forward and reverse scanning compatibility.

[0050] In summary, the relevant technology urgently needs to provide a gate drive control solution that is compatible with multiple modes.

[0051] In order to solve the above technical problems, the embodiments of the present application provide a gate driving circuit, a display panel and a display device. Figures 1 to 9 An example of a gate driving circuit according to an embodiment of the present application is provided.

[0052] Please see Figures 1 to 3 , Figure 1 FIG. 1 shows an optional circuit structure diagram of a gate driving circuit according to an embodiment of the present application. Figure 2 Shows Figure 1 Schematic diagram of optional circuit structure of a single shift register unit in, Figure 3 Shows Figure 1 Schematic diagram of the optional circuit structure of three cascaded shift register units.

[0053] exist Figure 1 In the embodiment, the gate driving circuit 1 may include n shift register units 10 arranged along a first direction X, where n may be a positive integer. The first direction X may be a direction intersecting a scanning signal line in the display panel, and illustratively, the first direction X may be a direction perpendicular to the scanning signal line.

[0054] It should be noted that the embodiment of the present application is described by taking the first direction X as a direction from far away from the display panel driver chip to close to the display panel driver chip as an example. The first direction is the same as the stage transmission direction of the scan signal SCAN when the shift register unit 10 works in the forward scanning mode. Correspondingly, the first shift register unit 10 arranged along the first direction X is the farthest from the driver chip, and the nth shift register unit is the closest to the driver chip.

[0055] Please continue to see Figures 1 to 3The shift register unit 10 may include an input module 14 , a first node control module 11 , a second node control module 12 and an output control module 13 .

[0056] The input module 14, the first node control module 11 and the second node control module 12 are all electrically connected to the third node N3.

[0057] The first node control module 11 may be used to control the level of the first node N1 , and the second node control module 12 may be used to control the level of the second node N2 .

[0058] The output control module 13 is electrically connected to the scan signal output terminal OUT, the first node N1 and the second node N2. The output control module 13 can control the scan signal output terminal OUT to output the scan signal SCAN according to the level of the first node N1 and the level of the second node N2. The scan signal SCAN can provide a control signal for the pixel circuit.

[0059] Along the first direction X, the control terminal SW of the input module 14 of the mth shift register unit 10 is electrically connected to the scan signal output terminal OUT of the m+1th shift register unit 10 and the scan signal output terminal OUT of the m-1th shift register unit 10 respectively, m∈n.

[0060] In the embodiment of the present application, n shift register units 10 are arranged along the first direction X in the gate driving circuit 1, and the shift register unit 10 includes an input module 14, a first node control module 11, a second node control module 12 and an output control module 13. The input module 14, the first node control module 11 and the second node control module 12 are all electrically connected to the third node N3. Because along the first direction X, the control end SW of the input module 14 of the mth shift register unit 10 is electrically connected to the scan signal output end OUT of the m+1th shift register unit 10 and the scan signal output end OUT of the m-1th shift register unit 10, respectively, m∈n. Therefore, by setting the connection relationship between the input module 14 in a single shift register unit 10 and the scan signal output terminals OUT of two adjacent shift register units 10, along the first direction X, the input module 14 of the single shift register unit 10 can simultaneously receive the signal control of the scan signal output terminals OUT of two adjacent shift register units 10, so that after the input module 14 of the gate drive circuit 1 receives the signal, the multiple shift register units 10 have two scan signal transmission directions, which are compatible with the forward scan mode and the reverse scan mode. Therefore, a gate drive control scheme in at least two modes is provided, which is suitable for various requirements and improves the compatibility of the display panel.

[0061] In this example, the number n of the shift register units 10 may be greater than the number of pixel rows in the display panel.

[0062] It should be noted that, since the embodiment of the present application needs to provide a gate drive control scheme applicable to the forward scanning mode and the reverse scanning mode, each shift register unit 10 in the first direction X requires the cooperation of two adjacent shift register units 10. In order to ensure that the gate drive circuit 1 can normally output the scanning signal SCAN to each sub-pixel, a plurality of shift register units 10 can be provided more than the number of pixel rows, thereby ensuring that the gate drive circuit 1 can stably output the scanning signal SCAN to each sub-pixel.

[0063] In addition, considering that there may be virtual pixel rows in the display area and there may be empty transmission of the shift register unit 10 in the gate drive circuit 1 (empty transmission means that the scanning signal output by the shift register unit 10 will not be transmitted to the pixel circuit, but only transmitted to the next level shift register unit 10), it is also necessary to set up several more levels of shift register units 10 so that the overall number of shift register units 10 is greater than the number of pixel rows in the display panel.

[0064] It should also be noted that in the related art, when the panel layout is fixed, the scan output end of the previous shift register unit usually controls the access signal of the next shift register unit. Figures 1 to 3 In the embodiment of the present application, the input module 14 is a module for receiving input signals in a single shift register unit 10, and the control end SW of the input module 14 is respectively connected to the scan signal output ends OUT of two adjacent shift register units 10 of the shift register unit 10, so the input module 14 can be controlled by the signals of the two adjacent shift register units 10. With such a configuration, the shift register unit 10 in the gate drive circuit 1 can be applicable to the forward scanning mode and the reverse scanning mode, thus providing a gate drive control scheme in at least two modes, which is applicable to various requirements and improves the compatibility of the display panel.

[0065] Exemplarily, the forward scanning mode may use the direction from away from the display panel driver chip to close to the display panel driver chip as the level transmission direction of the scanning signal SCAN, and the reverse scanning mode may use the direction from away from the driver chip to close to the display panel driver chip as the level transmission direction of the scanning signal SCAN.

[0066] Exemplarily, the earth can also be used as a reference. When the display panel where the gate drive circuit 1 is located is placed with a normal display screen as a reference, when the scan signal SCAN is output to the sub-pixels from top to bottom, the gate drive circuit 1 can be considered to be operating in a forward scan mode, and the gate drive circuit 1 can be considered to be operating in a reverse scan mode when the scan signal SCAN is output to the sub-pixels from bottom to top.

[0067] For some optional examples, see also Figures 1 to 4 In the gate driving circuit 1, along the first direction X, the control terminal SW of the input module 14 in the first shift register unit 10 is electrically connected to the start transmission signal line STV.

[0068] The control terminal SW of the input module 14 in the n-th shift register unit 10 is electrically connected to the start transmission signal line STV.

[0069] It should be noted that, when the shift register unit 10 operates in the forward scanning mode, the control end SW of the input module 14 in the first shift register unit 10 arranged along the first direction X can be electrically connected to the start transmission signal line STV, and can be connected to the start signal transmitted by the start transmission signal line STV. At this time, the control end SW of the input module 14 in the nth shift register unit 10 may not be connected to the start signal transmitted by the start transmission signal line STV, and the control end SW of the input module 14 in the nth shift register unit 10 may be electrically connected to the scan signal output end OUT of the n-1th shift register unit 10.

[0070] When the shift register unit 10 operates in the reverse scanning mode, the control end SW of the input module 14 in the first shift register unit 10 arranged along the first direction X may not be connected to the start signal transmitted by the start transmission signal line STV, and the control end SW of the input module 14 in the first shift register unit 10 may be electrically connected to the scan signal output end OUT of the second shift register unit 10. The control end SW of the input module 14 in the nth shift register unit 10 may be electrically connected to the start transmission signal line STV, and connected to the start signal transmitted by the start transmission signal line STV.

[0071] For some optional examples, see also Figure 1 and Figure 2 By distinguishing the start transmission signal line STV, different access controls of the first shift register unit 10 and the nth shift register unit 10 arranged along the first direction X for the start signal in the forward / reverse scanning mode can be achieved.

[0072] Exemplarily, the start transmission signal line STV may include a first start transmission signal line STV1 and a second start transmission signal line STV2. The first start transmission signal line STV1 may be electrically connected to the control terminal SW of the input module 14 in the first shift register unit 10 arranged along the first direction X, and the second start transmission signal line STV2 may be electrically connected to the control terminal SW of the input module 14 in the nth shift register unit 10 arranged along the first direction X.

[0073] For some alternative examples, see also Figure 2 and Figure 4A first selection switch S1 and a second selection switch S2 may also be set. The start transmission signal line STV may be electrically connected to the control end SW of the input module 14 in the first shift register unit 10 arranged along the first direction X through the first selection switch S1. The start transmission signal line STV may also be electrically connected to the control end SW of the input module 14 in the nth shift register unit 10 arranged along the first direction X through the second selection switch S2.

[0074] When the shift register unit 10 works in the forward scanning mode, the first selection switch S1 can be controlled to be turned on and the second selection switch S2 can be turned off. When the shift register unit 10 works in the reverse scanning mode, the second selection switch S2 can be controlled to be turned on and the first selection switch S1 can be turned off. Thus, by controlling the different states of the first selection switch S1 and the second selection switch S2, different access controls of the first shift register unit 10 and the nth shift register unit 10 arranged along the first direction X for the start signal in the forward and reverse scanning modes can be realized.

[0075] The start transmission signal line STV can control the input module 14 in the first or nth shift register unit 10 arranged along the first direction X to access the input signal. By being electrically connected to the start transmission signal line STV, the electrically connected shift register unit 10 can be controlled to access the input signal.

[0076] In this example, in the first direction X, by setting the control end SW of the input module 14 of the first shift register unit 10 to be electrically connected to the start transmission signal line STV, and setting the control end SW of the input module 14 of the nth shift register unit 10 to be electrically connected to the start transmission signal line STV, combined with the different access control of the start signal by the shift register units 10 at the head and tail ends when the shift register unit 10 works in the forward / reverse scanning mode, the shift register units 10 at the head and tail ends along the first direction X can flexibly receive the signal of the adjacent shift register unit 10 or the control of the signal of the start transmission signal line STV in the forward / reverse scanning mode, thereby making the input module 14 of the gate drive circuit 1 have two signal input directions, which are compatible with the forward scanning mode and the reverse scanning mode. Therefore, a gate drive control scheme in at least two modes is provided, which is suitable for various requirements and improves the compatibility of the display panel.

[0077] For some optional examples, see Figure 5 , and please also refer to Figures 1 to 4 , Figure 5 Another optional circuit structure schematic diagram of a shift register unit in a gate driving circuit of an embodiment of the present application is shown.

[0078] The input module 14 of the shift register unit 10 may include a first input selection unit 15 and a second input selection unit 16 .

[0079] The first input selection unit 15 includes a first input terminal IN1, a first output terminal OUT1 and a first control terminal SW1, and the second input selection unit 16 includes a second input terminal IN2, a second output terminal OUT2 and a second control terminal SW2.

[0080] The first input terminal IN1 is electrically connected to the first signal line L1, and the first output terminal OUT1 is electrically connected to the third node N3;

[0081] The second input terminal IN2 is electrically connected to the second signal line L2, and the second output terminal OUT2 is electrically connected to the third node N3;

[0082] Along the first direction X, the first control terminal SW1 of the mth shift register unit 10 is electrically connected to the scan signal output terminal OUT of the m+1th shift register unit 10 , and the second control terminal SW2 of the mth shift register unit 10 is electrically connected to the scan signal output terminal OUT of the m-1th shift register unit 10 .

[0083] In this example, a first input selection unit 15 and a second input selection unit 16 are provided in the input module 14, wherein the first input selection unit 15 is electrically connected to the scan signal output terminal OUT of the next-stage shift register unit 10, and the second input selection unit 16 is electrically connected to the scan signal output terminal OUT of the previous-stage shift register unit 10, thereby the input module 14 of the shift register unit 10 can selectively access the signal emitted by the first signal line L1 or the second signal line L2.

[0084] It should also be noted that, for the first shift register unit 10 arranged along the first direction X, in the forward scanning mode, its first control terminal SW1 can be electrically connected to the scanning signal output terminal OUT of the second shift register unit 10, and its second control terminal SW2 can be electrically connected to the start transmission signal line STV.

[0085] For the nth shift register unit 10 arranged along the first direction X, in the reverse scanning mode, its first control terminal SW1 can be electrically connected to the start transmission signal line STV, and its second control terminal SW2 can be electrically connected to the scanning signal output terminal OUT of the n-1th shift register unit 10.

[0086] The first signal line L1 and the second signal line L2 can stably output level signals. The level signals transmitted by the first signal line L1 and the second signal line L2 are different. For example, when the first signal line L1 outputs a high level signal, the second signal line L2 can output a low level signal. For another example, when the first signal line L1 outputs a low level signal, the second signal line L2 can output a high level signal.

[0087] In these examples, by setting the first input selection unit 15 and the second input selection unit 16 in the input module 14, the input module 14 can selectively control the level signal of the first signal line L1 or the level signal of the second signal line L2 to be transmitted to the third node N3 according to the signal output from the scanning signal output terminal OUT of the shift register unit 10 adjacent to the shift register unit 10, thereby providing an optional implementation scheme for the change of the node potential of the third node N3, and ultimately enabling a single shift register unit 10 to adapt to changes in the forward and reverse scanning modes, with strong adaptability.

[0088] Please see Figure 6 , and please also refer to Figures 1 to 5 ,in Figure 6 The signal timing diagram of each signal when the gate driving circuit operates in the forward scanning mode is shown.

[0089] It should be noted that the embodiments of the present application are described in conjunction with all the accompanying drawings by taking the thin film transistors in the shift register unit 10 and the pixel circuit as P-type thin film transistors as an example. In other examples, N-type thin film transistors may also be provided in the shift register unit and the pixel circuit. For example, when the scan signal output terminal OUT of the shift register unit 10 outputs a high-level scan signal SCAN, the pixel circuit enters the initialization stage.

[0090] In this example, when the gate driving circuit 1 operates in the forward scanning mode, the first signal line L1 transmits a high level signal, and the second signal line L2 transmits a low level signal.

[0091] When the gate driving circuit 1 operates in the forward scanning mode, the shift register units 10 sequentially arranged along the first direction X in the gate driving circuit 1 can output the scanning signal SCAN step by step.

[0092] During the T1 period, the second control terminal SW2 in the mth shift register unit 10 arranged along the first direction X is electrically connected to the scan signal output terminal OUT in the m-1th shift register unit 10, the second control terminal SW2 is connected to the low level signal output by the scan signal output terminal OUT in the m-1th shift register unit 10, and the second input selection unit 16 is turned on.

[0093] The first control terminal SW1 is electrically connected to the scan signal output terminal OUT in the m+1th shift register unit 10 , and the first control terminal SW1 receives the high level signal output by the scan signal output terminal OUT in the m+1th shift register unit 10 , and the first input selection unit 15 is turned off.

[0094] At this time, the second input terminal IN2 of the mth shift register unit 10 is connected to the low level signal transmitted by the second signal line L2, and the low level signal can be transmitted to the third node N3 via the second input selection unit 16. The third node N3 produces a potential change, and the mth shift register unit 10 is thus connected to the low level input signal, so that the scan signal output terminal OUT of the mth shift register unit 10 outputs a low level signal in the next time period, that is, the T3 time period.

[0095] In the T3 period, when the scan signal output terminal OUT of the mth shift register unit 10 arranged along the first direction X stably outputs a low level signal, the second control terminal SW2 of the m+1th shift register unit 10 arranged along the first direction X is electrically connected to the scan signal output terminal OUT of the mth shift register unit 10, and the first control terminal SW1 of the m-1th shift register unit 10 arranged along the first direction X is also electrically connected to the scan signal output terminal OUT of the mth shift register unit 10.

[0096] At this time, the second input selection unit 16 in the m+1th shift register unit 10 arranged along the first direction X is turned on, and the second input terminal IN2 in the m+1th shift register unit 10 is connected to the low level signal transmitted by the second signal line L2, so that the scanning signal output terminal OUT of the m+1th shift register unit 10 outputs a low level signal in the next time period, that is, the T2 time period.

[0097] The first input selection unit 15 in the m-1th shift register unit 10 arranged along the first direction X is turned on, and the first input terminal IN1 in the m-1th shift register unit 10 is connected to the high level signal transmitted by the first signal line L1, so that the m-1th shift register unit 10 realizes the signal reset of the third node N3, and the scan signal output terminal OUT of the m-1th shift register unit 10 outputs a high level signal in the next time period, that is, the T2 time period.

[0098] In the T2 period, when the scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X stably outputs a low-level signal, the first control terminal SW1 in the mth shift register unit 10 is electrically connected to the scan signal output terminal OUT in the m+1th shift register unit 10. The first input selection unit 15 in the mth shift register unit 10 is turned on, and the first input terminal IN1 in the mth shift register unit 10 writes the high-level signal transmitted by the first signal line L1 into the third node N3, so that the mth shift register unit 10 realizes signal reset of the third node N3, thereby enabling the mth shift register unit 10 to output a high-level signal in the next period.

[0099] In these examples, when the gate drive circuit 1 operates in the forward scanning mode, the first signal line L1 transmits a high-level signal and the second signal line L2 transmits a low-level signal, so that the single shift register unit 10 can selectively input high and low-level signals, thereby changing the potential of the third node N3, so that when the gate drive circuit 1 operates in the forward scanning mode, the potential of the third node N3 can be changed in different time periods, thereby ensuring the stable output of the scanning signal SCAN.

[0100] Please continue to see Figure 6 , and please also refer to Figures 1 to 5 In this example, when the gate driving circuit 1 operates in the forward scanning mode, it includes a first period T1 and a second period T2.

[0101] Continuing to take the case where the thin film transistors in the shift register unit 10 and the pixel circuit are P-type thin film transistors, and when the scan signal SCAN output to the pixel circuit is at a low level, the pixel circuit enters the initialization phase as an example for explanation, then in a single signal output cycle of a single shift register unit 10, the occurrence time of the first time period T1 may be earlier than the second time period T2. The above-mentioned single signal output cycle refers to the cycle in which the shift register unit 10 controls a sub-pixel to completely write the data of a data frame.

[0102] In the first period T1, in the mth shift register unit 10, the second control terminal SW2 turns on the second input selection unit 16 in response to the enable signal output from the scan signal output terminal OUT of the m-1th shift register unit 10. The first control terminal SW1 turns off the first input selection unit 15 in response to the non-enable signal output from the scan signal output terminal OUT of the m+1th shift register unit 10, so as to write the low level signal transmitted by the second signal line L2 into the first node N1 via the third node N3.

[0103] It should be noted that the first period T1 may be a period in which the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a low-level scan signal SCAN to initialize the connected pixel circuit.

[0104] The enable signal may be a low-level scan signal SCAN, and the disable signal may be a high-level scan signal SCAN.

[0105] When the gate driving circuit 1 operates in the forward scanning mode, within the first time period T1, the scanning signal SCAN output by the m-1th shift register unit 10 arranged along the first direction X is at a low level, and the scanning signal SCAN can also be electrically connected to the second control terminal SW2 in the mth shift register unit 10, so that the low-level scanning signal SCAN is multiplexed as an enable signal, which can control the second input selection unit 16 in the mth shift register unit 10 to be turned on.

[0106] At this time, the scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X outputs a high-level scan signal SCAN, and the high-level scan signal SCAN is electrically connected to the first control terminal SW1 in the mth shift register unit 10, so that the high-level scan signal SCAN is multiplexed as a non-enable signal, which can control the first input selection unit 15 in the mth shift register unit 10 to be cut off.

[0107] Therefore, in the first period T1, the second input selection unit 16 in the mth shift register unit 10 is turned on, and the first input selection unit 15 is turned off, so that the low level signal transmitted by the second signal line L2 can be written into the first node N1 via the third node N3.

[0108] In the second time period T2, in the mth shift register unit 10, the second control terminal SW2 responds to the non-enable signal output by the scan signal output terminal OUT of the m-1th shift register unit 10 to turn off the second input selection unit 16, and the first control terminal SW1 responds to the enable signal output by the scan signal output terminal OUT of the m+1th shift register unit 10 to turn on the first input selection unit 15 to write the high-level signal transmitted by the first signal line L1 into the first node N1 via the third node N3.

[0109] It should be noted that the second period T2 may be a period in which the scan signal output terminal OUT of the (m+1)th shift register unit 10 arranged along the first direction X outputs a low-level scan signal SCAN, so that the corresponding electrically connected pixel circuit enters initialization.

[0110] When the gate drive circuit 1 operates in the second time period T2 of the forward scan mode, the scan signal SCAN output by the m+1th shift register unit 10 arranged along the first direction X is at a low level, and the scan signal SCAN can also be electrically connected to the first control terminal SW1 in the mth shift register unit 10, so that the low-level scan signal SCAN is multiplexed as an enable signal, which can control the first input selection unit 15 in the mth shift register unit 10 to be turned on.

[0111] At this time, the scan signal output terminal OUT of the m-1th shift register unit 10 outputs a high-level scan signal SCAN, and the high-level scan signal SCAN is electrically connected to the second control terminal SW2 in the mth shift register unit 10, so that the high-level scan signal SCAN is multiplexed as a non-enable signal, which can control the second input selection unit 16 in the mth shift register unit 10 to be cut off.

[0112] Therefore, in the second period T2, the second input selection unit 16 in the mth shift register unit 10 is turned off, and the first input selection unit 16 is turned on, so that the high level signal transmitted by the first signal line L2 can be written into the first node N1 via the third node N3.

[0113] In these examples, in different time periods, the m+1th shift register unit 10 and the m-1th shift register unit 10 arranged along the first direction X respectively input different signals to the first control terminal SW1 and the second control terminal SW2 of the mth shift register unit 10, and can select an input selection unit to be turned on in different time periods, so that the third node N3 of the shift register unit 10 can produce a level change in different time periods, which is suitable for the needs when a single shift register unit 10 works in the forward scanning mode.

[0114] Please see Figure 6 , and please also refer to Figures 1 to 3 , Figure 6 It shows a signal timing diagram of the first signal line L1 and the second signal line L2 when the gate driving circuit 1 works in the reverse scanning mode.

[0115] The gate driving circuit 1 operates in a reverse scanning mode, the first signal line L1 can transmit a low level signal VGL, and the second signal line L2 can transmit a high level signal VGH.

[0116] Still taking the example that the driving chip is located at the lower side of the display area of ​​the display panel, when the gate driving circuit 1 works in the reverse scanning mode, along the first direction X, the shift register unit 10 in the gate driving circuit 1 can output the scanning signal SCAN step by step in the direction away from the driving chip.

[0117] At this time, in the first direction X, the first input selection unit 15 in the mth shift register unit 10 is controlled by the signal of the scan signal output terminal OUT in the m+1th shift register unit 10, the second control terminal SW2 is electrically connected to the scan signal output terminal OUT in the m-1th shift register unit 10, the second control terminal SW2 receives the high level signal output by the scan signal output terminal OUT in the m-1th shift register unit 10, and the second input selection unit 16 is cut off.

[0118] At this time, the first input terminal IN1 of the mth shift register unit 10 is connected to the low level signal transmitted by the first signal line L1, and the low level signal can be transmitted to the third node N3 via the first input selection unit 15. The third node N3 generates a potential change, and the mth shift register unit 10 is thus connected to the low level input signal, so that the scan signal output terminal OUT of the mth shift register unit 10 outputs a low level signal in the next time period, that is, the T3 time period.

[0119] In the T3 period, when the scan signal output terminal OUT of the m-th shift register unit 10 arranged along the first direction X stably outputs a low level signal, the first control terminal SW1 in the m-1-th shift register unit 10 arranged along the first direction X is electrically connected to the scan signal output terminal OUT in the m-th shift register unit 10, and the second control terminal SW2 in the m+1-th shift register unit 10 arranged along the first direction X is also electrically connected to the scan signal output terminal OUT in the m-th shift register unit 10.

[0120] At this time, the first input selection unit 16 in the m-1th shift register unit 10 arranged along the first direction X is turned on, and the first input terminal IN1 in the m-1th shift register unit 10 is connected to the low level signal transmitted by the first signal line L1, so that the scanning signal output terminal OUT of the m-1th shift register unit 10 outputs a low level signal in the next time period, that is, the T2 time period.

[0121] The second input selection unit 15 in the m+1th shift register unit 10 arranged along the first direction X is turned on, and the second input terminal IN2 in the m+1th shift register unit 10 is connected to the high level signal transmitted by the second signal line L2, so that the m+1th shift register unit 10 realizes the signal reset of the third node N3, and the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a high level signal in the next time period, that is, the T2 time period.

[0122] In the T2 period, when the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X stably outputs a low-level signal, the second control terminal SW2 in the m-1th shift register unit 10 is electrically connected to the scan signal output terminal OUT in the m-1th shift register unit 10. The second input selection unit 16 in the m-1th shift register unit 10 is turned on, and the second input terminal IN2 in the m-1th shift register unit 10 writes the high-level signal transmitted by the second signal line L2 to the third node N3, so that the m-1th shift register unit 10 can reset the signal of the third node N3, thereby enabling the m-1th shift register unit 10 to output a high-level signal in the next period.

[0123] In these examples, by transmitting a low-level signal through the first signal line L1 and a high-level signal through the second signal line L2 when the gate drive circuit 1 operates in the reverse scanning mode, a single shift register unit 10 can selectively input high and low-level signals, thereby changing the potential of the third node N3, so that when the gate drive circuit 1 operates in the reverse scanning mode, the potential of the third node N3 can be changed in different time periods, thereby ensuring stable output of the scanning signal SCAN.

[0124] Please continue to see Figure 7 , and please also refer to Figures 1 to 5 In this example, when the gate driving circuit 1 operates in the reverse scanning mode, it may include a first period T1 and a second period T2.

[0125] Continuing with the example that the thin film transistors in the shift register unit 10 and the pixel circuit are P-type thin film transistors, when the scan signal SCAN output to the pixel circuit is at a low level, the pixel circuit enters the initialization phase. Then, in a single signal output cycle of a single shift register unit 10, the occurrence time of the first time period T1 may be earlier than the second time period T2.

[0126] In the first period T1, in the mth shift register unit 10, the first control terminal SW1 turns on the first input selection unit 15 in response to the enable signal output from the scan signal output terminal OUT of the m+1th shift register unit 10. The second control terminal SW2 turns off the second input selection unit 16 in response to the non-enable signal output from the scan signal output terminal OUT of the m-1th shift register unit 10, so as to write the low level signal transmitted by the first signal line L1 into the first node N1 via the third node N3.

[0127] It should be noted that the first period T1 may be a period in which the scan signal output terminal OUT of the (m+1)th shift register unit 10 arranged along the first direction X outputs a low-level scan signal SCAN to initialize the connected pixel circuit.

[0128] The enable signal may be a low level signal of the scan signal SCAN, and the disable signal may be a high level signal of the scan signal SCAN.

[0129] When the gate driving circuit 1 operates in the reverse scanning mode, within the first time period T1, the scanning signal SCAN output by the m+1th shift register unit 10 arranged along the first direction X is at a low level, and the scanning signal SCAN is electrically connected to the first control terminal SW1 in the mth shift register unit 10, so that the low-level scanning signal SCAN is multiplexed as an enable signal, which can control the first input selection unit 15 in the mth shift register unit 10 to be turned on.

[0130] At this time, the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a high-level scan signal SCAN, and the high-level scan signal SCAN is electrically connected to the second control terminal SW2 in the mth shift register unit 10, so that the high-level scan signal SCAN is multiplexed as a non-enable signal, which can control the second input selection unit 16 in the mth shift register unit 10 to be cut off.

[0131] Therefore, in the first period T1, the first input selection unit 15 in the mth shift register unit 10 is turned on and the second input selection unit 16 is turned off, so that the low level signal transmitted by the first signal line L1 can be written into the first node N1 via the third node N3.

[0132] In the second time period T2, in the mth shift register unit 10, the first control terminal SW1 responds to the non-enable signal output by the scan signal output terminal OUT of the m+1th shift register unit 10 to turn off the first input selection unit 15, and the second control terminal SW2 responds to the enable signal output by the scan signal output terminal OUT of the m+1th shift register unit 10 to turn on the second input selection unit 16 to write the high-level signal transmitted by the second signal line L2 into the first node N1 via the third node N3.

[0133] It should be noted that the second period T2 may be a period in which the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a high-level scan signal SCAN to initialize the corresponding electrically connected pixel circuit.

[0134] When the gate drive circuit 1 operates in the second time period T2 of the forward scan mode, the scan signal SCAN output by the m-1th shift register unit 10 arranged along the first direction X is at a low level, and the scan signal SCAN can also be electrically connected to the second control terminal SW2 in the mth shift register unit 10, so that the low-level scan signal SCAN is multiplexed as an enable signal, which can control the second input selection unit 16 in the mth shift register unit 10 to be turned on.

[0135] At this time, the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a high-level scan signal SCAN, and the high-level scan signal SCAN is electrically connected to the first control terminal SW1 in the mth shift register unit 10, so that the high-level scan signal SCAN is multiplexed as a non-enable signal, which can control the first input selection unit 15 in the mth shift register unit 10 to be cut off.

[0136] Therefore, in the second period T2, the second input selection unit 16 in the mth shift register unit 10 is turned on, and the first input selection unit 15 is turned off, so that the high level signal transmitted by the second signal line L2 can be written into the first node N1 via the third node N3.

[0137] In these examples, in different time periods, the m-1th shift register unit 10 and the m+1th shift register unit 10 arranged along the first direction X respectively input different signals to the second control terminal SW2 and the first control terminal SW1 of the mth shift register unit 10, and can selectively turn on an input selection unit in different time periods, so that the third node N3 of the shift register unit 10 can produce a level change in different time periods, which is suitable for the needs when a single shift register unit 10 works in the forward scanning mode.

[0138] Please see Figure 8 and Fig. 9 , and please also refer to Figures 1 to 7 , Figure 8 is another optional circuit structure diagram of a single shift register unit in the gate driving circuit of an embodiment of the present application, Fig. 9 for Figure 8 Schematic diagram of the circuit structure when the shift register units involved are cascaded.

[0139] In this example, the first input selection unit 15 may include a first switch MA. The input terminal of the first switch MA is the first input terminal IN1, the output terminal of the first switch MA is the first output terminal OUT1, and the control terminal of the first switch MA is the first control terminal SW1.

[0140] The second input selection unit 16 may include a second switch MB. The input end of the second switch MB is the second input end IN2, the output end of the second switch MB is the second output end OUT2, and the control end of the second switch MB is the second control end SW2.

[0141] Combination Figure 3 and Figure 8 That is, the input end of the first switch MA is electrically connected to the first signal line L1, and the output end of the first switch MA is electrically connected to the third node N3. The input end of the second switch MB is electrically connected to the second signal line L2, and the output end of the second switch MB is electrically connected to the third node N3.

[0142] For the mth shift register unit 10 arranged along the first direction X, the control end of the first switch MA is electrically connected to the scan signal output end OUT of the m+1th shift register unit 10, and the control end of the second switch MB is electrically connected to the scan signal output end OUT of the m-1th shift register unit 10.

[0143] The first switch MA and the second switch MB may be thin film field effect transistors (TFT), and the types of the first switch MA and the second switch MB may be set according to actual needs. For example, the first switch MA and the second switch MB are both P-type thin film field effect transistors.

[0144] In these examples, the optional circuit structures of the first input selection unit 15 and the second input selection unit 16 are provided correspondingly through the connection setting of the first switch MA and the second switch MB, which provides a technical basis for the gate drive circuit 1 to be compatible with the forward and reverse scanning modes.

[0145] In order to better illustrate the scanning driving scheme of the gate driving circuit 1 in the present application, the following is an example of other circuit structures in the gate driving circuit 1 of the embodiment of the present application except the input module 14.

[0146] It should be noted that Figure 8 What is shown is a schematic diagram of an optional circuit structure of the gate drive circuit of an embodiment of the present application. Of course, in other examples, other circuit structures in the above-mentioned gate drive circuit 1 except the input module 14 can be set according to actual needs.

[0147] exist Figure 8 In the embodiment, the first node control module 11 may include a first transistor M1, a second transistor M2, and a third transistor M3 and a second capacitor C2.

[0148] The first transistor M1 is electrically connected to the second transistor M2 and the third node N3 respectively, and a control terminal of the first transistor M1 is electrically connected to the first clock signal line XCK.

[0149] The second transistor M2 is electrically connected to the constant voltage high level signal line VGH and the first transistor M1 respectively, and the control end of the second transistor M2 is electrically connected to the second node N2.

[0150] The third transistor M3 is electrically connected to the third node N3 and the first node N1 , and a control terminal of the third transistor M3 is electrically connected to the constant voltage low level signal line VGL.

[0151] The second capacitor C2 is disposed between the scan signal output terminal OUT and the first node N1.

[0152] The second node control module 12 may include a fourth transistor M4 , a fifth transistor M5 , and a first capacitor C1 .

[0153] The fourth transistor M4 is electrically connected to the constant voltage low level signal line VGL and the second node N2 respectively, and the control end of the fourth transistor M4 is electrically connected to the second clock signal line CK.

[0154] The fifth transistor M5 is electrically connected to the second clock signal line CK and the second node N2, respectively, and a control terminal of the fifth transistor M5 is electrically connected to the third node N3.

[0155] The first capacitor C1 is electrically connected between the constant voltage high level signal line VGH and the second node N2.

[0156] The output control module 13 may include a sixth transistor M6 and a seventh transistor M7.

[0157] The sixth transistor M6 is electrically connected to the scan signal output terminal OUT and the constant voltage high level signal line VGH respectively, and the control terminal of the seventh transistor M7 is connected to the second node N2.

[0158] The seventh transistor M7 is electrically connected to the first clock signal line XCK and the scan signal output terminal OUT respectively, and the control terminal of the seventh transistor M7 is electrically connected to the first node N1.

[0159] The first switch MA to the fifth transistor M5 may all be P-type thin film transistors.

[0160] Please also see Figures 1 to 6 as well as Figures 8 to 9 When the gate driving circuit 1 operates in the forward scanning mode, the first signal line L1 transmits a high level signal, and the second signal line L2 transmits a low level signal.

[0161] In the first time period T1, the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a low level, the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a high level, the first clock signal is a high level, and the second clock signal is a low level.

[0162] At this time, the second control terminal SW2 in the m-th shift register unit 10 arranged along the first direction X is connected to the low level output by the scan signal output terminal OUT of the previous stage shift register unit 10, the second input selection unit 16 where the second control terminal SW2 is located is turned on, the first control terminal SW1 in the m-th shift register unit 10 is connected to the high level output by the scan signal output terminal OUT of the next stage shift register unit 10, and the first input selection unit 15 where the first control terminal SW1 is located is turned off.

[0163] That is, the second input selection unit 16 in the mth shift register unit 10 is turned on, the first input selection unit 15 is turned off, the second input selection unit 16 writes the low level signal transmitted by the second signal line L2 into the third node N3, the third transistor M3 is turned on by the constant voltage low level control, the low level of the third node N3 is transmitted to the first node N1 through the third transistor M3, and the first node N1 is also at a low level.

[0164] The first node N1 maintains a low level, so the seventh transistor M7 in the output control module 13 is turned on. The third node N3 maintains a low level, so the fifth transistor M5 is turned on, and the low level signal transmitted by the second clock signal line CK can be transmitted to the second node N2 via the fifth transistor M5. The control end of the fourth transistor M4 is electrically connected to the second clock signal line CK, and the second clock signal line CK outputs a low level to turn on the fourth transistor M4, and the constant voltage low level can be transmitted to the second node N2 via the fourth transistor M4, thereby controlling the sixth transistor M6 in the output control module 13 to turn on, and the constant voltage high level and the high level output by the first clock signal line XCK are combined as the scan signal SCAN and output via the scan signal output end OUT.

[0165] In a third period T3 between the first period T1 and the second period T2, the first clock signal line XCK transmits a low level signal, the second clock signal line CK transmits a high level signal, the fourth transistor M4 is turned off, and the first transistor M1 is turned on.

[0166] The scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a high level, the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a high level, and the first input selection unit 15 and the second input selection unit 16 in the mth shift register unit 10 arranged along the first direction X are both turned off.

[0167] During this period, the second capacitor C2 maintains the first node N1 at a low level, the seventh transistor M7 is turned on, and the low level signal transmitted by the first clock signal line XCK is output as the scan signal SCAN through the scan signal output terminal OUT.

[0168] Since the third transistor M3 is turned on, the low level maintained by the first node N1 is transmitted to the third node N3 via the third transistor M4, and the third node N3 also maintains a low level. The fifth transistor M5 is turned on, and the high level transmitted by the second clock signal line CK is written into the second node N2 via the fifth transistor M5, so that the second transistor M2 and the sixth transistor M6 are turned off.

[0169] In the second period T2, the first clock signal line XCK transmits a high level, the second clock signal line CK transmits a low level, the first transistor M1 is turned off, and the fourth transistor M4 is turned on. The constant voltage low level is written into the second node N2 via the fourth transistor M4, the sixth transistor M6 is turned on, the first capacitor C1 acts to maintain the second node N2 at a low level, and the constant voltage high level is outputted via the sixth transistor M6 and the scan signal output terminal OUT in sequence.

[0170] During this period, the scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X is electrically connected to the first control terminal SW1 in the mth shift register unit 10, the first control terminal SW1 is connected to a low level signal, and the first input selection unit 15 in the mth shift register unit 10 is turned on. The scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X is electrically connected to the second control terminal SW2 in the mth shift register unit 10, the second control terminal SW2 is connected to a high level signal, and the second input selection unit 16 in the mth shift register unit 10 is turned off. The high level signal transmitted by the first signal line L1 is written into the third node N3 through the first input selection unit 15, the third node N3 and the first node N1 maintain a high level, and the seventh transistor M7 and the fifth transistor M5 are turned off.

[0171] Please continue to see Figures 1 to 5 as well as Figures 7 to 9 When the gate driving circuit operates in the reverse scanning mode, the first signal line L1 transmits a low level signal, and the second signal line L2 transmits a high level signal.

[0172] In the first time period T1, along the first direction X, the scan signal output terminal OUT of the m-1th shift register unit 10 outputs a high level, the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a low level, the first clock signal is a high level, and the second clock signal is a low level.

[0173] At this time, the first control terminal SW1 of the mth shift register unit 10 arranged along the first direction X is electrically connected to the scan signal output terminal OUT of the m+1th shift register unit 10, the first control terminal SW1 is connected to a low level signal, and the first input selection unit 15 where the first control terminal SW1 of the mth shift register unit 10 is located is turned on. The second control terminal SW2 of the mth shift register unit 10 is electrically connected to the scan signal output terminal OUT of the m-1th shift register unit 10, the second control terminal SW2 is connected to a high level signal, and the second input selection unit 16 where the second control terminal SW2 of the mth shift register unit 10 is located is turned off.

[0174] That is, the first input selection unit 15 in the mth shift register unit 10 is turned on, and the second input selection unit 16 is turned off. The first input selection unit 15 writes the low-level signal transmitted by the first signal line L1 into the third node N3. The third transistor M3 is turned on by the constant voltage low-level control. The low level of the third node N3 is transmitted to the first node N1 through the third transistor M3, and the first node N1 is also at a low level.

[0175] The first node N1 maintains a low level, so the seventh transistor M7 in the output control module 13 is turned on. The third node N3 maintains a low level, so the fifth transistor M5 is turned on, and the low level signal transmitted by the second clock signal line CK can be transmitted to the second node N2 via the fifth transistor M5. The control end of the fourth transistor M4 is electrically connected to the second clock signal line CK, and the second clock signal line CK outputs a low level to turn on the fourth transistor M4, and the constant voltage low level is transmitted to the second node N2 via the fourth transistor M4, thereby controlling the sixth transistor M6 in the output control module 13 to turn on, and the constant voltage high level and the high level output by the first clock signal line XCK are combined as the scan signal SCAN and output via the scan signal output end OUT.

[0176] In a third period T3 between the first period T1 and the second period T2, the first clock signal line XCK transmits a low level signal, the second clock signal line CK transmits a high level signal, the fourth transistor M4 is turned off, and the first transistor M1 is turned on.

[0177] The scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X outputs a high level, the scan signal output terminal OUT of the m+1th shift register unit 10 outputs a high level, and the first input selection unit 15 and the second input selection unit 16 in the mth shift register unit 10 arranged along the first direction X are both turned off.

[0178] During this period, the second capacitor C2 maintains the first node N1 at a low level, the seventh transistor M7 is turned on, and the low level signal transmitted by the first clock signal line XCK is output as the scan signal SCAN through the scan signal output terminal OUT.

[0179] Since the third transistor M3 is turned on, the low level maintained by the first node N1 is transmitted to the third node N3 via the third transistor M4, so that the third node N3 also maintains a low level, the fifth transistor M5 is turned on, and the high level transmitted by the second clock signal is written into the second node N2 via the fifth transistor M5, so that the second transistor M2 and the sixth transistor M6 are turned off.

[0180] In the second period T2, the first clock signal line XCK transmits a high level, the second clock signal line CK transmits a low level, the first transistor M1 is turned off, and the fourth transistor M4 is turned on. The constant voltage low level is written into the second node N2 via the fourth transistor M4, the sixth transistor M6 is turned on, the first capacitor C1 acts to maintain the second node N2 at a low level, and the constant voltage high level is outputted via the sixth transistor M6 and the scan signal output terminal OUT in sequence.

[0181] During this period, the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X controls the second control terminal SW2 in the mth shift register unit 10 to be electrically connected, the second control terminal SW2 is connected to a low level signal, and the second input selection unit 16 in the mth shift register unit 10 is turned on. The scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X is electrically connected to the first control terminal SW1 in the mth shift register unit 10, the first control terminal SW1 is connected to a high level signal, and the first input selection unit 15 in the mth shift register unit 10 is turned off. The high level signal transmitted by the second signal line L2 is written into the third node N3 through the first input selection unit 15, the third node N3 and the first node N1 maintain a high level, and the seventh transistor M7 and the fifth transistor M5 are turned off.

[0182] In these embodiments, by coordinating the timing of each signal and combining the settings of the components in each module in the shift register unit 10, an optional implementation scheme is provided for the gate drive circuit 1 to achieve compatibility with the forward and reverse scan modes, thereby ensuring the normal output of the scan signal SCAN of each level of the shift register unit 10 under different scan modes.

[0183] Please see Fig.10 An embodiment of the present application further provides a display panel, which may include a gate driving circuit, and the gate driving circuit may be configured as the gate driving circuit provided in the aforementioned embodiment of the present application.

[0184] In some optional examples of the display panel of the present application embodiment, please refer to Figures 11 to 13 The display panel may further include a plurality of forward and reverse scan selection modules 110 and a plurality of pixel rows 100 .

[0185] The pixel row 100 may include a plurality of sub-pixels P, and the plurality of sub-pixels P may be arranged along a row direction Y. The sub-pixel P may include a pixel circuit 120 and a light emitting element 130 . The pixel circuit 120 is used to drive the light emitting element 130 and provide a driving current for the light emitting element 130 .

[0186] The light-emitting element 130 may be a light-emitting diode (LED), an organic electroluminescence display (OLED) or others.

[0187] The forward and reverse scanning selection module 110 is a module capable of controlling the pixel circuit 120 to be suitable for the forward scanning mode or the reverse scanning mode. The forward and reverse scanning selection module 110 can be electrically connected to at least one pixel circuit 120 correspondingly.

[0188] For example, see Fig.11 , Fig.11 The optional circuit structure diagram of the gate driving circuit 1, the forward and reverse scanning selection module 110 and the pixel circuit 120 in the display panel of the embodiment of the present application is shown. The forward and reverse scanning selection module 110 can correspond to the pixel circuit 120 one by one. That is, each pixel circuit 120 is electrically connected to a forward and reverse scanning selection module 110, thereby helping to achieve precise control of the forward scanning mode or the reverse scanning mode.

[0189] For example, see Fig.12 , Fig.12 Another optional circuit structure schematic diagram of the gate drive circuit 1, the forward and reverse scan selection module 110 and the pixel circuit 120 in the display panel of the embodiment of the present application is shown. In this example, one of the forward and reverse scan selection modules 110 is electrically connected to the pixel circuits 120 of multiple sub-pixels P in a pixel row 100. That is, the pixel circuits 120 in a row of sub-pixels P can be electrically connected to the same forward and reverse scan selection module 110, and the number of forward and reverse scan selection modules 110 can be the same as the number of pixel rows 100. In this way, the setting of the forward and reverse scan selection module 110 can be reduced, and at the same time, the pixel circuit 120 can be suitable for the forward and reverse scan mode of the gate drive circuit 1.

[0190] Exemplarily, the forward and reverse scan selection module 110 may also be electrically connected to the pixel circuits 120 in another number (eg, two or three) of sub-pixels P in the pixel row 100 .

[0191] Please continue to see Figure 11 to Figure 12 The forward and reverse scan selection module 110 may include a forward and reverse scan selection output terminal 113 and a forward and reverse scan selection input terminal 114 .

[0192] The forward and reverse scan selection output terminal 113 of the forward and reverse scan selection module 110 is electrically connected to the pixel circuit 120 .

[0193] Along the first direction X, the scan signal output terminal OUT of the m+1th shift register unit 10 and the scan signal output terminal OUT of the m−1th shift register unit 10 are both electrically connected to the forward and reverse scan selection input terminal 114 of the forward and reverse scan selection module 110 .

[0194] That is, for a single pixel circuit 120 , the forward and reverse scan selection module 110 can selectively receive the scan signal SCAN output by the (m−1)th shift register unit 10 or the (m+1)th shift register unit 10 .

[0195] In this example, by electrically connecting the forward and reverse scan selection output terminal 113 to the pixel circuit 120, and electrically connecting the forward and reverse scan selection input terminal 114 to the scan signal output terminal OUT of the m+1th shift register unit 10 and the m-1th shift register unit 10 arranged along the first direction X, the pixel circuit 120 can cooperate with the gate drive circuit 1, so that the pixel circuit 120 is adapted to the forward scan mode and the reverse scan mode of the gate drive circuit 1.

[0196] It should be noted that the scanning signal SCAN outputted from the scanning signal output terminal OUT can control the pixel circuit 120, for example, it can control the pixel circuit 120 to enter the initialization phase, or it can control the data signal to be written into the pixel circuit 120, and it can also realize the compensation control of the transistor threshold voltage.

[0197] Please see Fig.13 and Fig.14 , Fig.14 Another optional module structure diagram of the forward and reverse scan selection module 110, the pixel circuit 120 and the gate drive circuit 1 in the display panel of the embodiment of the present application is shown. In this example, the forward and reverse scan selection module 110 includes a first scan selection unit 111 and a second scan selection unit 112.

[0198] The first scan selection unit 111 includes a first scan input terminal A1, a first scan control terminal A2 and a first scan output terminal A3, and the second scan selection unit 112 includes a second scan input terminal B1, a second scan control terminal B2 and a second scan output terminal B3.

[0199] Among them, the above-mentioned first scan input terminal A1 and the second scan input terminal B1 can both be used to access the scan signal SCAN from the shift register unit 10, and the above-mentioned first scan output terminal A3 and the second scan output terminal B3 are the output terminals of the forward and reverse scan selection module 110, that is, the forward and reverse scan selection output terminal 113 can include the first scan output terminal A3 and the second scan output terminal B3, and the first scan output terminal A3 is electrically connected to the second scan output terminal B3.

[0200] The first scan input terminal A1 can be electrically connected to the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X, and the second scan input terminal B1 can be electrically connected to the scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X.

[0201] The first scan selection unit 111 and the second scan selection unit 112 can selectively output the scan signal SCAN connected to the first scan input terminal A1 or the second scan input terminal B1 in the forward and reverse scan selection module 110 to the pixel circuit 120 via the forward and reverse scan selection output terminal 113 .

[0202] The first scan control terminal A2 may be electrically connected to the first control signal line L3, and the second scan control terminal B2 may be electrically connected to the second control signal line L4.

[0203] The first control signal line L3 can write a low level or high level signal into the first scan control terminal A2, thereby controlling the first scan selection unit 111 in the forward and reverse scan selection module 110 to be turned on or off. The second control signal line L4 can write a low level or high level signal into the second scan control terminal B2, thereby controlling the second scan selection unit 112 in the forward and reverse scan selection module 110 to be turned on or off.

[0204] In this example, by electrically connecting the first scan control terminal A2 to the first control signal line L3, the first scan input terminal A1 is electrically connected to the scan signal output terminal OUT of the m-1th shift register unit 10 arranged along the first direction X, the second scan control terminal B2 is electrically connected to the second control signal line L4, and the second scan input terminal B1 is electrically connected to the scan signal output terminal OUT of the m+1th shift register unit 10 arranged along the first direction X, the first scan selection unit 111 and the second scan selection unit 112 can be selectively turned on according to the signal connected to the first scan control terminal A2 and the second scan control terminal B2, so that the forward and reverse scan selection module 110 can selectively output the scan signal SCAN output by the m-1th shift register unit 10 or the m+1th shift register unit 10 to the pixel circuit 120.

[0205] In these examples, by setting a first scan selection unit 111 and a second scan selection unit 112 in the forward and reverse scan selection module 110, and setting a corresponding scan input terminal, a scan control terminal and a scan output terminal for each scan selection unit, a detailed connection structure between the forward and reverse scan selection module 110 and the pixel circuit 120 and the gate drive circuit 1 is provided, which provides an optional implementation scheme for the pixel circuit 120 to adapt to the forward or reverse scan mode of the gate drive circuit 1, thereby improving the functional diversity of the display panel.

[0206] Please see Fig.13 , and please also refer to Fig.14 In some optional examples, the pixel circuit 120 may include a driving transistor 141 and a first initialization module 142 .

[0207] The output terminal of the first initialization module 142 may be electrically connected to the control electrode of the driving transistor 141. The control terminal of the first initialization module 142 may be electrically connected to the first scan output terminal A3 and the second scan output terminal B3.

[0208] The driving transistor 141 can be used to provide a driving current for the light emitting element 130 in the sub-pixel P. When the first initialization module 142 is turned on, the gate of the driving transistor 141 can be connected to the reset voltage signal Vref, and the pixel circuit 120 enters the initialization stage.

[0209] In these examples, the control end of the first initialization module 142 in the pixel circuit 120 is electrically connected to the first scan output end A3 and the second scan output end B3, so that the forward and reverse scan selection module 110 can input the scan signal SCAN connected from the m+1th shift register unit 10 or the m-1th shift register unit 10 arranged along the first direction X to the pixel circuit 120. The control end of the first initialization module 142 in the pixel circuit 120 is connected to the scan signal output by the shift register unit 10, which can control the pixel circuit 120 to enter the initialization stage, so that the pixel circuit 120 can adapt to the forward scan mode and the reverse scan mode of the gate drive circuit 1.

[0210] When the scan signal SCAN output by the m+1th shift register unit 10 or the m-1th shift register unit 10 arranged along the first direction X is input to the control end of the first initialization module 142, the first initialization module 142 in the pixel circuit 120 can be turned on, and the gate of the driving transistor 141 is connected to the reset voltage signal Vref for initialization, and the pixel circuit 120 enters the initialization stage.

[0211] In these examples, the circuit connection relationship between the internal driving transistor 141 of the pixel circuit 120 and the first initialization module 142, as well as the connection structure design between the first initialization module 142 and the forward and reverse scan selection module 110 in the pixel circuit 120 are given, which enables the gate driving circuit 1 to utilize the scanning signal SCAN output by different shift register units 10 to realize the initialization control of the driving transistor 141 in both the forward and reverse scan modes, thereby ensuring that the pixel circuit 120 in the display panel can smoothly enter the initialization stage, enabling the display panel to adapt to forward scanning and reverse scanning, thereby improving the applicability of the display panel.

[0212] Please note that Fig.15, and please also refer to Fig.13 and Fig.14 The first initialization module 142 in the pixel circuit 120 may include a first initialization transistor T01. In addition, the pixel circuit 120 may further include a data writing module 143, a first light emission control transistor T03, a second light emission control transistor T04 and a second initialization transistor T05.

[0213] The data writing module 143 may include a data writing transistor T02. The data writing transistor T02 is electrically connected to the first electrode of the driving transistor 141 and the data signal line. When the data writing transistor T02 is turned on, the gate of the driving transistor 141 may be controlled to write the data signal Vdata, so that the pixel circuit 120 enters the data writing phase.

[0214] The first light emitting control transistor T03 and the second light emitting control transistor T04 are arranged between the anode of the light emitting element 130 and the power signal line PVDD, and the control electrodes of the first light emitting control transistor T03 and the second light emitting control transistor T04 are electrically connected to the light emitting control signal line EM. The first light emitting control transistor T03 and the second light emitting control transistor T04 can control the light emitting element 130 to enter the light emitting stage.

[0215] The control electrode of the second initialization transistor T05 is electrically connected to the scan signal output terminal OUT of the mth shift register unit 10 arranged along the first direction X, and can be turned on when receiving a low level signal, so that the reset voltage signal Vref can initialize the anode of the light emitting element 130 .

[0216] In other examples, the first initialization module 142 and other circuits or modules in the pixel circuit 120 may also be set with reference to the pixel circuit 120 in the related art, which will not be elaborated herein.

[0217] Please also see Figures 11 to 16 , and please also refer to Figure 1 , Figure 3 , Figure 6 and Fig. 9 In the display panel of the embodiment of the present application provided based on the diagram, when the gate drive circuit 1 operates in the forward scanning mode, the first scanning selection unit 111 is turned on in response to the enable signal output by the first control signal line L3, and the second scanning selection unit 112 is turned off in response to the disable signal output by the second control signal line L4.

[0218] It should be noted that in the example of the display panel of the embodiment of the present application, the thin film transistors in the gate drive circuit 1 and the pixel circuit 120 are still P-type transistors for illustration. At this time, the above-mentioned enable signal is a low-level signal, and the above-mentioned non-enable signal is a high-level signal.

[0219] In the forward scanning mode, the first control signal line L3 transmits an enable signal to the control end of the first scanning selection unit 111, and the first scanning selection unit 111 is turned on. Thus, the first scanning selection unit 111 outputs the scanning signal SCAN output by the m-1th shift register unit 10 arranged along the first direction X connected to the first scanning input terminal A1 to the control end of the first initialization module 142.

[0220] On the contrary, the second control signal line L4 transmits a non-enable signal to the control terminal of the second scan selection unit 112, and the second scan selection unit 112 is turned off.

[0221] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the first scan selection unit 111 can be turned on when the gate drive circuit 1 operates in the forward scan mode, and then the scan signal SCAN output from the scan signal output end OUT of the m-1th shift register unit 10 is input to the control end of the first initialization module 142, so that the pixel circuit 120 can enter the initialization stage, thereby ensuring the normal initialization of the driving transistor 141 of each pixel circuit 120 when the gate drive circuit 1 operates in the forward scan mode.

[0222] Subsequently, in the next period, the data writing module 143 in the pixel circuit 120 is normally controlled to be turned on in combination with the scan signal output terminal OUT of the mth shift register unit 10 arranged along the first direction X, so that the driving transistor 141 can realize data writing. Therefore, the normal operation of the pixel circuit 120 in the display panel is guaranteed when the gate driving circuit 1 works in the forward scanning mode.

[0223] Please see Fig.17 Please continue to see Figure 1 , Figure 3 , Figure 7 , Fig. 9 as well as Figures 11 to 14 When the gate driving circuit 1 operates in the reverse scanning mode, the first scanning selection unit 111 is turned off in response to the non-enable signal output by the first control signal line L3, and the second scanning selection unit 112 is turned on in response to the enable signal output by the second control signal line L4.

[0224] That is, in the reverse scanning mode, the second control signal line L4 transmits an enable signal to the control end of the second scanning selection unit 112, and the second scanning selection unit 112 is turned on, thereby the second scanning selection unit 112 outputs the scanning signal SCAN output by the m+1th shift register unit 10 along the first direction X connected to the second scanning input terminal B1 to the control end of the first initialization module 142.

[0225] On the contrary, the first control signal line L3 sends a non-enable signal to the control terminal of the first scan selection unit 111, and the first scan selection unit 111 is turned off.

[0226] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the second scan selection unit 112 can be turned on when the gate drive circuit 1 operates in the reverse scan mode, and then the scan signal SCAN output from the scan signal output end OUT of the m+1th shift register unit 10 is transmitted to the control end of the first initialization module 142, so that the pixel circuit 120 can enter the initialization stage, thereby ensuring the normal initialization of the driving transistor 141 of each pixel circuit 120 when the gate drive circuit 1 operates in the reverse scan mode.

[0227] Subsequently, in the next period, the data writing module 143 in the pixel circuit 120 is normally controlled to be turned on in combination with the scan signal output terminal OUT of the mth shift register unit 10 arranged along the first direction X, so that the driving transistor 141 can realize data writing. Therefore, the normal operation of the pixel circuit 120 in the display panel is guaranteed when the gate driving circuit 1 works in the reverse scanning mode.

[0228] Please see Fig.18 , and please also refer to Figure 13 to Figure 14 The pixel circuit 120 may include a driving transistor 141 and a data writing module 143 .

[0229] The output terminal of the data writing module 143 may be electrically connected to the first electrode of the driving transistor 141. The control terminal of the data writing module 143 may be electrically connected to the first scanning output terminal A3 and the second scanning output terminal B3.

[0230] The driving transistor 141 can be used to provide a driving current for the light emitting element 130 in the sub-pixel P. When the data writing module 143 is turned on, the gate of the driving transistor 141 can write a data signal Vdata, and the pixel circuit 120 enters a data writing phase. The data writing module 143 can be a data writing transistor.

[0231] In these examples, the control end of the data writing module 143 in the pixel circuit 120 is electrically connected to the first scan output end A3 and the second scan output end B3, so that the forward and reverse scan selection module 110 can input the scan signal SCAN connected from the m+1th shift register unit 10 or the m-1th shift register unit 10 arranged along the first direction X to the pixel circuit 120. The control end of the data writing module 143 in the pixel circuit 120 is connected to the scan signal SCAN output by the shift register unit 10, which can control the pixel circuit 120 to enter the data writing stage, so that the pixel circuit 120 can adapt to the forward scan mode and the reverse scan mode of the gate drive circuit 1.

[0232] When the scan signal SCAN output by the m+1th shift register unit 10 or the m-1th shift register unit 10 arranged along the first direction X is transmitted to the control end of the data writing module 143, the data writing module 143 in the pixel circuit 120 can be turned on, and the data signal line can write the data signal Vdata to the gate of the driving transistor 141 through the data writing module 143, and the pixel circuit 120 enters the data writing stage.

[0233] In these examples, the circuit connection relationship between the internal driving transistor 141 and the data writing module 143 of the pixel circuit 120, as well as the connection structure design between the data writing module 143 and the forward and reverse scanning selection module 110 in the pixel circuit 120 are given, which enables the gate driving circuit 1 to utilize the scanning signal SCAN output by different shift register units 10 to realize the driving control of the pixel circuit 120 in both the forward and reverse scanning modes, thereby ensuring that the pixel circuit 120 in the display panel can smoothly enter the data writing stage, enabling the display panel to adapt to forward scanning and reverse scanning, thereby improving the applicability of the display panel.

[0234] Please note that Fig.19 , and please refer to the figure Fig.14 and Fig.18 The data writing module 143 in the pixel circuit 120 may include a data writing transistor T02. The data writing transistor T02 is electrically connected to the first electrode of the driving transistor 141 and the data signal line. When the data writing transistor T02 is turned on, the gate of the driving transistor 141 may be controlled to write the data signal Vdata, so that the pixel circuit 120 enters the data writing stage.

[0235] In addition, the pixel circuit 120 may further include a first light emission control transistor T03 , a second light emission control transistor T04 , a first initialization transistor T01 , and a second initialization transistor T05 .

[0236] The first light-emitting control transistor T03 and the second light-emitting control transistor T04 are arranged between the anode of the light-emitting element 130 and the power signal line PVDD, and the control electrodes of the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are electrically connected to the light-emitting control signal line EM. When the control terminals of the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are connected to the light-emitting control signal of a low level, the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are turned on, and the light-emitting element 130 can be controlled to enter the light-emitting stage.

[0237] The output terminal of the first initialization transistor T01 is electrically connected to the gate of the driving transistor 141, and the control electrode of the first initialization transistor T01 is electrically connected to the scan signal output terminal OUT of the mth shift register unit 10 along the first direction X. When the scan signal output terminal OUT of the mth shift register unit 10 outputs a low-level scan signal SCAN, the first initialization transistor T01 is turned on, the reset voltage signal Vref is used to initialize the gate of the driving transistor, and the pixel circuit 120 enters the initialization stage.

[0238] The output end of the second initialization transistor T05 is electrically connected to the anode of the light emitting element 130, and the control end of the second initialization transistor T05 can be electrically connected to the data writing transistor T02, or the control end of the second initialization transistor T05 can also be electrically connected to the control end of the first initialization transistor T01. In some optional examples, the second initialization transistor T05 can also be controlled by an independent scan signal SCAN. The second initialization transistor T05 is turned on when receiving a low level signal, and the reset voltage signal Vref can initialize the anode of the light emitting element 130.

[0239] In other examples, the data writing module 143 and other circuits or modules in the pixel circuit 120 may be set with reference to the pixel circuit 120 in the related art, which will not be elaborated herein.

[0240] For some optional examples, see Figures 18 to 20 , and please also refer to Figure 1 , Figure 3 , Figure 6 , Fig. 9 as well as Fig.11 , Fig.12 , Fig.14 .

[0241] When the gate driving circuit 1 operates in the forward scanning mode, the first scanning selection unit 111 is turned off in response to the disabling signal output by the first control signal line L3, and the second scanning selection unit 112 is turned on in response to the enabling signal output by the second control signal line L4.

[0242] That is, in the forward scanning mode, the second control signal line L4 transmits an enable signal to the control end of the second scanning selection unit 112, and the second scanning selection unit 112 is turned on, thereby the second scanning selection unit 112 outputs the scanning signal SCAN output by the m+1th shift register unit 10 along the first direction X connected to the second scanning input terminal B1 to the control end of the data writing module 143.

[0243] On the contrary, the first control signal line L3 transmits a non-enable signal to the control terminal of the first scan selection unit 111, and the first scan selection unit 111 is turned off.

[0244] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the second scan selection unit 112 can be turned on when the gate drive circuit 1 operates in the forward scan mode, and then the scan signal SCAN output from the scan signal output end OUT of the m+1th shift register unit 10 is input to the control end of the data writing module 143, so that the pixel circuit 120 can enter the data writing stage, thereby ensuring the normal writing of data in each pixel circuit 120 when the gate drive circuit 1 operates in the forward scan mode.

[0245] Combined with the initialization control of the first initialization module 142 in the current pixel circuit 120 by the scan signal output terminal OUT of the mth shift register unit 10 before the second scan selection unit 112 is turned on in the first direction X, the driving transistor 141 can be initialized. Therefore, the normal operation of the pixel circuit 120 in the display panel is generally guaranteed when the gate drive circuit 1 works in the forward scanning mode.

[0246] For some optional examples, see Fig.21 Please continue to see Figure 1 , Figure 3 , Figure 7 , Fig. 9 as well as Fig.11 , Fig.12 , Fig.14 as well as Figure 18 to Figure 19 .

[0247] When the gate driving circuit 1 operates in the reverse scanning mode, the first scanning selection unit 111 is turned on in response to the enable signal output by the first control signal line L3, and the second scanning selection unit 112 is turned off in response to the disable signal output by the second control signal line L4.

[0248] In the reverse scanning mode, the first control signal line L3 transmits an enable signal to the control end of the first scanning selection unit 111, and the first scanning selection unit 111 is turned on. Thus, the first scanning selection unit 111 outputs the scanning signal SCAN output by the m-1th shift register unit 10 along the first direction X connected to the first scanning input terminal A1 to the control end of the data writing module 143.

[0249] On the contrary, the second control signal line L4 transmits a non-enable signal to the control terminal of the second scan selection unit 112, and the second scan selection unit 112 is turned off.

[0250] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the first scan selection unit 111 can be turned on when the gate drive circuit 1 operates in the reverse scan mode, and then the scan signal SCAN output from the scan signal output end OUT of the m-1th shift register unit 10 is input to the control end of the data writing module 143, so that the pixel circuit 120 can enter the data writing stage, thereby ensuring the normal writing of data in each pixel circuit 120 when the gate drive circuit 1 operates in the reverse scan mode.

[0251] Combined with the initialization control of the first initialization module 142 in the current pixel circuit 120 by the scan signal output terminal OUT of the mth shift register unit 10 before the first scan selection unit 111 is turned on in the first direction X, the driving transistor 141 can be initialized. Therefore, the normal operation of the pixel circuit 120 in the display panel is generally guaranteed when the gate drive circuit 1 works in the reverse scan mode.

[0252] Please see Fig. 22 , and please also refer to Figure 13 to Figure 14 In some optional examples, the pixel circuit 120 may include a driving transistor 141 , a data writing module 143 , and a threshold compensation module 144 .

[0253] The output end of the data writing module 143 is electrically connected to the first electrode of the driving transistor 141 .

[0254] The control end of the data writing module 143 is electrically connected to the first scan output end A3 and the second scan output end B3.

[0255] An input terminal of the threshold compensation module 144 is electrically connected to the second electrode of the driving transistor 141 , and an output terminal of the threshold compensation module 144 is electrically connected to the control electrode of the driving transistor 141 .

[0256] The control terminal of the threshold compensation module 144 is electrically connected to the first scan output terminal A3 and the second scan output terminal B3.

[0257] The above-mentioned driving transistor 141 can be used to provide a driving current for the light-emitting element 130 in the sub-pixel P. Exemplarily, the first electrode of the driving transistor 141 can be the source of the driving transistor 141, the second electrode of the driving transistor 141 can be the drain of the driving transistor 141, and the control electrode can be the gate of the driving transistor 141.

[0258] When the data writing module 143 is turned on, the gate of the driving transistor 141 can be written with the data signal Vdata, and the pixel circuit 120 enters the data writing phase. The data writing module 143 can be a data writing transistor.

[0259] The threshold compensation module 144 can be used to compensate for the threshold voltage of the driving transistor 141. Exemplarily, the threshold compensation module 144 can be a threshold compensation transistor or others.

[0260] In these examples, the control end of the data writing module 143 and the control end of the threshold compensation module 144 in the pixel circuit 120 are electrically connected to the first scan output terminal A3 and the second scan output terminal B3, so that the forward and reverse scan selection module 110 can input the scan signal SCAN connected from the m+1th shift register unit 10 or the m-1th shift register unit 10 arranged along the first direction X to the pixel circuit 120. The control end of the data writing module 143 of the pixel circuit 120 and the control end of the threshold compensation module 144 are connected to the scan signal SCAN output by the shift register unit 10, which can control the driving transistor 141 in the pixel circuit 120 to write data, and the pixel circuit 120 enters the data writing stage. At the same time, the threshold compensation module 144 can also compensate for the threshold voltage of the driving transistor 141, thereby ensuring the operating stability of the driving transistor 141.

[0261] In these examples, the circuit connection relationship between the driving transistor 141, the data writing module 143 and the threshold compensation module 144 inside the pixel circuit 120 is given, as well as the connection structure design of the data writing module 143, the threshold compensation module 144 and the forward and reverse scanning selection module 110 in the pixel circuit 120, which enables the gate driving circuit 1 to use the scanning signal SCAN output by different shift register units 10 to realize the driving control of the pixel circuit 120, ensuring that the pixel circuit 120 in the display panel can smoothly enter the data writing stage, so that the display panel can adapt to forward scanning and reverse scanning, thereby improving the applicability of the display panel. Moreover, the connection design of the threshold compensation module 144 and the forward and reverse scanning selection module 110 enables the forward and reverse scanning compatible design of the gate driving circuit 1 to adapt to various types of pixel circuits 120, while ensuring the operating stability of the driving transistor 141 during the data writing process.

[0262] Please note that Figure 22 to Figure 23 , and please also refer to Fig.14 The data writing module 143 in the pixel circuit 120 may include a data writing transistor T02. The data writing transistor T02 is electrically connected to the first electrode of the driving transistor 141 and the data signal line. When the data writing transistor T02 is turned on, the gate of the driving transistor 141 may be controlled to write the data signal Vdata, so that the pixel circuit 120 enters the data writing stage.

[0263] The threshold compensation module 144 may include a threshold compensation transistor T06, which is electrically connected to the second electrode and the gate of the driving transistor 141. When the threshold compensation transistor T06 is turned on, the threshold voltage of the driving transistor 141 may be compensated.

[0264] In addition, the pixel circuit 120 may further include a first light emission control transistor T03 , a second light emission control transistor T04 , a first initialization transistor T01 , and a second initialization transistor T05 .

[0265] The first light-emitting control transistor T03 and the second light-emitting control transistor T04 are arranged between the anode of the light-emitting element 130 and the power signal line PVDD, and the control electrodes of the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are electrically connected to the light-emitting control signal line EM. When the control terminals of the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are connected to the light-emitting control signal of a low level, the first light-emitting control transistor T03 and the second light-emitting control transistor T04 are turned on, and the light-emitting element 130 can be controlled to enter the light-emitting stage.

[0266] The output terminal of the first initialization transistor T01 is electrically connected to the gate of the driving transistor 141, and the control electrode of the first initialization transistor T01 is electrically connected to the scan signal output terminal OUT of the mth shift register unit 10 along the first direction X. When the scan signal output terminal OUT of the mth shift register unit 10 outputs a low-level scan signal SCAN, the first initialization transistor T01 is turned on, the reset voltage signal Vref is used to initialize the gate of the driving transistor, and the pixel circuit 120 enters the initialization stage.

[0267] The output end of the second initialization transistor T05 is electrically connected to the anode of the light emitting element 130 . The second initialization transistor T05 is turned on when receiving a low level signal. The reset voltage signal Vref can initialize the anode of the light emitting element 130 .

[0268] In other examples, the data writing module 143, the threshold compensation module 144 and other circuits or modules in the pixel circuit 120 may be set with reference to the pixel circuit 120 in the related art, which will not be elaborated herein.

[0269] Please continue to see Figure 20 to Figure 23 as well as Figure 1 , Figure 3 , Figure 6 , Fig. 9 as well as Fig.11 , Fig.12 , Fig.14 In some optional examples, when the gate drive circuit 1 operates in the forward scanning mode, the first scanning selection unit 111 is turned off in response to the non-enable signal output by the first control signal line L3, and the second scanning selection unit 112 is turned on in response to the enable signal output by the second control signal line L4.

[0270] That is, in the forward scanning mode, the second control signal line L4 transmits an enable signal to the control end of the second scanning selection unit 112, and the second scanning selection unit 112 is turned on. Thus, the second scanning selection unit 112 outputs the scanning signal SCAN output by the m+1th shift register unit 10 along the first direction X connected to the second scanning input terminal B1 to the control end of the data writing module 143 and the control end of the threshold compensation module 144.

[0271] On the contrary, the first control signal line L3 transmits a non-enable signal to the control terminal of the first scan selection unit 111, and the first scan selection unit 111 is turned off.

[0272] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the second scan selection unit 112 can be turned on when the gate drive circuit 1 works in the forward scan mode, and then the scan signal SCAN output by the scan signal output end OUT of the m+1th shift register unit 10 is input to the control end of the data writing module 143 and the control end of the threshold compensation module 144, so that the pixel circuit 120 can enter the data writing stage, thereby ensuring the normal writing of data of each pixel circuit 120 when the gate drive circuit 1 works in the forward scan mode. At the same time, the threshold compensation module 144 can be turned on to ensure the stable operation of the driving transistor 141.

[0273] Combined with the initialization control of the first initialization module 142 in the current pixel circuit 120 by the scan signal output terminal OUT of the mth shift register unit 10 before the second scan selection unit 112 is turned on in the first direction X, the driving transistor 141 can be initialized. Therefore, the normal operation of the pixel circuit 120 in the display panel is generally guaranteed when the gate drive circuit 1 works in the forward scanning mode.

[0274] Please continue to see Figure 20 to Figure 23 Please continue to see Figure 1 , Figure 3 , Figure 7 , Fig. 9 as well as Fig.11 , Fig.12 as well as Fig.14 In some optional examples, when the gate driving circuit 1 operates in the reverse scanning mode, the first scanning selection unit 111 is turned on in response to the enable signal output by the first control signal line L3, and the second scanning selection unit 112 is turned off in response to the disable signal output by the second control signal line L4.

[0275] That is, in the reverse scanning mode, the first control signal line L3 transmits an enable signal to the control end of the first scanning selection unit 111, and the first scanning selection unit 111 is turned on, thereby the first scanning selection unit 111 outputs the scanning signal SCAN output by the m-1th shift register unit 10 along the first direction X connected to the first scanning input terminal A1 to the control end of the data writing module 143 and the control end of the threshold compensation module 144.

[0276] On the contrary, the second control signal line L4 transmits a non-enable signal to the control terminal of the second scan selection unit 112, and the second scan selection unit 112 is turned off.

[0277] In these examples, by applying different signals to the control end of the first scan selection unit 111 and the control end of the second scan selection unit 112, the first scan selection unit 111 can be turned on when the gate drive circuit 1 operates in the reverse scan mode, and then the scan signal SCAN output by the scan signal output end OUT of the m-1th shift register unit 10 is input to the control end of the data writing module 143 and the control end of the threshold compensation module 144, so that the pixel circuit 120 can enter the data writing stage, thereby ensuring the normal writing of data to each pixel circuit 120 when the gate drive circuit 1 operates in the reverse scan mode, and also ensuring the stability of the driving transistor 141 in the pixel circuit 120, so that the forward and reverse scan modes can be adapted to different types of pixel circuits 120.

[0278] Combined with the initialization control of the first initialization module 142 in the current pixel circuit 120 by the scan signal output terminal OUT of the mth shift register unit 10 before the first scan selection unit 111 is turned on in the first direction X, the driving transistor 141 can be initialized. Therefore, the normal operation of the pixel circuit 120 in the display panel is generally guaranteed when the gate drive circuit 1 works in the reverse scan mode.

[0279] Please continue to see Fig.13 , Fig.15 , Fig.18 , Fig.19 as well as Figure 22 to Figure 23 , and please also refer to Fig.11 , Fig.12 as well as Fig.14 The first scan selection unit 111 includes a first scan selection switch M8, an input end of the first scan selection switch M8 is a first scan input end A1, a control end of the first scan selection switch M8 is a first scan control end A2, and an output end of the first scan selection switch M8 is a first scan output end A3.

[0280] The second scan selection unit 112 includes a second scan selection switch M9, an input end of the second scan selection switch M9 is a second scan input end B1, a control end of the second scan selection switch M9 is a second scan control end B2, and an output end of the second scan selection switch M9 is a second scan output end B3.

[0281] Exemplarily, the scan signal output terminal OUT of the m-1th shift register unit 10 along the first direction X can be electrically connected to the input terminal of the first scan selection switch M8, the output terminal of the first scan selection switch M8 can be electrically connected to the control terminal of the data writing module 143 in the pixel circuit 120, and the output terminal of the first scan selection switch M8 can also be electrically connected to the control terminal of the threshold compensation module 144.

[0282] The scan signal output end OUT of the m+1th shift register unit 10 along the first direction X can be electrically connected to the input end of the second scan selection switch M9, the output end of the second scan selection switch M9 can be electrically connected to the control end of the data writing module 143 in the pixel circuit 120, and the output end of the second scan selection switch M9 can also be electrically connected to the control end of the threshold compensation module 144.

[0283] Alternatively, in other examples, the scan signal output terminal OUT of the m-1th shift register unit 10 along the first direction X can be electrically connected to the input terminal of the first scan selection switch M8, and the output terminal of the first scan selection switch M8 can be electrically connected to the control terminal of the first initialization module 142 in the pixel circuit 120.

[0284] The scan signal output terminal OUT of the (m+1)th shift register unit 10 along the first direction X can be electrically connected to the input terminal of the second scan selection switch M9 , and the output terminal of the second scan selection switch M9 can be electrically connected to the control terminal of the first initialization module 142 in the pixel circuit 120 .

[0285] The first scan selection switch M8 and the second scan selection switch M9 may be thin film field effect transistors, and the types of the first scan selection switch M8 and the second scan selection switch M9 may be set according to actual needs. Exemplarily, the first scan selection switch M8 and the second scan selection switch M9 are both P-type thin film field effect transistors.

[0286] The present application also provides a display device. Fig.24 The display device may be a PC, a television, a monitor, a mobile terminal, a tablet computer, a wearable device, etc. The display device may include the display panel provided in the embodiment of the present application.

[0287] It should be noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus.

[0288] This article uses specific examples to illustrate the principles and implementation methods of this application. The above examples are only used to help understand the methods and core ideas of this application. The above are only preferred implementation methods of this application. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concepts and technical solutions of this application to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A gate drive circuit, characterized in that: include: n shift register units arranged along a first direction; The shift register unit includes an input module, a first node control module, a second node control module and an output control module; The input module, the first node control module and the second node control module are all electrically connected to the third node, the first node control module is used to control the level of the first node, the second node control module is used to control the level of the second node, and the output control module is electrically connected to the scan signal output terminal, the first node and the second node, and is used to control the scan signal output terminal to output the scan signal according to the level of the first node and the level of the second node; Along the first direction, the control end of the input module of the mth shift register unit is electrically connected to the scan signal output end of the m+1th shift register unit and the scan signal output end of the m-1th shift register unit, respectively, m∈n; The input module includes a first input selection unit and a second input selection unit, wherein the first input selection unit included in the mth shift register unit is electrically connected to the scan signal output end of the m+1th shift register unit, and the second input selection unit included in the mth shift register unit is electrically connected to the scan signal output end of the m-1th shift register unit.

2. The gate driving circuit according to claim 1, characterized in that: Along the first direction, the control end of the input module in the first shift register unit is electrically connected to the start transmission signal line; The control end of the input module in the nth shift register unit is electrically connected to the start transmission signal line.

3. The gate driving circuit according to claim 1, characterized in that: The first input selection unit includes a first input terminal, a first output terminal and a first control terminal, and the second input selection unit includes a second input terminal, a second output terminal and a second control terminal; The first input terminal is electrically connected to the first signal line, the first output terminal is electrically connected to the third node, The second input terminal is electrically connected to the second signal line, and the second output terminal is electrically connected to the third node; Along the first direction, the first control end of the mth shift register unit is electrically connected to the scan signal output end of the m+1th shift register unit, and the second control end of the mth shift register unit is electrically connected to the scan signal output end of the m-1th shift register unit.

4. The gate driving circuit according to claim 3, characterized in that: When the gate driving circuit operates in a forward scanning mode, the first signal line transmits a high level signal, and the second signal line transmits a low level signal.

5. The gate driving circuit according to claim 4, characterized in that: The gate drive circuit includes a first period and a second period when operating in a forward scanning mode; In the first period, in the mth shift register unit, the second control terminal is turned on in response to the enable signal output by the scan signal output terminal of the m-1th shift register unit, and the first control terminal is turned off in response to the disable signal output by the scan signal output terminal of the m+1th shift register unit, so as to write the low level signal into the first node; In the second time period, in the mth shift register unit, the second control end is cut off in response to the non-enable signal output by the scan signal output end of the m-1th shift register unit, and the first control end is turned on in response to the enable signal output by the scan signal output end of the m+1th shift register unit, so as to write the high-level signal into the first node.

6. The gate driving circuit according to claim 3, characterized in that: When the gate driving circuit operates in a reverse scanning mode, the first signal line transmits a low level signal, and the second signal line transmits a high level signal.

7. The gate driving circuit according to claim 6, characterized in that: The gate driving circuit includes a first period and a second period when operating in a reverse scanning mode; In the first period, in the mth shift register unit, the first control terminal is turned on in response to the enable signal output by the scan signal output terminal of the m+1th shift register unit, and the second control terminal is turned off in response to the disable signal output by the scan signal output terminal of the m-1th shift register unit, so as to write the low level signal into the first node; In the second time period, in the mth shift register unit, the first control end is cut off in response to the non-enable signal output by the scan signal output end of the m+1th shift register unit, and the second control end is turned on in response to the enable signal output by the scan signal output end of the m-1th shift register unit, so as to write the high-level signal into the first node.

8. The gate driving circuit according to claim 3, characterized in that: The first input selection unit includes a first switch, the input end of the first switch is the first input end, the output end of the first switch is the first output end, and the control end of the first switch is the first control end; The second input selection unit includes a second switch, an input end of the second switch is the second input end, an output end of the second switch is the second output end, and a control end of the second switch is the second control end.

9. A display panel, characterized in that: The display panel includes a gate driving circuit, and the gate driving circuit is configured as the gate driving circuit according to any one of claims 1 to 8.

10. The display panel according to claim 9, characterized in that: The display panel further comprises a plurality of forward and reverse scanning selection modules and a plurality of pixel rows, wherein the pixel rows comprise a plurality of sub-pixels, and the sub-pixels comprise pixel circuits and light-emitting elements; One of the forward and reverse scanning selection modules is electrically connected to at least one of the pixel circuits; The forward and reverse scanning selection module comprises a forward and reverse scanning selection output terminal and a forward and reverse scanning selection input terminal; The forward and reverse scan selection output terminal of the forward and reverse scan selection module is electrically connected to the pixel circuit; Along the first direction, the scan signal output end of the m+1th shift register unit and the scan signal output end of the m-1th shift register unit are both electrically connected to the forward and reverse scan selection input end of the forward and reverse scan selection module.

11. The display panel according to claim 10, characterized in that: The forward and reverse scan selection module includes a first scan selection unit and a second scan selection unit; the first scan selection unit includes a first scan input terminal, a first scan control terminal and a first scan output terminal, and the second scan selection unit includes a second scan input terminal, a second scan control terminal and a second scan output terminal; the forward and reverse scan selection output terminal includes the first scan output terminal and the second scan output terminal, and the first scan output terminal is electrically connected to the second scan output terminal; the forward and reverse scan selection input terminal includes the first scan input terminal and the second scan input terminal; Along the first direction, the scan signal output end of the m-1th shift register unit is electrically connected to the first scan input end, and the scan signal output end of the m+1th shift register unit is electrically connected to the second scan input end; The first scanning control terminal is electrically connected to the first control signal line; The second scanning control terminal is electrically connected to the second control signal line.

12. The display panel according to claim 11, characterized in that: The pixel circuit includes a driving transistor and a first initialization module; The output end of the first initialization module is electrically connected to the control electrode of the driving transistor; The control end of the first initialization module is electrically connected to the first scan output end and the second scan output end.

13. The display panel according to claim 12, characterized in that: When the gate driving circuit operates in a forward scanning mode, the first scanning selection unit is turned on in response to an enable signal output by the first control signal line, and the second scanning selection unit is turned off in response to a disable signal output by the second control signal line.

14. The display panel according to claim 12, characterized in that: When the gate driving circuit operates in a reverse scanning mode, the first scanning selection unit is turned off in response to a non-enable signal output by the first control signal line, and the second scanning selection unit is turned on in response to an enable signal output by the second control signal line.

15. The display panel according to claim 11, characterized in that: The pixel circuit includes a driving transistor and a data writing module; The output end of the data writing module is electrically connected to the first electrode of the driving transistor; The control end of the data writing module is electrically connected to the first scanning output end and the second scanning output end.

16. The display panel according to claim 15, characterized in that: When the gate driving circuit operates in a forward scanning mode, the first scanning selection unit is turned off in response to a non-enable signal output by the first control signal line, and the second scanning selection unit is turned on in response to an enable signal output by the second control signal line.

17. The display panel according to claim 15, characterized in that: When the gate driving circuit operates in a reverse scanning mode, the first scanning selection unit is turned on in response to an enable signal output by the first control signal line, and the second scanning selection unit is turned off in response to a disable signal output by the second control signal line.

18. The display panel according to claim 11, characterized in that: The pixel circuit includes a driving transistor, a data writing module and a threshold compensation module; The output end of the data writing module is electrically connected to the first electrode of the driving transistor; The control end of the data writing module is electrically connected to the first scanning output end and the second scanning output end; The input end of the threshold compensation module is electrically connected to the second electrode of the driving transistor, and the output end of the threshold compensation module is electrically connected to the control electrode of the driving transistor; The control end of the threshold compensation module is electrically connected to the first scan output end and the second scan output end.

19. The display panel according to claim 18, characterized in that: When the gate driving circuit operates in a forward scanning mode, the first scanning selection unit is turned off in response to a non-enable signal output by the first control signal line, and the second scanning selection unit is turned on in response to an enable signal output by the second control signal line.

20. The display panel according to claim 18, characterized in that: When the gate driving circuit operates in a reverse scanning mode, the first scanning selection unit is turned on in response to an enable signal output by the first control signal line, and the second scanning selection unit is turned off in response to a disable signal output by the second control signal line.

21. The display panel according to claim 11, characterized in that: The first scan selection unit comprises a first scan selection switch, the input end of the first scan selection switch is the first scan input end, the control end of the first scan selection switch is the first scan control end, and the output end of the first scan selection switch is the first scan output end; The second scan selection unit includes a second scan selection switch, the input end of the second scan selection switch is the second scan input end, the control end of the second scan selection switch is the second scan control end, and the output end of the second scan selection switch is the second scan output end.

22. The display panel according to claim 10, characterized in that: One of the forward and reverse scanning selection modules is electrically connected to one of the pixel rows.

23. The display panel according to claim 10, characterized in that: The forward and reverse scanning selection modules are electrically connected to the sub-pixels in a one-to-one correspondence.

24. A display device, characterized in that: The display device includes a display panel, and the display panel is configured as the display panel according to any one of claims 9 to 23.

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