Semiconductor power module and power conversion device

Abstract

A semiconductor power module is provided that improves the accuracy of overcurrent protection. A semiconductor power module in which a three-phase AC inverter is mounted within a package has first to third circuit patterns on which second, fourth, and sixth switching elements are mounted, respectively; a fourth circuit pattern on which first, third, and fifth switching elements are mounted; a second main electrode that is commonly connected to main electrode wiring of the second, fourth, and sixth switching elements; a second main electrode terminal that is connected to the second main electrode; a first main electrode that is electrically connected to the fourth circuit pattern; and a first main electrode terminal that is connected to the first main electrode, the second main electrode extending along one side of the package, the second main electrode terminal being disposed at an end portion in the extending direction of the second main electrode when viewed in plan view, and, with respect to the main electrode wiring of the second, fourth, and sixth switching elements, the closer the main electrode wiring is to the second main electrode terminal in the horizontal direction when viewed in plan view, the longer the main electrode wiring is.

Description

Technical Field

[0001] This invention relates to semiconductor power modules, and more particularly to semiconductor power modules with improved overcurrent protection accuracy. Background Technology

[0002] For semiconductor power modules with multiple transistor chips connected in parallel, a wire bonding-based connection method that uniformly achieves low inductance is disclosed, for example, in Patent Document 1.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-154079

[0004] The technology disclosed in Patent Document 1 targets a semiconductor power module in which multiple transistor chips are connected in parallel on the same circuit pattern, rather than a semiconductor power module in which a three-phase AC inverter is mounted in the same package.

[0005] When a three-phase AC inverter is installed in the same package, the following problem exists: the emitter electrode connected to the N terminal is common-connected. If load current flows through it, the power module will be cut off earlier than the specified value when the overcurrent protection operates due to the difference in wiring inductance of the common-connected emitter electrode. Summary of the Invention

[0006] The present invention is proposed to solve the above-mentioned problems, and its purpose is to provide a semiconductor power module with improved overcurrent protection accuracy.

[0007] The semiconductor power module of the present invention is a semiconductor power module in which a three-phase AC inverter is installed within a package. The three-phase AC inverter includes: a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a sixth switching element connected in series between a first main power line given a first potential and a second main power line given a second potential lower than the first potential; and a first freewheeling element, a second freewheeling element, a third freewheeling element, a fourth freewheeling element, a fifth freewheeling element, and a sixth freewheeling element connected in reverse parallel with the first to sixth switching elements, respectively. The semiconductor power module includes: a first circuit pattern, a second circuit pattern, and a third circuit pattern, which respectively mount the second switching element, the fourth switching element, and the sixth switching element; a fourth circuit pattern, which mounts the first switching element, the third switching element, and the fifth switching element; and a second main electrode, which is connected in parallel with the second switching element, the fourth switching element, and the sixth switching element. The main electrode wiring of each of the sixth switching elements is commonly connected; a second main electrode terminal is connected to the second main electrode; a first main electrode is electrically connected to the fourth circuit pattern; and a first main electrode terminal is connected to the first main electrode. The first, second, and third chip pads of the first to third circuit patterns, which respectively mount the second, fourth, and sixth switching elements, are arranged in a parallel row. The arrangement direction of the first, second, and third chip pads is along one side of the package. The second main electrode is arranged to extend along the side. The second main electrode terminal is located at the end of the extension direction of the second main electrode when viewed from above. The main electrode wiring of each of the second, fourth, and sixth switching elements is arranged such that the main electrode wiring that is closer to the second main electrode terminal in the horizontal direction when viewed from above is longer.

[0008] The effects of the invention

[0009] According to the semiconductor power module of the present invention, the main electrode wiring of the second switching element, the fourth switching element and the sixth switching element are arranged such that the main electrode wiring that is closer to the second main electrode terminal when viewed from above is longer. Therefore, the wiring inductance from the second switching element, the fourth switching element and the sixth switching element to the second main electrode can be made to be consistent, and a semiconductor power module with improved overcurrent protection accuracy can be obtained. Attached Figure Description

[0010] Figure 1 This is a top view showing the structure of the semiconductor power module according to Embodiment 1.

[0011] Figure 2 This is a cross-sectional view showing the structure of the semiconductor power module according to Embodiment 1.

[0012] Figure 3 This is a diagram showing the circuit structure of a semiconductor power module.

[0013] Figure 4 This is a diagram of an H-bridge circuit simulating the inverter operation of a three-phase AC inverter for a semiconductor power module.

[0014] Figure 5 This is a diagram of an H-bridge circuit simulating the inverter operation of a three-phase AC inverter for a semiconductor power module.

[0015] Figure 6 This is a graph showing the simulation results of spike-shaped noise voltage.

[0016] Figure 7 This is a diagram of an H-bridge circuit simulating the inverter operation of a three-phase AC inverter for a semiconductor power module.

[0017] Figure 8 This is a diagram of an H-bridge circuit simulating the inverter operation of a three-phase AC inverter for a semiconductor power module.

[0018] Figure 9 This is a graph showing the simulation results of spike-shaped noise voltage.

[0019] Figure 10 This is a graph showing the simulation results of spike-shaped noise voltage.

[0020] Figure 11 This is a graph showing the simulation results of spike-shaped noise voltage.

[0021] Figure 12 This is a top view showing the structure of the semiconductor power module according to Embodiment 2.

[0022] Figure 13 This is a top view showing the structure of the semiconductor power module according to Embodiment 3.

[0023] Figure 14 This is a block diagram showing the structure of the power conversion system according to Embodiment 4. Detailed Implementation

[0024] <Implementation Method 1>

[0025] Figure 1 This is a top view showing the structure of the semiconductor power module 100 according to Embodiment 1 of the present invention. Figure 2 yes Figure 1A sectional view along the XY lines in the vector direction. Furthermore, in Figure 1 In this design, the upper part of the resin casing RC is omitted for convenience, allowing for visual observation of the circuit pattern. Additionally, in... Figure 2 For convenience, the sealing resin filling inside the resin shell RC is omitted.

[0026] like Figure 2 As shown, the semiconductor power module 100 has an insulating substrate IB mounted on a base plate BP that forms the bottom of the resin housing RC.

[0027] like Figure 1 As shown, multiple circuit patterns are formed on the insulating substrate IB. Specifically, P-side collector circuit pattern PCP, N-side collector circuit patterns NCP1, NCP2, and NCP3 are formed.

[0028] The P-side collector circuit pattern PCP includes transistor chips 4, 5, and 6, and diode chips 14, 15, and 16. The N-side collector circuit pattern NCP1 includes transistor chip 1 and diode chip 11. The N-side collector circuit pattern NCP2 includes transistor chip 2 and diode chip 12. The N-side collector circuit pattern NCP3 includes transistor chip 3 and diode chip 13.

[0029] The emitter of transistor chip 4 and the anode of diode chip 14 are connected to the N-side collector circuit pattern NCP1 via wire WR. The emitter of transistor chip 6 and the anode of diode chip 16 are connected to the N-side collector circuit pattern NCP2 via wire WR. The emitter of transistor chip 5 and the anode of diode chip 15 are connected to the N-side collector circuit pattern NCP3 via wire WR.

[0030] The N-side collector circuit pattern NCP1 is electrically connected to the U terminal UT via the wire WR, the N-side collector circuit pattern NCP2 is electrically connected to the V terminal VT via the wire WR, and the N-side collector circuit pattern NCP3 is electrically connected to the W terminal WT via the wire WR. Furthermore, the U terminal UT, V terminal VT, and W terminal WT are exposed at the upper part of the resin housing RC.

[0031] The emitter of transistor chip 1 and the anode of diode chip 11 are connected to the N-side main electrode NM via emitter wire EW1. The emitter of transistor chip 2 and the anode of diode chip 12 are connected to the N-side main electrode NM via emitter wire EW2. The emitter of transistor chip 3 and the anode of diode chip 13 are connected to the N-side main electrode NM via emitter wire EW3. The N-side main electrode NM is exposed at the upper part of the resin housing RC as the N-terminal NT of the semiconductor power module 100.

[0032] The P-side collector circuit pattern PCP is connected to the P-side main electrode PM via a wire WR. The P-side main electrode PM is exposed as the P terminal PT of the semiconductor power module 100 in the upper structure of the resin housing RC.

[0033] In addition, the sensing current terminals CS are respectively disposed on the emitter side of transistor chips 1 to 6 and are electrically connected to the relay terminal RT via wire WR.

[0034] In addition, gate terminals (not shown) are respectively disposed on the emitter side surface of transistor chips 1 to 6 and are electrically connected to relay terminals RT via wires WR.

[0035] like Figure 2 As shown, the relay terminal RT is electrically connected to the control circuit CC of the control substrate CB mounted on the insulating substrate IB within the semiconductor power module 100, and inputs the gate signal output from the control circuit CC to the transistor chip, or inputs the sensing current output from the sensing current terminal CS to the control circuit CC.

[0036] In addition, such as Figure 2 As shown, multiple connectors CN are provided on the upper structure of the resin housing RC for exchanging electrical signals between the control board CB and the outside during manufacturing, and guide pins GD are provided on both sides of the queue of multiple connectors CN to improve the insertability of the external connectors.

[0037] Figure 3 This is a diagram showing the circuit structure of the semiconductor power module 100. (As shown...) Figure 3 As shown, transistor chips 4 and 1, 5 and 2, and 6 and 3 are connected in series between the main power line PL (connected to the high-potential side, P-side, P terminal PT, which is connected to the positive terminal of the power supply PW) and the main power line NL (connected to the low-potential side, N terminal NT, which is connected to the negative terminal of the power supply PW). Additionally, a smoothing capacitor CX is connected in parallel with the power supply PW. Furthermore, the power supply PW is not installed in the semiconductor power module 100 but is located outside the module, receiving DC power from an external source via the P terminal PT and the N terminal NT.

[0038] The connection node between transistor chip 4 and transistor chip 1 is the U terminal UT of the output U phase, the connection node between transistor chip 5 and transistor chip 2 is the V terminal VT of the output V phase, and the connection node between transistor chip 6 and transistor chip 3 is the W terminal WT of the output W phase. Transistor chips 1 to 6 constitute a three-phase AC inverter.

[0039] In addition, diode chips 11 to 16 are connected in reverse parallel to transistor chips 1 to 6 respectively.

[0040] Transistor chips 1 to 6 are controlled by control circuits CC1, CC2, CC3, CC4, CC5, and CC6, respectively. For example, a gate signal is output from the gate terminal GT of control circuit CC4 and input to the gate of transistor chip 4. Additionally, the sensing current terminal CS of transistor chip 4 is input to the current sensing terminal SC of control circuit CC4. Figure 1 The sensing current is measured by the reference potential terminal GND of the control circuit CC4, which is connected to the U terminal UT.

[0041] like Figure 1 As shown, in the semiconductor power module 100, the emitter wires EW1, EW2, and EW3 of the transistor chips 1-3 with different collector potentials are configured such that the emitter wires that are closer to the N-terminal NT in the horizontal direction are longer. That is, the N-side collector circuit patterns NCP1, NCP2, and NCP3 are arranged in a row such that the chip pads DP1, DP2, and DP3 on which the transistor and diode chips are mounted are parallel to each other, and their arrangement direction is along the long side of the rectangular resin casing RC when viewed from above. Furthermore, the chip pads DP1-DP3 of the N-side collector circuit patterns NCP1, NCP2, and NCP3 are arranged at different heights. That is, the front end of the N-side main electrode NM side of chip pad DP1 is located at the position farthest from the N-side main electrode NM, the front end of the N-side main electrode NM side of chip pad DP3 is located at the position closest to the N-side main electrode NM, and the front end of the N-side main electrode NM side of chip pad DP2 is located between chip pad DP1 and chip pad DP3. In other words, chip pads DP1 to DP3 are arranged in a stepped configuration that decreases in height towards the N-terminal NT when viewed from above.

[0042] Furthermore, the N-terminal NT and the P-terminal PT are arranged along one short side of the resin housing RC, and the N-side main electrode NM extends along one long side of the resin housing RC, bending within the sidewall of the short side of the resin housing RC. Figure 2 The emitter wires EW1, EW2, and EW3 are exposed at the upper part of the resin housing RC. Therefore, when viewed from above, they are arranged in a row relative to the N terminal NT, with the emitter wires being the longest as they are closer to the N terminal NT in the horizontal direction parallel to the long side of the resin housing RC. More specifically, the emitter wire EW1, which is closest to the N terminal NT, is the longest, and the emitter wire EW3, which is farthest from the N terminal NT, is the shortest.

[0043] Furthermore, by arranging the N-terminal NT and the P-terminal PT adjacent to each other along one short side of the resin housing RC, the inductance of the N-side main electrode NM and the P-side main electrode can be reduced, thereby suppressing surge voltage.

[0044] In this way, by setting the chip pads DP1 to DP3 in a stepped configuration that decreases in height when viewed from above towards the N terminal NT, the emitter wires that are closer in the horizontal direction to the N terminal NT can have longer wire lengths. This allows for consistent parasitic inductance and identical wiring inductance, thereby improving the accuracy of overcurrent protection.

[0045] The mechanism for improving the accuracy of overcurrent protection is explained below. First, the sensing current terminal CS of each transistor chip is connected to the control board CB via a wire WR through a relay terminal RT. Figure 2 The current sensing terminal SC of the control circuit CC above.

[0046] The current sensing terminal SC is provided for detecting overcurrent and short-circuit current, monitoring the voltage between SC and GND. This is achieved through the current sensing terminals CS (located on transistor chips 1-6). Figure 1 A small current proportional to the collector current flows, for example, a sensing current of about 1 / 10000 of the collector current, causing the voltage between SC and GND to rise. If the voltage between SC and GND reaches a threshold, the overcurrent protection function of the control circuit CC is activated to implement overcurrent protection, which can cut off the overcurrent before the semiconductor power module 100 is damaged in the event of an overcurrent.

[0047] Here, as Figure 3 As shown, on the main power line NL, i.e., the N-side main electrode NM ( Figure 1 Parasitic inductance exists. The parasitic inductance of the N-side main electrode NM is set as L, starting from the inductance closest to the N-terminal NT. N1 L N2 L N3 Let the parasitic inductances of the emitter wires EW1, EW2, and EW3 on the N side be L respectively. UN L VN and L WN .

[0048] Next, Figure 4 , Figure 5 The diagram shows an H-bridge circuit simulating the inverter operation of a three-phase AC inverter for a semiconductor power module 100.

[0049] Figure 4The arrows indicate the current path when transistor chip 6 on the P side and transistor chip 1 on the N side are energized (conducted). The thick solid line indicates that the reference potential terminal GND on the N side above the control substrate CB is common. This common reference potential terminal GND pattern is called the GND pattern of the N-side emitter. Furthermore, in Figure 4 The diagram shows the current path via terminal U (UT), terminal V (VT), and terminal W (WT), but this is the current path via an external inductive load (not shown) connected to each terminal.

[0050] Figure 5 As indicated by the arrow, in Figure 4 The freewheeling current path after the three-phase AC inverter operates, and the power supply to transistor chip 6 is stopped, is shown by the thick solid line on the control substrate CB. Figure 2 The reference potential terminal GND on the N side above is a common case.

[0051] In Figure 4 After the current path causes the three-phase AC inverter to operate, if the power supply to transistor chip 6 is stopped, then... Figure 5 Such a freewheeling current. At this time, due to the parasitic inductance L existing in the path of the freewheeling current... N2 L N3 and L WM Due to the influence of the GND pattern of the N-side emitter on the control substrate CB, a potential difference is generated, resulting in a spike-shaped noise voltage between SC and GND of the control circuit CC1 connected to the transistor chip 1.

[0052] Figure 6 The simulation results for this spike-shaped noise voltage are shown in the figure. Figure 6 In the diagram, the horizontal axis is set to time (in arbitrary units), and the vertical axis is set to the voltage between SC and GND (in arbitrary units), illustrating the periodic generation of spike-shaped noise voltage SN. Here, as a simulation condition, it is assumed that... Figure 1 The emitter wires EW1, EW2, and EW3 shown are all of equal length, and the parasitic inductance L... UN L VN and L WN Set them to the same value.

[0053] The spike-shaped noise voltage can cause malfunctions in the overcurrent protection of the control circuit. Furthermore, the magnitude of the spike-shaped noise voltage depends on the parasitic inductance of the freewheeling path.

[0054] in addition, Figure 7 , Figure 8 The text shows the relationship between... Figure 4 , Figure 5The same inverter operation was simulated using an H-bridge circuit.

[0055] Figure 7 The arrows show the current path when transistor chip 4 on the P side and transistor chip 3 on the N side are energized (conducted). The thick solid line shows that the reference potential terminal GND on the N side above the control substrate CB is common.

[0056] Figure 8 As indicated by the arrow, in Figure 7 The freewheeling current path after the three-phase AC inverter operates, causing the power supply to transistor chip 4 to stop, is shown by the thick solid line on the control substrate CB. Figure 2 The reference potential terminal GND on the N side above is common.

[0057] In Figure 7 After the current path causes the three-phase AC inverter to operate, if the power supply to transistor chip 4 is stopped, then... Figure 8 Such a freewheeling current. At this time, due to the parasitic inductance L existing in the path of the freewheeling current... UN Due to the influence of the GND pattern of the N-side emitter on the control substrate CB, a potential difference is generated, resulting in a spike-shaped noise voltage between SC and GND of the control circuit CC3 connected to the transistor chip 3.

[0058] Figure 9 The simulation results for this spike-shaped noise voltage are shown in the figure. Figure 9 In the diagram, the horizontal axis is set to time (in arbitrary units), and the vertical axis is set to the voltage between SC and GND (in arbitrary units), illustrating the periodic generation of spike-shaped noise voltage SN. Here, as a simulation condition, it is assumed that... Figure 1 The emitter wires EW1, EW2, and EW3 shown are all of equal length, and the parasitic inductance L... UN L VN and L WN Set them to the same value. Furthermore, Figure 9 The simulation results show that it is only affected by the parasitic inductance L UN The result of the influence, therefore with Figure 6 Compared to the simulation results, the spike-shaped noise voltage SN has a lower height. Thus, depending on the value of the affected parasitic inductance, the spike-shaped noise voltage varies significantly, causing fluctuations in the accuracy of overcurrent protection.

[0059] In contrast, such as using Figure 1As explained, in the semiconductor power module 100 of Embodiment 1, by setting the lengths of the emitter wires EW1, EW2, and EW3 of each of the transistor chips 1 to 3 to be such that the emitter wires that are closer to the N terminal NT in the horizontal direction are longer, the value of the parasitic inductance is L. UN >L VN >L WN The relationship.

[0060] here, Figure 10 The text appears to be a mix of Chinese characters and symbols, possibly representing a corrupted or incomplete document. A direct translation wouldn't be meaningful without further context or clarification. Figure 4 After the current path causes the three-phase AC inverter to operate, and the power supply to transistor chip 6 is stopped, in the process of forming... Figure 5 The simulation results show the spike-like noise voltage generated between SC and GND of the control circuit CC1 connected to transistor chip 1 under the condition of a freewheeling current path. Figure 10 The spike-shaped noise voltage SN is also generated periodically, but unlike... Figure 6 Compared to the simulation results shown, the spike-shaped noise voltage SN has a lower height.

[0061] in addition, Figure 11 The text appears to be a mix of Chinese characters and symbols, possibly representing a corrupted or incomplete document. A direct translation wouldn't be meaningful without further context or clarification. Figure 7 After the current path causes the three-phase AC inverter to operate, and the power supply to transistor chip 4 is stopped, in the process of forming... Figure 7 The simulation results show the spike-like noise voltage generated between SC and GND of the control circuit CC3 connected to transistor chip 3 under the condition of a freewheeling current path. Figure 11 The spike-shaped noise voltage SN is also generated periodically, but the height of the spike-shaped noise voltage SN is... Figure 10 The simulation results shown are the same. Therefore, the spike-like noise voltage between SC and GND of the control circuits CC1 to CC3 connected to transistor chips 1 to 3 can be made consistent, thereby improving the accuracy of overcurrent protection for transistor chips 1 to 3.

[0062] also, Figure 10 as well as Figure 11 The simulation conditions shown in the figure are such that the value of the parasitic inductance is L. UN =L VN +L N2 =L WN +L N2 +L N3 The size of each parasitic inductor is set in a way that is equivalent to setting the length of the emitter wires EW1, EW2 and EW3 of transistor chips 1 to 3 in such a way that the emitter wires that are closer to the N terminal NT in the horizontal direction are longer.

[0063] In addition, the rated values ​​for the semiconductor power module 100 are 10 to 500 A for output current and 600 to 1700 V for output voltage.

[0064] <Implementation Method 2>

[0065] Figure 12 This is a top view showing the structure of the semiconductor power module 200 according to Embodiment 2 of the present invention, for comparison with... Figure 1 The semiconductor power module 100 of Embodiment 1 shown in the figure has the same structure and is labeled with the same reference numerals, and repeated descriptions are omitted.

[0066] like Figure 12 As shown, in the semiconductor power module 200, the emitter wires EW1, EW2, and EW3 of the transistor chips 1-3 with different collector potentials are configured such that the emitter wires that are closer to the N-terminal NT in the horizontal direction have fewer wires. That is, in a direction parallel to the long side of the resin casing RC, the emitter wires that are closer to the N-terminal NT have fewer wires. More specifically, the emitter wire EW1, which is closest to the N-terminal NT, has the fewest wires, while the emitter wire EW3, which is farthest from the N-terminal NT, has the most wires.

[0067] By making the emitter wires that are closer together in the horizontal direction to the N terminal NT, the number of wires is reduced, thereby making the parasitic inductance consistent and the wiring inductance the same, which can improve the accuracy of overcurrent protection.

[0068] <Implementation Method 3>

[0069] Figure 13 This is a top view showing the structure of the semiconductor power module 300 according to Embodiment 3 of the present invention, for comparison with... Figure 1 The semiconductor power module 100 of Embodiment 1 shown in the figure has the same structure and is labeled with the same reference numerals, and repeated descriptions are omitted.

[0070] like Figure 13 As shown, in the semiconductor power module 300, regarding the diameters of the emitter wires EW1, EW2, and EW3 of the transistor chips 1-3 with different collector potentials, the emitter wires that are closer to the N-terminal NT in the horizontal direction have smaller diameters. That is, in the direction parallel to the long side of the resin casing RC, the emitter wires that are closer to the N-terminal NT have smaller diameters. More specifically, the emitter wire EW1, which is closest to the N-terminal NT, has the smallest diameter, and the emitter wire EW3, which is farthest from the N-terminal NT, has the largest diameter.

[0071] By making the emitter wires that are closer in the horizontal direction to the N terminal NT have smaller wire diameters, it is possible to make the parasitic inductance consistent and the wiring inductance the same, thereby improving the accuracy of overcurrent protection.

[0072] <Variation Example>

[0073] Furthermore, in the embodiments 1 to 3 described above, the switching element, i.e., the transistor chip, and the freewheeling element, i.e., the diode chip, are shown as different chips. However, the same effect can be achieved by using a reverse conducting insulated gate transistor (RC-IGBT) that integrates the switching element and the freewheeling element into a single chip.

[0074] Semiconductors used as switching elements are not limited to silicon (Si); wide-bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) can also be used. Compared with silicon semiconductor devices, wide-bandgap semiconductor devices can be miniaturized, have better voltage withstand capability, allow higher current density, and have higher heat resistance, thus enabling operation at high temperatures.

[0075] Furthermore, in the embodiments 1 to 3 described above, examples of using wires as emitter wires EW1 to EW3 are shown, but strip wires can also be used.

[0076] <Implementation Method 4>

[0077] This embodiment applies the semiconductor power modules 100-300 of embodiments 1 to 3 described above to a power conversion device.

[0078] Figure 14 This is a block diagram showing the structure of a power conversion system that applies the power conversion device according to Embodiment 4.

[0079] Figure 14 The power conversion system shown consists of a power supply 1000, a power conversion device 2000, and a load 3000.

[0080] The power supply 1000 is a DC power supply that supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit connected to an AC system and an AC / DC converter. Alternatively, the power supply 1000 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0081] The power conversion device 2000 uses at least one of the semiconductor power modules 100-300 described in embodiments 1-3 above. The U terminal UT, V terminal VT, and W terminal WT of the semiconductor power modules 100-300 are connected to the load 3000.

[0082] Load 3000 is a three-phase motor driven by AC power obtained by converting DC power to AC power through power conversion device 2000. Furthermore, load 3000 is not limited to a specific application and is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0083] The power conversion device according to this embodiment uses at least one of the semiconductor power modules 100 to 300 of embodiments 1 to 3, thereby improving the accuracy of overcurrent protection. Furthermore, by miniaturizing the semiconductor power modules, the overall system can be miniaturized.

[0084] Furthermore, the present invention allows for free combination of various embodiments within its disclosed scope, or appropriate modification or omission of various embodiments.

[0085] Explanation of the label

[0086] 1-6 transistor chips, 11-16 diode chips, CC1-CC6 control circuit, NL, PL main power supply lines, NCP1, NCP2, NCP3 N-side collector circuit pattern, PCP P-side collector circuit pattern, EW1, EW2, EW3 emitter wires, NM N-side main electrode, PPM P-side main electrode, NT N terminal, PTP terminal, DP1, DP2, DP3 chip pads, CS current sensing terminal, SC current sensing terminal.

Claims

1. A semiconductor power module comprising a three-phase AC inverter mounted within a package. in, The three-phase AC inverter has the following features: A first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, and a sixth switching element are connected in series between a first main power line given a first potential and a second main power line given a second potential lower than the first potential. as well as The first, second, third, fourth, fifth, and sixth freewheeling elements are connected in parallel in reverse order to the first through sixth switching elements, respectively. The semiconductor power module has: The first circuit pattern, the second circuit pattern, and the third circuit pattern are respectively equipped with the second switching element, the fourth switching element, and the sixth switching element; A fourth circuit pattern, which incorporates the first switching element, the third switching element, and the fifth switching element; The second main electrode is connected in common with the main electrode wiring of the second switching element, the fourth switching element and the sixth switching element; The second main electrode terminal is connected to the second main electrode. The first main electrode is electrically connected to the fourth circuit pattern; as well as The first main electrode terminal is connected to the first main electrode. The first, second, and third chip pads of the first to third circuit patterns, which respectively mount the second, fourth, and sixth switching elements, are arranged in a parallel column. The arrangement direction of the first, second, and third chip pads is along one side of the package. The second main electrode is arranged to extend along said side. When viewed from above, the second main electrode terminal is located at the end of the second main electrode in the direction of its extension. The main electrode wiring of the second switching element, the fourth switching element, and the sixth switching element is arranged such that, when viewed from above, the main electrode wiring that is closer to the second main electrode terminal in the horizontal direction is longer.

2. The semiconductor power module according to claim 1, wherein, The first chip pad to the third chip pad are arranged in a stepped manner as follows: The first chip pad has the smallest horizontal distance to the second main electrode terminal when viewed from above. The horizontal distance to the second main electrode terminal increases in the order of the second chip pad and the third chip pad, and the height of the pads decreases when viewed from above as they face the second main electrode terminal.

3. The semiconductor power module according to claim 1, wherein, The first to the sixth switching elements have current sensing terminals. The semiconductor power module has a control circuit that controls the switching on and off of the first to the sixth switching elements, respectively. The control circuit has a current sensing terminal that receives a sensing current output from the sensing current terminals of the respective first to sixth switching elements, and the control circuit controls the on / off state of the first to sixth switching elements based on the input sensing current.

4. The semiconductor power module according to claim 1, wherein, The first main electrode terminal and the second main electrode terminal are disposed adjacent to each other along the other side of the package that is orthogonal to one side.

5. The semiconductor power module according to claim 1, wherein, The main electrode wiring of the second switching element, the fourth switching element, and the sixth switching element is arranged such that, when viewed from above, the main electrode wiring that is closer to the second main electrode terminal in the horizontal direction has fewer wires.

6. The semiconductor power module according to claim 1, wherein, The main electrode wiring of the second switching element, the fourth switching element, and the sixth switching element is arranged such that, when viewed from above, the main electrode wiring that is closer to the second main electrode terminal in the horizontal direction has a smaller wire thickness.

7. The semiconductor power module according to claim 1, wherein, The first to the sixth switching elements are wide-bandgap semiconductor elements.

8. A power conversion device comprising a semiconductor power module according to any one of claims 1 to 7, the power conversion device converting incoming power to output power.

Images