Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a preparation method thereof, a substrate, the substrate comprising a first region and a second region; a virtual gate pattern and a functional gate pattern, located on the substrate in the second region, the virtual gate pattern being close to the first region, the virtual gate pattern comprising a first partial gate pattern and a second partial gate pattern, the virtual gate pattern and the functional gate pattern both comprising a gate metal layer, the upper surface of the gate metal layer in the first partial gate pattern being lower than the upper surface of the gate metal layer in the second partial gate pattern; a dielectric layer, located on the substrate in the first region, and located on the substrate in the second region between the virtual gate pattern and the first region.

Description

[0001] This application is a divisional application for a patent with an application date of "September 11, 2018", an application number of "201811058556.0", and an invention name of "Semiconductor device and its preparation method". Technical Field

[0002] The present invention relates to the field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0003] DRAM (Dynamic Random Access Memory) is a semiconductor memory device. DRAM includes a memory array area and peripheral circuits. The memory array area includes structures such as memory and capacitors, and the peripheral circuits include circuits for controlling the arrangement of the memory cell array.

[0004] Typically, a dummy MOS gate is provided in the boundary region (transition region between the memory array region and the peripheral circuit) to solve the boundary edge effect in the photolithography process and the micro loading effect in the chemical mechanical polishing process. However, the provision of the dummy MOS gate will reduce the density of the integrated circuit. Summary of the invention

[0005] The main purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the floor space occupied by dummy transistors to improve the density of integrated circuits.

[0006] To achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] Providing a substrate, the substrate comprising a first area and a second area, wherein a first boundary is formed at a junction of the first area and the second area;

[0008] forming a gate polysilicon layer on the substrate, wherein the gate polysilicon layer is located in the second region and has a second boundary on a side close to the first region;

[0009] forming a gate metal layer and a gate protection layer on the substrate in sequence, wherein the gate metal layer and the gate protection layer cover the gate polysilicon layer and extend from the second boundary of the gate polysilicon layer to the first region; and

[0010] The gate protection layer, the gate metal layer and the gate polysilicon layer are sequentially etched to form a virtual gate pattern and a functional gate pattern separated from each other on the second region, the gate polysilicon layer of the virtual gate pattern has the second boundary, the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend to between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary;

[0011] A dielectric layer is formed on the substrate and planarized.

[0012] Optionally, in the method for preparing the semiconductor device, the step of forming a dielectric layer on the substrate and planarizing the dielectric layer includes:

[0013] forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the dummy gate pattern and the functional gate pattern, and fills a gap between the dummy gate pattern and the functional gate pattern;

[0014] The dielectric layer is planarized until the dummy gate pattern and the functional gate pattern are exposed.

[0015] Optionally, in the method for manufacturing the semiconductor device, a width of the dummy gate pattern between the first boundary and the second boundary accounts for 2% to 60% of a total width of the dummy gate pattern.

[0016] Optionally, in the method for preparing the semiconductor device, a buried gate is formed in the substrate of the first region, a surface of the buried gate is lower than a surface of the substrate, and an insulating layer is also formed on the buried gate and the substrate of the first region.

[0017] Optionally, in the method for preparing the semiconductor device, before forming the gate polysilicon layer, the method further includes: forming a gate oxide layer on the substrate, wherein the gate oxide layer covers the substrate in the second region.

[0018] Optionally, in the method for preparing the semiconductor device, the step of forming the gate polysilicon layer on the substrate includes:

[0019] forming a gate polysilicon material layer on the substrate, wherein the gate polysilicon material layer covers the substrate and the gate oxide layer;

[0020] forming a patterned photoresist layer on the gate polysilicon material layer;

[0021] The gate polysilicon material layer is etched using the patterned photoresist layer as a mask to remove the first region and a portion of the gate polysilicon material layer in the second region close to the first region to form the gate polysilicon layer.

[0022] Optionally, in the method for preparing the semiconductor device, after forming the gate polysilicon layer and before forming the gate metal layer, the method further includes: forming a metal adhesion layer on the substrate.

[0023] Optionally, in the method for preparing the semiconductor device, the step of forming the dummy gate pattern and the functional gate pattern includes:

[0024] forming a patterned photoresist layer on the gate protection layer;

[0025] Using the patterned photoresist layer as a mask, the gate protection layer, the gate metal layer, the metal adhesion layer and the gate polysilicon layer are sequentially etched until the substrate is exposed, and a dummy gate pattern and a functional gate pattern are formed on the substrate in the second region.

[0026] Optionally, in the preparation method of the semiconductor device, the material of the gate metal layer includes tungsten, aluminum or doped polysilicon, the material of the metal adhesion layer includes cobalt silicide, titanium silicide or titanium nitride, the material of the gate protection layer includes silicon dioxide, silicon nitride or silicon carbide, and the material of the dielectric layer includes silicon dioxide or silicon nitride.

[0027] Accordingly, the present invention further provides a semiconductor device, comprising:

[0028] A substrate, the substrate comprising a first region and a second region, wherein a first boundary is formed at a junction of the first region and the second region;

[0029] A virtual gate pattern and a functional gate pattern separated from each other are located on the substrate in the second region, and the virtual gate pattern is close to the first region; the virtual gate pattern and the functional gate pattern both include a gate polysilicon layer, a gate metal layer and a gate protection layer sequentially located on the substrate, and the gate polysilicon layer of the virtual gate pattern has a second boundary on a side close to the first region, the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend to between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary;

[0030] The dielectric layer is located on the substrate and filled between the dummy gate pattern and the functional gate pattern.

[0031] Optionally, in the semiconductor device, a width of the dummy gate pattern between the first boundary and the second boundary accounts for 2% to 60% of a total width of the dummy gate pattern.

[0032] Optionally, in the semiconductor device, a buried gate is formed on the substrate in the first region, a surface of the buried gate is lower than a surface of the substrate, and an insulating layer is further formed on the buried gate and the substrate in the first region.

[0033] Optionally, in the semiconductor device, the virtual gate pattern and the functional gate pattern also include: a gate oxide layer located between the substrate and the gate polysilicon layer, and the projection of the gate oxide layer in the virtual gate pattern on the substrate coincides with the projection of the gate metal layer on the substrate.

[0034] Optionally, in the semiconductor device, the virtual gate pattern and the functional gate pattern also include: a metal adhesion layer located between the gate polysilicon layer and the gate metal layer, and the projection of the metal adhesion layer in the virtual gate pattern on the substrate coincides with the projection of the gate metal layer on the substrate.

[0035] Optionally, in the semiconductor device, the material of the gate metal layer includes tungsten, aluminum or doped polysilicon, the material of the metal adhesion layer includes cobalt silicide, titanium silicide or titanium nitride, the material of the gate protection layer includes silicon dioxide, silicon nitride or silicon carbide, and the material of the dielectric layer includes silicon dioxide or silicon nitride.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] In the present invention, a portion of the virtual gate graphics is located between the first boundary and the second boundary. Compared with the virtual gate graphics located on the side of the second boundary away from the first boundary in the prior art, the virtual gate graphics are closer to the first region, thereby saving the area of ​​the second region, increasing the density of the integrated circuit, and improving the area utilization of the semiconductor device.

[0038] Furthermore, the gate polysilicon layer of the virtual gate pattern has the second boundary, and the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary, so that after the dielectric layer is planarized, the height of the dielectric layer from the virtual gate pattern to the first area is close to the height of the dielectric layer in the first area, that is, the dielectric layer has a planarized surface, avoiding the problem of uneven etching when the dielectric layer in the first area is subsequently etched, and can also avoid the problem of bottom short circuit of the device subsequently formed in the first area, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a cross-sectional schematic diagram of a semiconductor device;

[0040] Figure 2 A flow chart of a method for preparing a semiconductor device provided by one embodiment of the present invention;

[0041] Figure 3 A schematic cross-sectional view of a substrate provided in a method for preparing a semiconductor device according to an embodiment of the present invention;

[0042] Figure 4 is Figure 3 A schematic cross-sectional view of forming a gate polysilicon material layer on the structure;

[0043] Figure 5 is Figure 4 A schematic cross-sectional view of a patterned photoresist layer formed on the structure;

[0044] Figure 6 is Figure 5 A schematic cross-sectional view of forming a gate polysilicon layer on the structure;

[0045] Figure 7 is Figure 6 A schematic cross-sectional view of a gate metal layer and a gate protection layer formed on the structure;

[0046] Figure 8 is Figure 7 A cross-sectional schematic diagram of forming a dummy gate pattern and a functional gate pattern on the structure shown;

[0047] Fig. 9 is Figure 8 A cross-sectional schematic diagram of forming a dielectric layer on the structure shown and performing planarization.

[0048] The reference numerals are as follows:

[0049] 1-substrate; 1A-first region; 1B-second region;

[0050] 10-buried gate; 11-buried gate metal layer; 12-buried gate dielectric layer;

[0051] 20-insulating layer;

[0052] 30-gate oxide layer;

[0053] 40-gate polysilicon layer;

[0054] 50-metal adhesion layer;

[0055] 60-gate metal layer;

[0056] 70-gate protection layer;

[0057] 80- dielectric layer;

[0058] 2- Virtual gate pattern;

[0059] 3- Functional gate pattern;

[0060] 100-substrate; 100A-first region; 100B-second region;

[0061] 110 - buried gate; 111 - buried gate metal layer; 112 - buried gate dielectric layer;

[0062] 120-insulation layer;

[0063] 130 - gate polysilicon layer; 130 ' - gate polysilicon material layer;

[0064] 140-gate oxide layer;

[0065] 150-patterned photoresist layer;

[0066] 160-metal adhesion layer;

[0067] 170-gate metal layer;

[0068] 180-gate protection layer;

[0069] 190- medium layer;

[0070] 200-virtual gate pattern;

[0071] 300-functional gate pattern;

[0072] S1-first boundary; S2-second boundary. DETAILED DESCRIPTION

[0073] Figure 1 is a cross-sectional schematic diagram of a semiconductor device, such as Figure 1 As shown, the semiconductor device includes: a substrate 1, the substrate 1 includes a first region 1A and a second region 1B, the first region 1A is a region for forming a memory cell array, the second region 1B is a region for forming an array peripheral circuit, and a first boundary S1 is provided at the junction of the first region 1A and the second region 1B.

[0074] In the first region 1A, a built-in buried gate 10 is formed in the substrate 1, that is, the buried gate 10 is located in a groove of the substrate 1, and the buried gate 10 includes a buried gate dielectric layer 12 located at the bottom and sidewalls of the groove and a buried gate metal layer 11 filled in the groove, and the surface of the buried gate 10 is lower than the surface of the substrate 1, and an insulating layer 20 is also formed on the buried gate 10 and the substrate 1 in the first region 1A.

[0075] In the second region 1B, a dummy gate pattern 2 and a functional gate pattern 3 separated from each other are formed on the substrate 1. Compared with the functional gate pattern 3, the dummy gate pattern 2 is closer to the first region 1A. Both the dummy gate pattern 2 and the functional gate pattern 3 include a gate oxide layer 30, a gate polysilicon layer 40, a metal adhesion layer 50, a gate metal layer 60 and a gate protection layer 70 sequentially located on the substrate 1. The dummy gate pattern 2 has a second boundary S2 close to the first region 1A.

[0076] A dielectric layer is also formed on the substrate 1, and the dielectric layer covers the substrate 1, the insulating layer 20, the dummy gate pattern 2, and the functional gate pattern 3. Then, the dielectric layer needs to be planarized to expose the dummy gate pattern 2 and the functional gate pattern 3, so as to form a Figure 1 The formation of the dummy gate pattern 2 is to overcome the boundary edge effect in the photolithography process and the micro loading effect in the chemical mechanical polishing process, but the dummy gate pattern 2 cannot be used as an effective functional transistor, and its formation will occupy the area of ​​the second region 1B, resulting in a reduction in the density of the integrated circuit.

[0077] Furthermore, since the second region 1B is formed with the dummy gate pattern 2 and the functional gate pattern 3, and the first region 1A is only formed with the insulating layer 20, the height of the first region 1A is smaller than the height of the second region 1B. When the dielectric layer 80 is subsequently filled and planarized, the surface of the dielectric layer 80 from the second boundary S2 to the first region 1A may be uneven. Figure 1As shown, from the second boundary S2 to the first region 1A, the height of the dielectric layer 80 gradually decreases, so that when etching is subsequently performed in the first region 1A, the etching aspect ratio will change, thereby causing the relatively high region of the dielectric layer 80 to easily cause a bottom short circuit of the device.

[0078] Based on the above problems, the present invention provides a semiconductor device and a preparation method thereof, providing a substrate having a first region and a second region, wherein the first region and the second region have a first boundary at their junction, forming a gate polysilicon layer on the substrate, the gate polysilicon layer being located in the second region and having a second boundary on a side of the gate polysilicon layer close to the first region, then forming a gate metal layer and a gate protection layer in sequence on the substrate, the gate metal layer and the gate protection layer covering the gate polysilicon layer and extending from the second boundary of the gate polysilicon layer to the first region, then etching the gate protection layer, the gate metal layer and the gate polysilicon layer in sequence to form a virtual gate pattern and a functional gate pattern separated from each other on the second region, the gate polysilicon layer of the virtual gate pattern having the second boundary, the gate metal layer and the gate protection layer of the virtual gate pattern covering the gate polysilicon layer and extending to between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary, and finally forming a dielectric layer on the substrate and planarizing it.

[0079] The gate polysilicon layer of the virtual gate pattern in the present invention has the second boundary, and the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary. In this way, after the dielectric layer is subsequently filled and flattened, the height of the dielectric layer from the virtual gate pattern to the first region is close to the height of the dielectric layer in the first region, that is, the dielectric layer has a flattened surface, which avoids the problem of uneven etching when the dielectric layer in the first region is subsequently etched, and can also avoid the problem of short circuit at the bottom of the device subsequently formed in the first region, thereby improving the performance of the semiconductor device.

[0080] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0081] Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0082] Please refer to Figure 2 , which is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 2 As shown, the method for preparing the semiconductor device comprises the following steps:

[0083] Step S01: providing a substrate, wherein the substrate comprises a first region and a second region, wherein a first boundary is formed at a junction of the first region and the second region;

[0084] Step S02: forming a gate polysilicon layer on the substrate, wherein the gate polysilicon layer is located in the second region and has a second boundary on a side of the gate polysilicon layer close to the first region;

[0085] Step S03: sequentially forming a gate metal layer and a gate protection layer on the substrate, wherein the gate metal layer and the gate protection layer cover the gate polysilicon layer and extend from the second boundary of the gate polysilicon layer to the first region;

[0086] Step S04: etching the gate protection layer, the gate metal layer and the gate polysilicon layer in sequence to form a virtual gate pattern and a functional gate pattern separated from each other on the second region, the gate polysilicon layer of the virtual gate pattern having the second boundary, the gate metal layer and the gate protection layer of the virtual gate pattern covering the gate polysilicon layer and extending to between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary;

[0087] Step S05: forming a dielectric layer on the substrate and planarizing it.

[0088] Figure 3 FIG. 1 is a cross-sectional view of a substrate provided in a method for preparing a semiconductor device according to an embodiment of the present invention. Figure 3 As shown, in step S01 , a substrate 100 is provided. The substrate 100 includes a first region 100A and a second region 100B. A first boundary S1 is formed at a junction between the first region 100A and the second region 100B.

[0089] The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI); it may also be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is preferably single crystal silicon (Si).

[0090] The substrate 100 includes a first region 100A and a second region 100B. The first region 100A is used to form a memory cell array, and the second region 100B is used to form a peripheral circuit. A first boundary S1 is provided at the junction of the first region 100A and the second region 100B. The height of the substrate 100 in the second region 100B is higher than the height of the substrate 100 in the first region 100A, that is, the upper surface of the substrate 100 in the second region 100B is higher than the upper surface of the substrate 100 in the first region 100A. In addition, the substrate 100 may also include regions for other functions, such as a cutting region, etc., which are not described one by one here.

[0091] A buried gate 110 is formed in the first substrate 100 in the first region 100A. Figure 3 As shown, a groove is formed in the first substrate 100, and the buried gate 110 is formed in the groove. In the embodiment of the present application, the buried gate 110 includes a buried gate dielectric layer 112 and a buried gate metal layer 111, the buried gate dielectric layer 112 is located on the sidewall and bottom of the groove, the buried gate metal layer 111 is filled in the groove, and the upper surface of the buried gate dielectric layer 112 is lower than the upper surface of the buried gate metal layer 111, and the upper surface of the buried gate metal layer 111 is lower than the upper surface of the substrate 100. An insulating layer 120 is also formed on the buried gate 110 and the substrate 100.

[0092] Figure 4 is Figure 3 A schematic cross-sectional view of a gate polysilicon material layer formed on the structure, Figure 5 is Figure 4 A schematic cross-sectional view of a patterned photoresist layer formed on the structure, Figure 6 is Figure 5 A schematic cross-sectional view of a gate polysilicon layer formed on the structure. Figure 4 , Figure 5 and Figure 6As shown, in step S02, a gate polysilicon layer 130 is formed on the substrate 100, the gate polysilicon layer 130 is located in the second region 100B, and has a second boundary S2 on one side of the gate polysilicon layer close to the first region 100A.

[0093] In the embodiment of the present application, before forming the gate polysilicon layer 130, a gate oxide layer 140 is first formed on the substrate 100 in the second region 100B. The material of the gate oxide layer 140 includes but is not limited to silicon dioxide. Specifically, the gate oxide layer 140 is grown by the ISSG method, which will only grow SiO2 on the surface where silicon is exposed, and will not grow on the surface where SiN is present, that is, the gate oxide layer 140 is only formed on the substrate 100 in the second region 100B.

[0094] Then, please continue to refer to Figure 4 As shown, a gate polysilicon material layer 130 ′ is formed on the substrate, and the gate polysilicon material layer 130 ′ covers the substrate 100 and the gate oxide layer 140 .

[0095] Next, please refer to Figure 5 and Figure 6 As shown, the gate polysilicon material layer 130' is etched to remove the first region 100A and the second region 100B near the first region 100A, so as to form a gate polysilicon layer 130, and the gate polysilicon layer 130 has a second boundary S2 on one side near the first region 100A, that is, Figure 6 The left side of the gate polysilicon layer 130 is shown overlapping with the second boundary S2.

[0096] In the embodiment of the present application, a photoresist layer (not shown) is formed on the gate polysilicon material layer 130', and the photoresist layer is patterned, for example, the photoresist layer is exposed and developed to form a patterned photoresist layer 150, such as Figure 5 As shown. The patterned photoresist layer 150 exposes the gate polysilicon material layer 130 of the first region 100A, and exposes the gate polysilicon material layer 130' of a portion of the second region 100B close to the first region 100A. Next, the gate polysilicon material layer 130' is etched using the patterned photoresist layer 150 as a mask to remove the gate polysilicon material layer 130' that is not blocked by the patterned photoresist layer 150, and retain the gate polysilicon material layer 130' that is blocked by the patterned photoresist layer 150, so as to form a gate polysilicon layer 130, as shown. Figure 6The gate polysilicon layer 130 has a second boundary S2 close to the first region 100A.

[0097] So far, in the embodiment of the present application, two boundaries are set. The first boundary S1 is the boundary at the junction of the first region 100A and the second region 100B, and the second boundary S2 is a side surface of the gate polysilicon layer 130 close to the first region 100A.

[0098] Figure 7 is Figure 6 A schematic cross-sectional view of a gate metal layer and a gate protection layer formed on the structure. Figure 7 As shown, in step S03, a gate metal layer 170 and a gate protection layer 180 are sequentially formed on the substrate 100, and the gate metal layer 170 and the gate protection layer 180 cover the gate polysilicon layer 130 and extend from the second boundary S2 of the gate polysilicon layer 130 to the first region 100A.

[0099] In an embodiment of the present application, before forming the gate metal layer 170, a metal adhesion layer 160 is first formed on the substrate 100 to ensure the adhesion of the subsequently formed gate metal layer 170 to the gate polysilicon layer 130. The metal adhesion layer 160 covers the substrate 100, the gate oxide layer 140 and the gate polysilicon layer 130. Specifically, the metal adhesion layer 160 covers the substrate 100 in the first region 100A, covers the gate oxide layer 140 between the first boundary S1 and the second boundary S2, and also covers the gate polysilicon layer 130 on the side of the second boundary S2 away from the first boundary S1.

[0100] Next, a gate metal layer 170 is formed on the metal adhesion layer 160, and the gate metal layer 170 covers the metal adhesion layer 160. Then, a gate protection layer 180 is formed on the gate metal layer 170, and the gate protection layer 180 covers the gate metal layer 170. The material of the metal adhesion layer 160 includes but is not limited to cobalt silicide, titanium silicide or titanium nitride, the material of the gate metal layer 170 includes but is not limited to tungsten, aluminum or doped polysilicon, and the material of the gate protection layer 180 includes but is not limited to silicon dioxide, silicon nitride or silicon carbide.

[0101] It should be noted that, since the gate polysilicon layer 130 is not formed between the first boundary S1 and the second boundary S2, the second boundary S2 on the second region 100B is close to the side of the first boundary S1 (eg Figure 7 The height of the second boundary S2 on the left side is lower than the height of the second boundary S2 on the side away from the first boundary S1 (as shown in FIG. Figure 7 Then, after the metal adhesion layer 160, the gate metal layer 170 and the gate protection layer 180 are formed, in the process from the left side of the second boundary S2 to the first boundary S1, the upper surface of the gate protection layer 180 has a slope, that is, the height of the semiconductor device gradually decreases to a certain height.

[0102] Figure 8 is Figure 7 A cross-sectional diagram of a structure in which a dummy gate pattern and a functional gate pattern are formed. Figure 8 As shown, in step S04, the gate protection layer 180, the gate metal layer 170 and the gate polysilicon layer 130 are etched in sequence to form a virtual gate pattern 200 and a functional gate pattern 300 on the second region 100B, the gate polysilicon layer 130 of the virtual gate pattern 200 having the second boundary S2, the gate metal layer 170 and the gate protection layer 180 of the virtual gate pattern 200 covering the gate polysilicon layer 130 and extending to between the second boundary S2 and the first boundary S1, so that the height of the virtual gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1.

[0103] A photoresist layer (not shown) is formed on the gate protection layer 180, and the photoresist layer is patterned, for example, the photoresist layer is exposed and developed to form a patterned photoresist layer, wherein the patterned photoresist layer only covers the area on the gate protection layer 180 where the virtual gate pattern 200 and the functional gate pattern 300 are to be formed, and then the gate protection layer 180, the gate metal layer 170, the metal adhesion layer 160, the gate polysilicon layer 130 and the gate oxide layer 140 are sequentially etched using the patterned photoresist layer as a mask to form a gate protective layer 180, as shown in FIG. Fig. 9 The dummy gate pattern 200 and the functional gate pattern 300 are shown.

[0104] A portion of the virtual gate pattern 200 is located between the first boundary S1 and the second boundary S2. In the embodiment of the present application, the width of the virtual gate pattern 200 between the first boundary S1 and the second boundary S2 accounts for 2% to 60% of the total width of the virtual gate pattern 200. The virtual gate pattern 200 located between the first boundary S1 and the second boundary S2 does not have the gate polysilicon layer 130 at its bottom. Figure 1 In the embodiment, the virtual gate pattern 2 is located on the side of the second boundary S2 away from the first boundary S1, that is, on the right side of the second boundary S2, and Fig. 9In the embodiment, a portion of the virtual gate pattern 200 is located between the first boundary S1 and the second boundary S2, that is, the virtual gate pattern 200 intersects with the second boundary S2. Figure 1 In comparison, in the embodiment of the present application, the virtual gate pattern 200 is closer to the first region 100A, so the area of ​​the second region 100B can be appropriately reduced, thereby increasing the density of the integrated circuit and improving the area utilization of the semiconductor device.

[0105] The virtual gate pattern 200 includes a gate oxide layer 140 located on the substrate, a gate polysilicon layer 130 located on a portion of the gate oxide layer 140, a metal adhesion layer 160 located on the gate oxide layer 140 and the gate polysilicon layer 130, a gate metal layer 170 located on the metal adhesion layer 160, and a gate protection layer 180 located on the gate metal layer 170. The virtual gate pattern 200 does not have the function of a real gate, and is only used to overcome the boundary edge effect in the photolithography process and the micro loading effect in the chemical mechanical polishing process. That is, in the method for preparing a semiconductor device provided in the embodiment of the present application, on the basis of overcoming the boundary edge effect and the micro loading effect, the density of the integrated circuit can also be increased.

[0106] As described above, in the process of forming the metal adhesion layer 160, the gate metal layer 170 and the gate protection layer 180, due to the existence of the gate polysilicon layer 130, the layers formed thereon have a slope between the first boundary S1 and the second boundary S2. After etching the gate protection layer 180, the gate metal layer 170, the metal adhesion layer 160 and the gate polysilicon layer 130, between the first boundary S1 and the second boundary S2, the upper surface of the gate protection layer 180 will also have a slope, that is, from the second boundary S2 to the first boundary S1, the height of the virtual gate pattern 200 gradually decreases.

[0107] The functional gate pattern 300 includes a gate oxide layer 140, a gate polysilicon layer 130, a metal adhesion layer 160, a gate metal layer 170 and a gate protection layer 180 which are sequentially located on the substrate, wherein the gate oxide layer 140, the gate polysilicon layer 130, the metal adhesion layer 160 and the gate metal layer 170 constitute a gate, and the gate will form a transistor with the source and drain electrodes formed subsequently as a device in the second region 100B, and the gate protection layer 180 is used to protect the gate.

[0108] Fig. 9 is Figure 8A schematic cross-sectional view of forming a dielectric layer on the structure shown in FIG. Fig. 9 In step S05 , a dielectric layer 190 is formed on the substrate 100 and planarized.

[0109] Specifically, a dielectric layer 190 is deposited on the substrate 100 , and the dielectric layer 190 covers the substrate 100 , the insulating layer 120 , the dummy gate pattern 200 , and the functional gate pattern 300 , and fills the gaps between the components.

[0110] Then, the dielectric layer 190 is planarized. Since the height of the dummy gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1, after the dielectric layer 190 is planarized, the height of the dielectric layer 190 on the side of the dummy gate pattern 200 close to the first boundary S1 is relatively close to the height of the dielectric layer 190 in the first region 100A, that is, the dielectric layer 190 in the first region 100A has good planarity, which can avoid the problem of uneven etching when etching the dielectric layer later, and can also avoid the problem of bottom short circuit when manufacturing devices in the first region 100A later, thereby improving the performance of semiconductor devices.

[0111] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above. Fig. 9 As shown, the semiconductor device comprises:

[0112] A substrate 100, wherein the substrate 100 comprises a first region 100A and a second region 100B, wherein a first boundary S1 is formed at a junction between the first region 100A and the second region 100B;

[0113] The virtual gate pattern 200 and the functional gate pattern 300 are located on the substrate 100 in the second area 100B, the virtual gate pattern 200 and the functional gate pattern 300 are separated from each other, and the virtual gate pattern 200 is close to the first area 100A; the virtual gate pattern 200 and the functional gate pattern 300 both include a gate polysilicon layer 130, a gate metal layer 170 and a gate protection layer 180 sequentially located on the substrate 100, and the gate polysilicon layer 130 of the virtual gate pattern 200 has a second boundary S2 on one side close to the first area 100A, the gate metal layer 170 and the gate protection layer 180 of the virtual gate pattern 200 cover the gate polysilicon layer 130 and extend between the first boundary S1 and the second boundary S2, so that the height of the virtual gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1.

[0114] The device further comprises: a dielectric layer 190, the dielectric layer 190 being located on the substrate 100 and filling between the dummy gate pattern 200 and the functional gate pattern 300. Since the height of the dummy gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1, the height of the dielectric layer 190 from the dummy gate pattern 200 to the first region 100A is close to the height of the dielectric layer 190 in the first region 100A, that is, the dielectric layer 190 has a planarized surface, which avoids the problem of uneven etching when etching the dielectric layer 190 in the first region 100A in the subsequent process, and also avoids the problem of short circuit at the bottom of the device formed in the first region 100A in the subsequent process, thereby improving the performance of the semiconductor device.

[0115] A buried gate 110 is formed on the substrate 100 in the first region 100A, the surface of the buried gate 110 is lower than the surface of the substrate 100, and an insulating layer 120 is also formed on the buried gate 110 and the substrate 100 in the first region 100A. Specifically, a groove is formed in the substrate 100, the buried gate 110 is formed in the groove and partially fills the groove, and an insulating layer 120 is formed on the top of the buried gate 110 in the groove and on the substrate 100. The buried gate 110 includes a buried gate dielectric layer 112 and a buried gate metal layer 111, the buried gate dielectric layer 112 fills the bottom and sidewalls of the groove, and the buried gate metal layer 111 fills the groove.

[0116] The dummy gate pattern 200 and the functional gate pattern 300 both further include: a gate oxide layer 140 located between the substrate 100 and the gate polysilicon layer 130, and the projection of the gate oxide layer 140 in the dummy gate pattern 200 on the substrate 100 coincides with the projection of the gate metal layer 170 on the substrate 100. The dummy gate pattern 200 and the functional gate pattern 300 both further include: a metal adhesion layer 160 located between the gate polysilicon layer 130 and the gate metal layer 170, and the projection of the metal adhesion layer 160 in the dummy gate pattern 200 on the substrate 100 coincides with the projection of the gate metal layer 170 on the substrate 100.

[0117] In the embodiment of the present application, the virtual gate pattern 200 includes a gate oxide layer 140 located on the substrate 100, a portion of the gate oxide layer 140 is located between the first boundary S1 and the second boundary S2, a gate polysilicon layer 130 located on a portion of the gate oxide layer 140, the gate polysilicon layer 130 is located on a side of the second boundary S2 away from the first boundary S1, and a metal adhesion layer 160, a gate metal layer 170, and a gate protection layer 180 located on the gate oxide layer 140 and the gate polysilicon layer 130. The projections of the gate protection layer 180, the gate metal layer 170, the metal adhesion layer 160, and the gate oxide layer 140 on the substrate overlap.

[0118] The width of the virtual gate pattern 200 between the first boundary S1 and the second boundary S2 accounts for 2% to 60% of the total width of the virtual gate pattern 200. Figure 1 Compared with the semiconductor device shown in FIG. 1 , the dummy gate pattern 200 is closer to the first region 100A, thereby saving the area of ​​the second region 100B, increasing the density of the integrated circuit, and improving the area utilization of the semiconductor device.

[0119] The gate metal layer 170 is made of tungsten, aluminum or doped polysilicon, the metal adhesion layer 160 is made of cobalt silicide, titanium silicide or titanium nitride, the gate protection layer 180 is made of silicon dioxide, silicon nitride or silicon carbide, and the dielectric layer 190 is made of silicon dioxide or silicon nitride.

[0120] To sum up, in the semiconductor device and the preparation method thereof provided by the present invention, a portion of the virtual gate pattern is located between the first boundary and the second boundary. Compared with the virtual gate pattern located on the side of the second boundary away from the first boundary in the prior art, the virtual gate pattern is closer to the first region, thereby saving the area of ​​the second region, increasing the density of the integrated circuit, and improving the area utilization of the semiconductor device.

[0121] Furthermore, the gate polysilicon layer of the virtual gate pattern has a second boundary, and the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend between the second boundary and the first boundary, so that the height of the virtual gate pattern gradually decreases from the second boundary to the first boundary. After the dielectric layer is subsequently formed and flattened, the height of the dielectric layer from the virtual gate pattern to the first area is close to the height of the dielectric layer in the first area, that is, the dielectric layer has a flattened surface, which avoids the problem of uneven etching when the dielectric layer in the first area is subsequently etched, and can also avoid the problem of bottom short circuit of the device subsequently formed in the first area, thereby improving the performance of the semiconductor device.

[0122] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising a first region and a second region; A virtual gate pattern and a functional gate pattern, located on the substrate in the second region, the virtual gate pattern is close to the first region, the virtual gate pattern includes a first partial gate pattern and a second partial gate pattern, the virtual gate pattern and the functional gate pattern both include a gate metal layer and a gate protection layer located on the gate metal layer, the upper surface of the gate metal layer in the first partial gate pattern is lower than the upper surface of the gate metal layer in the second partial gate pattern, and the upper surface of the gate protection layer in the first partial gate pattern is lower than the upper surface of the gate protection layer in the second partial gate pattern; a dielectric layer, located on the substrate in the first region and located on the substrate in the second region between the dummy gate pattern and the first region; The first area is used to form a memory cell array, and the second area is used to form a peripheral circuit. In a direction from the second region to the first region, a height of an upper surface of the gate protection layer in the first partial gate pattern gradually decreases.

2. The semiconductor device according to claim 1, wherein: The dummy gate pattern and the functional gate pattern both further include a metal adhesion layer between the substrate and the gate metal layer, and an upper surface of the metal adhesion layer in the first partial gate pattern is lower than an upper surface of the metal adhesion layer in the second partial gate pattern.

3. The semiconductor device according to claim 2, characterized in that In a direction from the second region to the first region, a height of an upper surface of the metal adhesion layer in the first partial gate pattern gradually decreases.

4. The semiconductor device according to claim 2, characterized in that The material of the metal adhesion layer includes cobalt silicide, titanium silicide or titanium nitride.

5. The semiconductor device according to claim 1, wherein: The dummy gate pattern and the functional gate pattern both further include a gate polysilicon layer located between the gate metal layer and the substrate, and the gate polysilicon layer in the dummy gate pattern is only located in the second partial gate pattern.

6. The semiconductor device according to claim 5, characterized in that The dummy gate pattern and the functional gate pattern both further include a gate oxide layer located between the substrate and the gate polysilicon layer, and the first partial gate pattern and the second partial gate pattern both include the gate oxide layer.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The width of the first partial gate pattern accounts for 2%-60% of the total width of the dummy gate pattern.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first partial gate pattern is closer to the first region than the second partial gate pattern.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that: A buried gate is formed in the substrate of the first region, the surface of the buried gate is lower than the surface of the substrate, an insulating layer is further formed on the buried gate and the substrate of the first region, and the dielectric layer covers the insulating layer.

10. The semiconductor device according to any one of claims 1 to 6, characterized in that: The dielectric layer located on the substrate in the first region and on the substrate in the second region between the dummy gate pattern and the first region has a planarized surface.

11. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region; forming a dummy gate pattern and a functional gate pattern, wherein the dummy gate pattern and the functional gate pattern are located on the substrate in the second region, the dummy gate pattern is close to the first region, the dummy gate pattern comprises a first partial gate pattern and a second partial gate pattern, the dummy gate pattern and the functional gate pattern both comprise a gate metal layer and a gate protection layer located on the gate metal layer, the upper surface of the gate metal layer in the first partial gate pattern is lower than the upper surface of the gate metal layer in the second partial gate pattern, and the upper surface of the gate protection layer in the first partial gate pattern is lower than the upper surface of the gate protection layer in the second partial gate pattern; forming a dielectric layer, wherein the dielectric layer covers the substrate, the dummy gate pattern and the functional gate pattern, and fills a gap between the dummy gate pattern and the functional gate pattern; planarizing the dielectric layer until the dummy gate pattern and the functional gate pattern are exposed; The first area is used to form a memory cell array, and the second area is used to form a peripheral circuit. In a direction from the second region to the first region, a height of an upper surface of the gate protection layer in the first partial gate pattern gradually decreases.

12. The preparation method according to claim 11, characterized in that: The dielectric layer in the first region and in the second region between the dummy gate pattern and the first region has a planarized surface.

13. The preparation method according to claim 11, characterized in that: The first area and the second area have a first boundary at their junction; Forming the dummy gate pattern and the functional gate pattern includes: forming a gate polysilicon layer, wherein the gate polysilicon layer is located on the substrate in the second region and has a second boundary on a side close to the first region; forming a metal adhesion layer, a gate metal layer and a gate protection layer in sequence, wherein the metal adhesion layer, the gate metal layer and the gate protection layer cover the gate polysilicon layer and extend from the second boundary of the gate polysilicon layer to the first region; The gate protection layer, the gate metal layer, the metal adhesion layer and the gate polysilicon layer are sequentially etched to form the virtual gate pattern and the functional gate pattern, the gate polysilicon layer of the virtual gate pattern having the second boundary, and the metal adhesion layer, the gate metal layer and the gate protection layer of the virtual gate pattern covering the gate polysilicon layer and extending to between the second boundary and the first boundary.

14. The preparation method according to claim 13, characterized in that: An upper surface of the metal adhesion layer in the first partial gate pattern is lower than an upper surface of the metal adhesion layer in the second partial gate pattern.

15. The preparation method according to claim 13, characterized in that: The gate polysilicon layer in the dummy gate pattern is only located in the second partial gate pattern.

16. The preparation method according to any one of claims 11 to 15, characterized in that: The width of the first partial gate pattern accounts for 2%-60% of the total width of the dummy gate pattern.

17. The preparation method according to any one of claims 11 to 15, characterized in that: A buried gate is formed in the substrate of the first region, the surface of the buried gate is lower than the surface of the substrate, an insulating layer is further formed on the buried gate and the substrate of the first region, and the dielectric layer covers the insulating layer.

Images