An embedded data reading and writing method
By adopting the embedded data reading and writing method performed asynchronously in the elevator control equipment, the problem of lag caused by synchronous execution of storage operations is solved, and the normal operation and maintenance costs of the equipment are reduced.
Patent Information
- Application Number
- CN202310743213.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-21
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2043-06-21
AI Technical Summary
In elevator control equipment, when performing storage operations synchronously, due to insufficient MCU performance, the storage process is slow, which easily causes the equipment to run stutter.
An embedded data reading and writing method is proposed. By judging the urgency of external data, non-emergency data is written to the memory in multiple times by asynchronous execution, to avoid lag caused by synchronous execution.
It effectively reduces the blocking time in the storage process, ensures the normal operation of the equipment, solves the equipment lag caused by synchronous execution, and reduces the equipment maintenance cost.
Smart Images
Figure CN116881182B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of embedded development, and in particular to an embedded data reading and writing method. Background Art
[0002] As more and more building users come, naturally there will be more salespeople, decorators, etc. In order to avoid unnecessary harassment of owners and residents, strengthen building security, and improve intelligent property management, intelligent elevator control management is particularly important. During operation, the elevator control device needs to store operating status information, pass records and other information, that is, the data that the device needs to store is given to the storage module, and the storage module returns the execution result after execution. The system executes other functional modules after the storage module is executed. This process is essentially synchronous execution. Synchronous execution storage is very dependent on the performance of the MCU. When the performance of the MCU is not enough and the number of functional modules executed is large, the execution process will be very slow, and the result is that the device runs stuck and the experience is very bad. Summary of the invention
[0003] The present invention provides an embedded data reading and writing method, which solves the problem in the related art that the synchronous execution and storage process is slow and easily causes the device to run stuck.
[0004] The technical solution of the present invention is as follows:
[0005] An embedded data reading and writing method is applied to a processor, including a data reading operation and a data writing operation.
[0006] The data writing operation includes:
[0007] Determine whether external data is received; the external data includes a flag, data to be stored and the length of the data to be stored;
[0008] When receiving external data, judging whether the data to be stored is urgent data or non-urgent data according to the flag bit, and storing the data to be stored in a buffer;
[0009] When the data to be stored is non-urgent data, the data in the buffer is written into the memory in multiple times, and after the last write operation is completed, the memory is returned to an idle state; after other secondary memory write operations are completed, the memory is returned to a write interruption state;
[0010] or
[0011] The data reading operation includes:
[0012] Determine whether a read data request is received; the read data request includes a flag bit, an address of data to be read, and a length of data to be read;
[0013] When receiving a data read request, determining whether the data to be read is urgent data or non-urgent data according to the flag bit;
[0014] When the data to be read is non-urgent data, the memory read operation is performed multiple times. After the last read operation is completed, the memory is returned to the idle state; after the other read operations are completed, the memory is returned to the read interrupt state.
[0015] The working principle and beneficial effects of the present invention are:
[0016] In the present invention, the processor determines the urgency of reading or writing data according to the flag bit of the external data. If the external data is non-urgent data, the storage task is divided into multiple executions (asynchronous execution), and the storage task is exited after writing 1 byte of data to be stored each time. In this way, the device does not need to wait for the completion of the storage task before executing other functional modules, which can effectively reduce the blocking time in the storage process, ensure the normal operation of the device, solve the device jam caused by synchronous execution, and reduce the device maintenance cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0018] Figure 1 Write data operation flow chart in the present invention;
[0019] Figure 2 This is a flow chart of the data reading operation in the present invention;
[0020] Figure 3 This is a flowchart of any data writing operation in the present invention;
[0021] Figure 4 is a flowchart of any data reading operation in the present invention;
[0022] Figure 5 A flow chart of a first embodiment of an embedded data reading and writing method of the present invention;
[0023] Figure 6 This is a flow chart of a second embodiment of an embedded data reading and writing method of the present invention. DETAILED DESCRIPTION
[0024] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0025] Example 1
[0026] This embodiment provides an embedded data reading and writing method, which is applied to a processor and includes a data reading operation and a data writing operation.
[0027] like Figure 1 As shown, the write data operation includes:
[0028] S110: Determine whether external data is received; the external data includes a flag, data to be stored, and the length of the data to be stored;
[0029] S120: upon receiving external data, determining whether the data to be stored is urgent data or non-urgent data according to the flag bit, and storing the data to be stored in a buffer;
[0030] The processor is used to receive external data and store (write) the received external data into the memory. The external data (external data is in the form of a data packet) includes a flag bit, data to be stored and the length of the data to be stored. The data to be stored is temporarily stored in the buffer. Before storing (writing) the external data, the urgency of the external data is first determined, and the urgency of the external data is distinguished according to the flag bit in the external data packet.
[0031] S130: When the data to be stored is non-urgent data, the data in the buffer is written into the memory in multiple times, and after the last write operation is completed, the memory is returned to an idle state; after other write operations to the memory are completed, the memory is returned to a write interruption state;
[0032] If the data to be stored in the buffer is non-urgent data, the data in the buffer is written into the memory in multiple times, that is, asynchronously executed, and 1 byte of the data to be written is written each time.
[0033] like Figure 3 As shown, any write operation includes:
[0034] S131: Determine whether the memory is idle. When the memory is idle, send the read and write operation enable instruction, the write operation instruction, the write operation start address and the data to be written in sequence; when the memory is in the write interrupt state, send the data to be written in this time;
[0035] Specifically, enable the read and write operation instructions, write operation instructions, write operation starting address and the data to be written this time to be written to the corresponding registers in the memory respectively. Taking the sending of the data to be written this time as an example, after the processor writes the data to be written this time into the write operation register, the memory takes out the data from the write operation register and stores it.
[0036] S132: Increase the number of write times by one;
[0037] S133: When the number of write operations is equal to the length of the data to be stored, any write operation is the last write operation, and the memory is returned to an idle state; otherwise, it is another write operation, and the memory is returned to a write interrupted state.
[0038] Taking the data to be stored as 10 bytes as an example, assuming that the 10 bytes are: 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A. When storing the first byte 0x01, the processor determines that the memory is in an idle state, and sends the enable read and write operation instructions, write operation instructions, and write operation starting address in sequence, and writes the data to be written 0x01 into the write operation register; the number of writes is 1; then, the memory takes out the data from the write register and stores it.
[0039] When storing the second byte 0x02, the processor determines that the memory is in a write interrupt state, and directly writes the data 0x02 to be written this time into the write operation register; the number of writes is 2; then, the memory takes out the data from the write operation register and stores it.
[0040] And so on…
[0041] When storing the 10th byte 0x0A, the processor determines that the memory is in a write interrupt state, and directly writes the data to be written 0x0A into the write operation register; the number of writes is 10, and the memory returns to an idle state.
[0042] like Figure 2 As shown, the data read operation includes:
[0043] S210: Determine whether a data read request is received; the data read request includes a flag, an address of data to be read, and a length of data to be read;
[0044] S220: upon receiving a data read request, determining whether the data to be read is urgent data or non-urgent data according to the flag bit;
[0045] S230: When the data to be read is non-urgent data, the memory read operation is performed multiple times. After the last read operation is completed, the memory is returned to the idle state; after the other read operations are completed, the memory is returned to the read interrupt state.
[0046] like Figure 4 As shown, any read operation includes:
[0047] S231: Determine whether the memory is idle. When the memory is idle, send the enable read and write operation instruction, the read operation instruction and the read operation start address in sequence, and receive the data returned by the memory as the current read data; when the memory is in the read interrupt state, receive the data returned by the memory as the current read data;
[0048] Specifically, the read and write operation enable instruction, write operation instruction, and write operation start address are respectively written into the corresponding registers in the memory. Taking the read and write operation enable instruction as an example, the processor writes the read and write operation enable instruction into the corresponding register to enable the memory read and write operation.
[0049] Each time the memory reads data from an address, it first puts the data into a read operation register, and the processor reads the data from the read operation register as the data read from the memory this time.
[0050] S232: increase the number of reads by one;
[0051] S233: When the number of reads is equal to the length of the data to be read, any one read operation is the last read operation, and the returned memory is in an idle state; otherwise, it is another read operation, and the returned memory is in a read interrupted state.
[0052] Taking the length of the data to be read = 10 as an example, when reading the first byte, the processor determines that the memory is in an idle state, and sends the enable read and write operation instruction, the read operation instruction and the read operation start address in sequence; the memory enables the read operation, starts to read data and writes it into the read operation register, and after the memory writes the data of the corresponding address into the read operation register, the processor reads the data from the read operation register, and the number of reads is 1;
[0053] When reading the second byte, the processor determines that the memory is in a read interrupt state, and the processor reads data from the read operation register as the data read this time; the number of reads is 2;
[0054] And so on…
[0055] When reading the 10th byte, the processor determines that the memory is in a read interrupt state, and the processor reads data from the read operation register as the data read this time; the number of reads is 10, and the memory is returned to an idle state.
[0056] Furthermore, when the data to be stored is urgent data, the data to be stored is written into the memory.
[0057] Furthermore, when the data to be read is urgent data, the data is read from the memory according to the address of the data to be read and the length of the data to be read.
[0058] For urgent data that needs to be stored immediately, it is necessary to read and write data from the memory synchronously (synchronous execution).
[0059] Further, if Figure 5 As shown,
[0060] The external data is card swiping module data, and the card swiping module data includes the number of card swiping times;
[0061] When the card swiping module data and the data in the memory are the same, the card swiping times are updated;
[0062] The card swipe times are stored in the card swipe module and the memory.
[0063] In this embodiment, taking the IC card swiping module as an example, the card swiping module of the elevator control system reads the IC card. When the card swiping module data and the data in the memory are the same, it is determined that the card swiping is successful. At the same time, the processor determines that the IC card data is non-emergency data and temporarily stores the IC card data in the buffer. The IC card is set with a card swiping count. Each time a card swiping operation is performed, the IC card swiping count is reduced by 1.
[0064] The card swiping module will determine whether to enable the anti-copying function according to business needs. If the anti-copying function is enabled, the card swiping times will be synchronously stored in the memory. In this way, through the synchronous update and comparison of the card swiping times, even if the IC card is copied into two or more, the total card swiping times will not increase, thereby playing an effective anti-copying function.
[0065] Example 2
[0066] like Figure 6 As shown, external data may also come from a network module.
[0067] The network module is a module with a large amount of data interaction, and its functions also interact with the storage. In actual applications, remote operation and control can only be performed normally after the network is connected normally;
[0068] When the network sends remote control commands, these commands are usually parameter modification or reading commands, which require reading or modifying data in the device memory. These operations are not real-time and urgent operations and can be performed when the memory is idle, that is, asynchronous execution. After the memory returns the processing results, the next module executes the corresponding operation.
[0069] When the device needs to be maintained through the network module, for example, upgrading, restoring to factory settings, etc., such maintenance functions are usually not performed when the device is in external use, but such functions need to be executed synchronously, that is, such functions belong to emergency functions.
[0070] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. An embedded data reading and writing method, applied to a processor, including a data reading operation and a data writing operation, characterized in that: The data writing operation includes: Determine whether external data is received; the external data includes a flag, data to be stored and the length of the data to be stored; When receiving external data, judging whether the data to be stored is urgent data or non-urgent data according to the flag bit, and storing the data to be stored in a buffer; When the data to be stored is non-urgent data, the data in the buffer is written into the memory in multiple times, and after the last write operation is completed, the memory is returned to an idle state; after other secondary memory write operations are completed, the memory is returned to a write interruption state; or The data reading operation includes: Determine whether a read data request is received; the read data request includes a flag bit, an address of data to be read, and a length of data to be read; When receiving a data read request, determining whether the data to be read is urgent data or non-urgent data according to the flag bit; When the data to be read is non-urgent data, the memory read operation is performed multiple times, and after the last read operation is completed, the memory is returned to an idle state; after the other read operations are completed, the memory is returned to a read interrupt state; When the data to be stored is urgent data, writing the data to be stored into a memory; When the data to be read is urgent data, the data is read from the memory according to the address of the data to be read and the length of the data to be read.
2. The embedded data reading and writing method according to claim 1, characterized in that: Any write operation includes: Determine whether the memory is idle. When the memory is idle, send the enable read and write operation instruction, write operation instruction, write operation start address and data to be written in sequence; when the memory is in write interrupt state, send the data to be written; Increase the number of writes by one; When the number of write times is equal to the length of the data to be stored, any one write operation is the last write operation, otherwise, it is another write operation.
3. The embedded data reading and writing method according to claim 1, characterized in that: Any read operation includes: Determine whether the memory is idle. When the memory is idle, send the enable read and write operation instruction, the read operation instruction and the read operation start address in sequence, and receive the data returned by the memory as the data read this time; when the memory is in the read interrupt state, receive the data returned by the memory as the data read this time; Increase the number of reads by one; When the number of reads is equal to the length of the data to be read, any one read operation is the last read operation, otherwise, it is another read operation.
4. The embedded data reading and writing method according to claim 1, characterized in that: The external data is card swiping module data, and the card swiping module data includes the number of card swiping times; When the card swiping module data and the data in the memory are the same, the card swiping times are updated; The card swipe times are stored in the card swipe module and the memory.
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