A charge steer digital phase detector and its charge steer sampling all-digital phase-locked loop

Abstract

The present invention discloses a charge rudder digital phase detector with high phase detection gain and a fractional frequency all-digital phase-locked loop based on the phase detector. The charge rudder digital phase detector includes a charge rudder sampling circuit, a capacitive digital-to-analog converter, a successive approximation analog-to-digital converter, etc. The charge rudder sampling circuit completes the charge presetting of the capacitor array in the digital-to-analog and analog-to-digital converters when the oscillator frequency division signal is at a high level, and performs the charge rudder sampling operation when the sampling pulse signal is triggered by the falling edge of the frequency division signal. The present invention compensates for the detected fractional frequency division periodic error by adjusting the lower plate access voltage of some capacitors of the capacitive digital-to-analog converter, so that the successive approximation analog-to-digital converter can directly digitize the detected phase error caused by phase noise for subsequent all-digital phase-locked loop operation. Therefore, the fractional frequency all-digital phase-locked loop based on the charge rudder digital phase detector can simultaneously obtain the performances of low jitter, low fractional frequency division spurious, and low reference spurious.

Description

Technical Field

[0001] The present invention relates to a phase detector, a filter and a phase-locked loop using the phase detector and the filter, and in particular to a charge rudder digital phase detector, a digital loop filter and a charge rudder sampling full digital phase-locked loop using the phase detector and the filter. Background Art

[0002] The analog phase-locked loop (PLL) chip is a negative feedback control system that uses the error between the phase of the voltage-controlled oscillator and the reference frequency to generate a synchronous voltage to tune the voltage-controlled oscillator to generate the target frequency. It mainly includes a phase detector (PFD), an analog filter, a VCO (voltage-controlled oscillator), and a fractional divider based on a delta-sigma modulator control. However, the traditional analog phase-locked loop has a low phase detection gain of the phase detector and a fractional frequency division scheme based on a delta-sigma modulator, which produces a large fractional frequency division quantization error, making it difficult to obtain a low-jitter target frequency signal to meet the 5G / 6G communication requirements.

[0003] In order to obtain low jitter frequency signals, the following technologies are commonly used:

[0004] For example, the charge injection locked phase-locked loop, however, has the following disadvantages: 1. The feedforward path performs direct phase and frequency calibration, resulting in poor reference spurious; 2. The phase lock position is unclear and may be locked to the rising or falling edge waveform of the oscillator; 3. It can essentially only be used in integer operating mode.

[0005] Another example is the sub-sampling phase-locked loop, but its disadvantages are: 1. The sampling process causes periodic interference to the phase-locked loop output waveform, resulting in poor reference spurious; 2. An analog loop filter is required, which occupies a large chip area; 3. The phase detection range is narrow and an additional frequency locking loop is required to ensure stable operation.

[0006] Another example is the traditional all-digital phase-locked loop (ADPLL), but its disadvantages are: 1. The quantization noise is large and is limited by an inverter delay; 2. It cannot provide high phase-detection gain, which reduces the loop bandwidth and cannot effectively suppress the oscillator phase noise.

[0007] Another example is the bang-bang phase-locked loop, but its disadvantages are: 1. Single-bit digital output, the phase-locked loop has a slow locking speed; 2. The phase-locked loop has a small locking range and is prone to losing lock.

[0008] At the same time, the fractional frequency division scheme based on the time-to-digital converter has the following disadvantages: 1. The phase noise of the digital-to-time converter itself deteriorates the phase noise of the phase-locked loop output; 2. The nonlinearity of the digital-to-time converter itself deteriorates the fractional spurious of the phase-locked loop; 3. The chip area is large, the sensitivity to parasitic parameters is high, it is affected by power supply ripple, and the design cost is high. Summary of the invention

[0009] In order to solve the technical problems of large quantization noise, low phase detection gain, poor output signal jitter and spurious error existing in the traditional all-digital phase-locked loop (ADPLL), and at the same time solve the technical problems of long locking time, narrow locking range and essentially only supporting integer division locking in the bang-bang phase-locked loop, the present invention provides a charge steered digital phase detector and a charge steered sampling fractional division all-digital phase-locked loop using the phase detector.

[0010] In addition, in order to solve the technical problems of high phase noise and low linearity in the fractional division scheme based on the digital time converter, the present invention provides a charge rudder sampling fractional division all-digital phase-locked loop based on a capacitive digital-to-analog converter and periodic fractional division error compensation in the charge domain.

[0011] The present invention is implemented by the following technical solution: a charge rudder digital phase detector, comprising:

[0012] Capacitive digital-to-analog converters that compensate for the inherent periodic phase error caused by fractional frequency division operations;

[0013] A successive approximation analog-to-digital converter, which is used to digitize the phase error;

[0014] The charge rudder sampling circuit, when the oscillator frequency division signal clk_div is at a high level, the capacitor array of the digital-to-analog converter and the analog-to-digital converter completes the charge presetting, and then when the sampling pulse signal clk_css is triggered by the falling edge of clk_div, the charge rudder sampling operation is performed: the phase difference Δt between clk_div and the input reference signal received by the charge rudder digital phase detector is detected err ; Among them, the phase error Δt err The random phase error Δt caused by the phase noise of the oscillator frequency division signal and the input reference signal err,pn That is, the charge domain ΔV err,pn and the inherent periodic phase error Δt caused by the fractional frequency operation of the phase-locked loop err,frac That is, the charge domain ΔV err,frac ; The input reference signal is a pair of sinusoidal differential signals V ref1 、V ref2 ;

[0015] Among them, by adjusting the lower plate access voltage of some capacitors of the capacitive digital-to-analog converter from V SSTo V ref,adc Compensation of the detected periodic phase error ΔV in the charge domain err,frac , which enables the successive approximation analog-to-digital converter to directly digitize the random phase error ΔV caused by phase noise detected err,pn ; The corresponding adjustment method is: the control word D of the capacitive digital-to-analog converter frac Relationship with corresponding compensation voltage ΔV err,frac =D frac ·C unit / (C frac +C sar )·V ref,adc , where C unit is the unit capacitance of the capacitor array in the digital-to-analog and analog-to-digital converters, C frac is the total capacitance of the capacitive DAC, C sar is the total capacitance of the successive approximation ADC.

[0016] Capacitive DACs include:

[0017] A capacitor array includes a plurality of unit capacitors C unit , multiple C unit The two ends are connected together to form a capacitor C frac The two upper plates are connected to the differential output end of the charge rudder sampling circuit;

[0018] With multiple C unit The corresponding multiple bidirectional selection switches have one end electrically connected to the corresponding C unit The lower plate of the , the other end of which is a bidirectional selection terminal, one of which can be connected to the voltage V ref,adc , the other direction can be connected to the low level V SS ;

[0019] Further, the oscillator frequency division signal clk_div is delayed to obtain clk_frac, whose falling edge is used to control the capacitive digital-to-analog converter to compensate for the fractional frequency division error in the charge domain; clk_frac is delayed to obtain the signal clk_sar, whose rising edge controls the capacitive digital-to-analog converter to reset.

[0020] As a further improvement of the above solution, the charge steering sampling circuit includes a pair of switches S1, one end of which is electrically connected to a voltage source V DD , while the other end is electrically connected to the upper plate shared by the two converters;

[0021] The charge steering sampling circuit comprises a pair of switches S2 and a group of differential pair transistors M1 and M2; the pair of switches S2 are electrically connected to C frac and C sarThe upper plate of the upper plate is shared by the upper plate, and the other end is electrically connected to the drain of M1 and M2 respectively, and the gate of M1 and M2 is connected to the sinusoidal differential reference signal V ref1 、V ref2 , the sources of M1 and M2 are electrically connected to the low level V ss ;

[0022] When clk_div is at a high level, C frac and C sar The upper plate is charged to the high level V through the corresponding S1 DD , while C frac and C sar The lower plate is set to a low level V by the rising edge of clk_sar obtained by delaying clk_div SS , complete the C frac and C sar Charge preset;

[0023] The falling edge of clk_div triggers the sampling pulse clk_css to turn on the corresponding S2 to perform the charge steering sampling operation.

[0024] As a further improvement of the above scheme, the sinusoidal differential reference signal V ref1 、V ref2 The sine differential reference signal V is generated by an on-chip sinusoidal differential reference signal generator, which includes an off-chip high-Q value resonant cavity and an on-chip amplifier circuit. The same-direction end and the reverse-direction end of the on-chip amplifier circuit are electrically connected to the two ends of the high-Q value resonant cavity, respectively. ref1 、V ref2 Output from the two output terminals of the on-chip amplifier circuit.

[0025] The present invention also provides a digital loop filter, which includes a proportional path γ and an integral path ρ. The digital loop filter also includes an intermediate up-converter and a dead zone. The input signal of the digital loop filter is passed through the intermediate up-converter to obtain an output signal D err , and then directly enters the proportional path γ on the one hand, and enters the integral path ρ on the other hand.

[0026] As a further improvement of the above scheme, the input signal of the digital loop filter is the output signal D of the successive approximation analog-to-digital converter in any charge rudder digital phase detector mentioned above. out .

[0027] Furthermore, the proportional path γ includes a shift module 1, which is used to shift the output signal D of the intermediate encoder err Shifting to obtain the output signal of the proportional path γ;

[0028] And / or, the integral path ρ includes a dead zone, an accumulator and a shift module 2; Derr The output signal of the integral path ρ is obtained through the dead zone, the accumulator and the shift module 2.

[0029] The present invention also provides a charge rudder sampling all-digital phase-locked loop, which comprises:

[0030] Charge rudder digital phase detector, detects the oscillator frequency division signal clk_div and the sinusoidal differential reference signal V ref1 、V ref2 The phase error is output as a digital phase error signal D out ;

[0031] The digital loop filter is used to digitize the phase error signal D out Perform digital filtering;

[0032] The digital controlled oscillator is used to output the final desired frequency signal, whose frequency is controlled by the filtered D out control;

[0033] A current mode fixed frequency divider, which is used to down-convert the pair of oscillator frequency signals into a preliminary frequency division signal that can be supported by the multi-mode frequency divider;

[0034] The multi-mode frequency divider is used for converting the preliminary frequency division signal into the frequency division signal clk_div required for fractional frequency division under the control of the delta-sigma modulator.

[0035] As a further improvement of the above solution, the digital loop filter is the above digital loop filter.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The charge rudder sampling phase detector has a high phase detection gain, which has a very high suppression capability for the phase detector noise itself, and at the same time makes the loop have a high bandwidth to suppress the phase noise of the digital controlled oscillator (DCO); the isolation between the reference signal and the oscillator frequency division signal in the charge rudder is good, which can effectively suppress the reference spurious;

[0038] 2. The fractional frequency division scheme uses the charge steering and capacitive digital-to-analog converter (FRAC-N CDAC) scheme, which has the characteristics of low noise and high linearity, thus making the fully digital phase-locked loop architecture have the advantages of low phase noise and low fractional spurious. In addition, this scheme has a compact structure, small area and low power consumption;

[0039] 3. The multi-bit digital phase output of the charge rudder digital phase detector effectively improves the locking speed and locking range of the fully digital phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1This is a circuit diagram of a fractional-frequency charge rudder digital phase detector provided in Example 1 of the present invention.

[0041] Figure 2 for Figure 1 Working timing diagram of small and medium frequency charge rudder digital phase detector.

[0042] Figure 3 for Figure 1 Detailed working timing diagram of small and medium frequency charge rudder digital phase detector.

[0043] Figure 4 for Figure 1 Working principle diagram of small-to-medium frequency charge-steering digital phase detector.

[0044] Figure 5 This is a schematic diagram of the detection gain enhancement principle of the intermediate up-encoder of the charge rudder sampling all-digital phase-locked loop provided in Example 2 of the present invention.

[0045] Figure 6 for Figure 5 Circuit diagram of the fully digital phase-locked loop with fractional frequency sampling using charge rudder. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] Example 1

[0048] See also Figure 1 , which is a circuit diagram of a charge steer digital phase detector (CSS-PD) provided in Example 1 of the present invention. The charge steer digital phase detector includes a charge steer sampling circuit, a capacitive digital-to-analog converter (Frac-NC-DAC), and a successive approximation analog-to-digital converter (SAR-ADC).

[0049] The charge steering sampling circuit includes a pair of switches S1, one end of which is electrically connected to a high level V DD , and the other end is electrically connected to the common upper plate of the two converters. The charge steering sampling circuit includes a pair of switches S2 and a set of differential pairs of tubes M1 and M2. One end of the switch S2 is electrically connected to the upper plate of the converter, and the other end is electrically connected to the drain of M1 and M2. The gates of M1 and M2 are connected to the sinusoidal differential reference signal V ref1 、V ref2 , the drains of M1 and M2 are electrically connected to the low level V ss .

[0050] Please combine Figure 2 and Figure 3 , the charge steering sampling circuit completes the charge presetting of the capacitor arrays of the above two converters when the oscillator frequency division signal clk_div is at a high level. In this embodiment, when clk_div is at a high level, C frac and C sar The upper plate is charged to the high level V through the corresponding S1 DD , while C frac and C sar The lower plate is set to a low level V by the rising edge of clk_sar obtained by delaying clk_div SS , complete C frac and C sar Charge preset.

[0051] After charge presetting, the charge rudder sampling circuit performs a charge rudder sampling operation when the sampling pulse signal clk_css is triggered by the falling edge of the frequency division signal clk_div: the phase difference Δt between the oscillator frequency division signal clk_div and the input reference signal received by the charge rudder digital phase detector is detected. err . Among them, the phase error Δt err Contains random phase error Δt caused by phase noise err,pn (i.e., charge domain ΔV err,pn ) and the inherent periodic phase error Δt caused by the fractional frequency division operation of the phase-locked loop err,frac That is, the charge domain ΔV err,frac ; The input signal is a pair of sinusoidal differential reference signals V ref1 、V ref2 In this embodiment, the falling edge of clk_div triggers the sampling pulse clk_css to turn on the corresponding S2 to perform the charge steering sampling operation.

[0052] The charge rudder digital phase detector adjusts the voltage of the lower plate of the capacitor of the capacitive digital-to-analog converter from V SS To V ref,adc Compensation for detected fractional charge errors ΔV err,frac , which enables the successive approximation analog-to-digital converter to directly digitize the detected phase error ΔV caused by phase noise. err,pn ; The corresponding adjustment method is: the control word D of the capacitive digital-to-analog converter frac Relationship with corresponding compensation voltage ΔV err,frac =D frac ·C unit / (C frac +C sar )·V ref,adc , where C unit is the unit capacitance of the capacitor array in the digital-to-analog and analog-to-digital converters, Cfrac is the total capacitance of the capacitive DAC, C sar is the total capacitance of the successive approximation ADC.

[0053] Capacitive digital-to-analog converter (C-DAC) is used for fractional error compensation, and successive approximation analog-to-digital converter is used to digitize phase error. frac The upper plate and the capacitor C of the SAR-ADC sar The upper plate of C-DAC is shared by the capacitor C frac The lower plate also shares the SAR-ADC reference voltage V through an independent control switch. ref,adc and low level V SS .

[0054] The capacitive digital-to-analog converter includes: a capacitor array and a plurality of bidirectional selection switches. The capacitor array includes a plurality of unit capacitors, one end of which is connected together to form a capacitor C frac The upper plate of capacitor C frac The two upper plates are connected to the output end of the charge steering sampling circuit. Multiple bidirectional selection switches correspond to the unit capacitors, one end of which is electrically connected to the other end of the corresponding unit capacitor, and the other end is a bidirectional selection end, one of which can be connected to the voltage V ref,adc , the other direction can be connected to the low level V SS .

[0055] The oscillator frequency division signal clk_div is delayed to obtain the control signal clk_frac, whose falling edge controls the capacitive digital-to-analog converter C-DAC to compensate the fractional frequency division error in the charge domain; the pulse signal clk_frac is delayed to obtain the control signal clk_sar, whose rising edge controls the capacitive digital-to-analog converter C-DAC to reset.

[0056] Figure 3 Detailed timing diagram of the proposed fractional-frequency charge-steering digital phase detector, showing the mechanism of periodic fractional detection error and its charge domain compensation (in terms of T ref =(4+1 / 3)T osc As an example, all phase noise and static phase error are ignored. Meanwhile, the SAR-ADC of the present invention has multi-bit output, and has advantages of fast locking speed and large locking range compared with the traditional Bang-Bang type phase-locked loop.

[0057] Please combine Figure 4 (It can also be combined with Example 2 Figure 6 ), the working principle of CSS-PD is as follows.

[0058] (1) Charge preset.

[0059] When clk_div is at a high level, the charge steering digital phase detector (CSS-PD) will frac and C sar The upper plate is charged to a high level V through S1 DD , and their lower plates are placed at a low level V by the rising edge of clk_sar (delayed by clk_div) SS , complete C frac and C sar Charge preset.

[0060] (2) Charge rudder sampling.

[0061] The falling edge of clk_div triggers the sampling pulse clk_css to turn on S2 to perform charge steering sampling operation to detect clk_div and the input standard sinusoidal differential reference signal V ref1,2 The phase difference between the output oscillator frequency signal and the input reference frequency signal. frac and C sar The differential charge on M1 and M2 is discharged through M1 and M2 respectively. The net discharge amount of M1 and M2 depends on clk_css and V ref1 -V ref2 The overlapping area of Figure 4 The shaded area on the right and the shaded area on the left are shown. frac and C sar The differential residual charge ΔV err Represents the detected phase error Δt err .

[0062] (3) Fractional frequency charge compensation.

[0063] When the PLL operates in fractional frequency division mode, the detected phase error Δt err Contains the error part Δt caused by phase noise (PN) err,pn (i.e. ΔV in the charge / voltage domain err,pn ) and the periodic fractional detection error part Δt err,frac (i.e. ΔV in the charge / voltage domain err,frac ). In order to compensate for the periodic fractional detection error, the present invention proposes to replace the traditional time-to-digital converter (DTC) solution with a capacitive digital-to-analog converter (C-DAC). By adjusting the voltage V ref,adc , used to compensate for the detected fractional charge error ΔV err,frac . C-DAC control word D frac Relationship with corresponding compensation voltage ΔV err,frac =D frac ·C unit / (Cfrac +C sar )·V ref,adc , where C unit is the unit capacitance of the capacitor array. Figure 3 The generation mechanism of periodic fractional detection error and its charge domain compensation (in terms of T ref =(4+1 / 3)T osc As an example, ignoring all phase noise and static phase error), where T ref and T osc They are the reference frequency period and the oscillator period respectively. clk_osc represents the square wave V osc (To clearly show its zero crossing).

[0064] (4)Digitalization

[0065] After compensating for the fractional charge error, the SAR-ADC directly digitizes the detected phase error ΔV caused by phase noise. err,pn , used for subsequent all-digital phase-locked loop operation.

[0066] The charge rudder sampling phase detector of this embodiment has a high phase detection gain and has a very high suppression capability for the noise of the phase detector itself, while making the loop have a high bandwidth to suppress the phase noise of the DCO; the isolation between the reference signal and the oscillator in the charge rudder is good, which can effectively suppress the reference spurious.

[0067] Example 2

[0068] See also Figure 5 , which is a circuit diagram of a charge steer sampling all-digital phase-locked loop provided in Example 2 of the present invention. The charge steer sampling all-digital phase-locked loop of this embodiment includes a charge steer digital phase detector (CSS-PD), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a current mode (CML) fixed divider, and a multi-mode divider (MMDIV). The charge steer digital phase detector detects the oscillator frequency division signal clk_div and the input sinusoidal differential reference signal V ref1 、V ref2 The phase difference outputs the digital phase error signal D out In this embodiment, the charge steer digital phase detector uses the charge steer digital phase detector in Embodiment 1.

[0069] The feed-forward path of the charge-steering sampling all-digital phase-locked loop contains the proposed CSS-PD, SAR-ADC, C-DAC, and a digital loop filter (DLF) and DCO using a mid-ramp encoder (MRE).

[0070] The digital loop filter (DLF) is used to filter the digital phase error signal D outFor digital filtering, the DLF generally includes a proportional path γ and an integral path ρ. However, in this embodiment, the DLF also includes an intermediate up-encoder (MRE) and a dead zone (DZ). The input signal of the digital loop filter (DLF) passes through the intermediate up-encoder (MRE) and then directly enters the proportional path γ on the one hand, and passes through the dead zone (DZ) and then enters the integral path ρ on the other hand.

[0071] Since there is a controllable dead zone (DZ) at the front of the integral path ρ, the integral path ρ can be disabled after phase locking to avoid conflicts between the two control paths. This approach can greatly improve the clock jitter performance of the phase-locked loop. The output of the DLF directly controls the capacitor switch array of the DCO, and changes the oscillation frequency of the DCO by changing the capacitor value connected to the DCO and realizing the phase calibration of the DCO output signal.

[0072] The frequency signal output by the digitally controlled oscillator (DCO) is converted into a preliminary frequency division signal (entering the operating frequency range of the multi-mode divider) by the current mode (CML) fixed divider and the multi-mode divider (MMDIV). The multi-mode divider converts the preliminary frequency division signal into the frequency division signal clk_div under the control of the delta-sigma modulator signal. The feedback path of the phase-locked loop includes the CML2 divider and MMDIV, and the delta-sigma controller controls the MMDIV to realize the fractional frequency division function. At the same time, the detection error D is used err The C-DAC gain is calibrated by the LMS algorithm to reduce fractional spurious.

[0073] Figure 6 The charge steer digital phase detector shows that when clk_css samples the reference signal V ref1,2 When the discharge node V err1,2 The charge steering sampling operation proposed in the present invention has a wide linear phase detection range, up to T, compared with the traditional sub-sampling phase-locked loop. ref / 4. Therefore, when the periodic fractional phase detection error Δt err,frac Range close to maximum + / -T osc , which is in the proposed CSS-PD linear working area. Linear compensation can be achieved through C-DAC to obtain excellent fractional spurious performance. However, due to the low slope of the reference signal, the phase detection gain of the charge steering sampling reference signal is small. Therefore, we propose to use the intermediate encoder (MRE) to re-encode the result of the SAR-ADC output, so that the phase detection gain does not depend on the slope of the reference signal but on the clock jitter of the reference signal, which greatly improves the phase detection gain. Figure 6 The upper right image area of ​​.

[0074] The fractional frequency division scheme of this embodiment uses a charge steering and digital-to-analog converter scheme, which has the characteristics of low noise and high linearity, thereby making the fully digital phase-locked loop architecture have the advantages of low phase noise and low spurious. In addition, this scheme has a compact structure, small area and low power consumption.

[0075] In this embodiment, the sinusoidal differential reference signal V ref1 、V ref2 It can be generated by a sinusoidal differential reference signal generator, which includes a high-Q resonant cavity and an on-chip amplifier circuit (–g m ), on-chip amplifier circuit (–g m ) are electrically connected to the two ends of the high Q value resonant cavity, and the sinusoidal differential reference signal V ref1 、V ref2 By on-chip amplifier circuit (–g m ) output at two output terminals. Standard reference signal V ref The high-Q resonant cavity and on-chip amplifier circuit (–g m ) is generated, which can make V ref With extremely low phase noise levels, the reference signal noise is not limited by the input buffer.

[0076] In this regard, in this embodiment, two experimental examples are taken as examples for detailed description.

[0077] (1) Input reference signal V ref The frequency is 250MHz, the fractional frequency control word N frac =0, the division ratio of MMDIV is fixed to 48, combined with the CML2 divider, the total division ratio is 96, and the DCO output frequency is locked at 24GHz. At this time, the C-DAC and LMS algorithm are not working, and their control word D frac Keep it to 0, the phase error detected by CSS-PD only includes the phase error caused by loop phase noise. Set the DLF proportional path γ = 1, and after locking, set the dead zone size to shift right by two bits to disable the integral path. At this time, the control word of the DCO will jump between two digital numbers to achieve phase-locked loop locking.

[0078] (2) Input reference signal V ref The frequency is 250MHz, the fractional frequency control word N frac =1 / 3, input frequency division ratio control word N int Set to 48, DSM is set to 1st order, then the MMDIV division ratio will be periodically set to 48, 48, 49, combined with the CML2 divider, the total division ratio will be periodically set to 96, 96, 98, and the DCO output frequency will be locked at 24.167GHz. At this time, the C-DAC will periodically compensate 1 / 3T osc, 2 / 3T osc , the charge error corresponding to 0. The output D of MRE err The compensation gain of C-DAC will be calibrated by LMS algorithm. Set the proportional path of DLF γ = 1, and after locking, set the dead zone size to shift right by two bits to disable the integral path. At this time, the control word of DCO will jump between two digital numbers to achieve phase-locked loop locking.

[0079] It can be seen from the two embodiments that the present invention has the following advantages.

[0080] 1. The multi-bit output digital phase detector proposed in this project, which is formed by the fusion of charge steering sampling technology and successive approximation analog-to-digital converter in the charge domain, has high phase detection gain, has extremely high suppression capability for the noise of the phase detector itself, and at the same time enables the loop to have high bandwidth to suppress the phase noise of the DCO. In addition, compared with the sub-sampling phase-locked loop, the isolation between the reference signal and the oscillator in the charge steering is good, which can effectively suppress the reference spurious.

[0081] 2. The fractional frequency division scheme uses charge rudder sampling and capacitive digital-to-analog converter scheme. Compared with the scheme based on digital time converter, this scheme has the characteristics of low noise and high linearity, which makes the fully digital phase-locked loop architecture have the advantages of low phase noise and low spurious. In addition, this scheme has a compact structure, small area and low power consumption. Among them, the capacitors in the charge rudder sampling phase detector (CSS-PD) and the capacitive digital-to-analog converter can directly reuse the capacitors of the successive approximation analog-to-digital converter.

[0082] 3. The present invention effectively improves the locking speed and locking range of the all-digital phase-locked loop through the multi-bit digital phase output of the charge rudder digital phase detector. This effectively overcomes the disadvantage of the long locking time of the phase-locked loop based on the bang-bang phase detector (i.e., 1-bit digital phase output).

[0083] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A charge steer digital phase detector, characterized in that: It includes: A capacitive digital-to-analog converter used to compensate for the inherent periodic phase error caused by the fractional frequency division operation of a phase-locked loop; The successive approximation analog-to-digital converter is used to digitize the phase error; the capacitor C of the capacitive digital-to-analog converter frac The upper plate and the capacitor C of the successive approximation analog-to-digital converter sar The upper plate of the capacitive DAC is shared by frac The lower plate also shares the reference voltage V of the successive approximation analog-to-digital converter through an independent control switch. ref,adc and low level V SS ; The charge rudder sampling circuit, when the oscillator frequency division signal clk_div is at a high level, the capacitor array of the digital-to-analog converter and the analog-to-digital converter completes the charge presetting, and then when the sampling pulse signal clk_css is triggered by the falling edge of clk_div, the charge rudder sampling operation is performed: the phase difference Δt between clk_div and the input reference signal received by the charge rudder digital phase detector is detected err ; Among them, the phase error Δt err The random phase error Δt caused by the phase noise of the oscillator frequency division signal and the input reference signal err,pn That is, the charge domain ΔV err,pn and the inherent periodic phase error Δt caused by the fractional frequency operation of the phase-locked loop err,frac That is, the charge domain ΔV err,frac ; The input reference signal is a pair of sinusoidal differential signals V ref1 、V ref2 The charge steering sampling circuit includes a pair of switches S1, one end of which is electrically connected to a high level V DD , and the other end is electrically connected to the upper plate shared by the two converters; the charge steering sampling circuit includes a pair of switches S2 and a group of differential pairs of tubes M1 and M2; one end of the pair of switches S2 is electrically connected to C frac and C sar The other end is connected to the drain of M1 and M2 respectively, and the gate of M1 and M2 is connected to the sinusoidal differential reference signal V ref1 、V ref2 , the sources of M1 and M2 are electrically connected to the low level V ss ; When clk_div is at a high level, C frac and C sar The upper plate is charged to a high level V through S1 conduction DD , while C frac and C sar The lower plate is set to a low level V by the rising edge of clk_sar obtained by delaying clk_div SS , complete the C frac and C sar The charge is preset; the falling edge of clk_div triggers the sampling pulse clk_css to turn on the corresponding S2 and disconnect S1 to perform the charge steering sampling operation; Among them, by adjusting the lower plate access voltage of some capacitors of the capacitive digital-to-analog converter from the low level V SS to the reference voltage V ref,adc Compensation of the detected periodic phase error ΔV in the charge domain err,frac , which enables the successive approximation analog-to-digital converter to directly digitize the random phase error ΔV caused by phase noise detected err,pn ; The corresponding adjustment method is: the control word D of the capacitive digital-to-analog converter frac Relationship with corresponding compensation voltage ΔV err,frac =D frac ·C unit / (C frac +C sar )·V ref,adc , where C unit is the unit capacitance of the capacitor array in the digital-to-analog and analog-to-digital converters, C frac is the total capacitance of the capacitive DAC, C sar is the total capacitance of the successive approximation ADC.

2. The charge steer digital phase detector according to claim 1, characterized in that: Capacitive DACs include: A capacitor array includes a plurality of unit capacitors C unit , multiple C unit The two ends are connected together to form a capacitor C frac The two upper plates are connected to the differential output end of the charge rudder sampling circuit; With multiple C unit The corresponding multiple bidirectional selection switches have one end electrically connected to the corresponding C unit The lower plate of the , the other end of which is a bidirectional selection terminal, one of which can be connected to the voltage V ref,adc , the other direction can be connected to the low level V SS .

3. The charge steer digital phase detector as claimed in claim 2, characterized in that: The oscillator frequency division signal clk_div is delayed to obtain clk_frac, whose falling edge is used to control the capacitive digital-to-analog converter to compensate for the fractional frequency division periodic phase error in the charge domain; clk_frac is delayed to obtain the signal clk_sar, whose rising edge controls the capacitive digital-to-analog converter to reset.

4. The charge steer digital phase detector according to claim 1, characterized in that: Sinusoidal differential reference signal V ref1 、V ref2 The sine differential reference signal V is generated by an on-chip sinusoidal differential reference signal generator, which includes an off-chip high-Q value resonant cavity and an on-chip amplifier circuit. The same-direction end and the reverse-direction end of the on-chip amplifier circuit are electrically connected to the two ends of the high-Q value resonant cavity, respectively. ref1 、V ref2 Output from the two output terminals of the on-chip amplifier circuit.

5. A digital loop filter, comprising a proportional path γ and an integral path ρ, characterized in that: The digital loop filter also includes an intermediate up-converter and a dead zone. The input signal of the digital loop filter is passed through the intermediate up-converter to obtain the output signal D err It is divided into two signals, one of which directly enters the proportional path γ, and the other enters the integral path ρ after passing through the dead zone. The outputs of the proportional path γ and the integral path ρ are synthesized. The input signal of the digital loop filter is the output signal D of the successive approximation analog-to-digital converter in the charge steer digital phase detector as claimed in any one of claims 1 to 4. out .

6. The digital loop filter according to claim 5, characterized in that: The proportional path γ includes a shift module 1, which is used to shift the output signal D of the intermediate encoder. err The output signal of the proportional path γ is obtained by shifting.

7. The digital loop filter according to claim 5, wherein: The integral path ρ includes a dead zone, an accumulator and a shift module 2; D err The output signal of the integral path ρ is obtained through the dead zone, the accumulator and the shift module 2.

8. A charge rudder sampling all-digital phase-locked loop, comprising: The charge steer digital phase detector according to any one of claims 1 to 4, detecting the oscillator frequency division signal clk_div and the sinusoidal differential reference signal V ref1 、V ref2 The phase error is output as a digital phase error signal D out ; The digital loop filter is used to digitize the phase error signal D out Perform digital filtering; The digital controlled oscillator is used to output the final desired frequency signal, whose frequency is controlled by the filtered D out control; A current mode fixed frequency divider, which is used to down-convert the pair of oscillator frequency signals into a preliminary frequency division signal that can be supported by the multi-mode frequency divider; The multi-mode frequency divider is used for converting the preliminary frequency division signal into the frequency division signal clk_div required for fractional frequency division under the control of the delta-sigma modulator.

9. The charge steer sampling all-digital phase-locked loop according to claim 8, characterized in that: The digital loop filter has a proportional path γ and an integral path ρ. The digital loop filter also includes an intermediate up-converter and a dead zone. The output signal D obtained by the input signal of the digital loop filter after passing through the intermediate up-converter is err It is divided into two signals, one signal directly enters the proportional path γ, and the other signal enters the integral path ρ after passing through the dead zone. The outputs of the proportional path γ and the integral path ρ are synthesized.

10. The charge steer sampling all-digital phase-locked loop according to claim 9, characterized in that: The proportional path γ includes a shift module 1, which is used to shift the output signal D of the intermediate encoder. err The output signal of the proportional path γ is obtained by shifting.

11. The charge steer sampling all-digital phase-locked loop according to claim 9, characterized in that: The integral path ρ includes a dead zone, an accumulator and a shift module 2; D err The output signal of the integral path ρ is obtained through the dead zone, the accumulator and the shift module 2.

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