Real-time simulation data transmission method, device, equipment and storage medium

By using DMA operation and fiber optic communication technology on the FPGA of the real-time simulation node and adding serial numbers to the tail of the data frame for detection, the problem of data transmission in the prior art does not take into account microsecond real-time performance, achieving more efficient Real-time data transmission.

CN117579224BActive Publication Date: 2025-02-14ELECTRIC POWER RES INST CHINA SOUTHERN POWER GRID CO LTD
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Patent Information

Application Number
CN202311534087.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-11-16
Publication Date
2025-02-14
Estimated Expiration
2043-11-16

AI Technical Summary

Technical Problem

Existing real-time simulation nodes do not consider microsecond real-time when data transmission, resulting in large time jitter and difficult to meet higher transmission needs.

Method used

By deploying FPGAs on the simulation sending side and receiving side, data transmission is performed using DMA operations and fiber optic communication technology, and a serial number is added at the tail of the data frame. The receiving side detects whether the serial number is increased to determine the reception of new data by polling.

Benefits of technology

Reduces time jitter caused by interrupting and switching CPU processes, improves the real-timeness of data transmission, and can meet higher transmission needs.

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Abstract

The present application discloses a real-time simulation data transmission method, device, equipment and storage medium, the method comprising: judging whether there is a data frame to be sent on the simulation sending side, if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1; sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology by the FPGA of the simulation sending side to obtain a received data frame; judging whether the frame tail sequence number of the received data frame increases by the FPGA of the simulation receiving side, if so, extracting the received data frame in the receiving buffer and saving it. The simulation receiving side can detect new data directly by polling whether the frame tail sequence number increases without interruption, thereby reducing the time jitter caused by interrupting the switching of the CPU process. Therefore, the present application can solve the technical problem that the existing data transmission and reception does not consider the real-time performance at the microsecond level, the time jitter is large, and it is difficult to meet the higher transmission requirements of the existing data.
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Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a real-time simulation data transmission method, device, equipment and storage medium. Background Art

[0002] At present, Ethernet is often used for data communication between different real-time simulation nodes, and the medium can be ordinary network cables or optical fibers. However, the real-time simulation nodes may not use real-time operating systems, use third-party network cards, and the Ethernet card driver does not consider real-time performance, resulting in large jitter in data transmission and reception time, which cannot meet the microsecond-level real-time requirements. Summary of the invention

[0003] The present application provides a real-time simulation data transmission method, device, equipment and storage medium for solving the technical problem that the existing data transmission and reception does not take into account the real-time performance at the microsecond level, has large time jitter, and is difficult to meet the higher transmission requirements of the existing data.

[0004] In view of this, the first aspect of the present application provides a real-time simulation data transmission method, comprising:

[0005] Determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1;

[0006] The FPGA of the simulation sending side sends the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology to obtain a received data frame;

[0007] The FPGA on the simulated receiving side determines whether the frame tail sequence number of the received data frame increases. If so, the received data frame is extracted and saved in the receiving buffer.

[0008] Preferably, the step of judging whether there is a data frame to be sent on the simulated sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1, further comprises:

[0009] A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0010] Preferably, the step of sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulation sending side to obtain the received data frame includes:

[0011] Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface;

[0012] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

[0013] Preferably, the FPGA of the simulated receiving side is used to determine whether the frame tail sequence number of the received data frame increases, and if so, the received data frame is extracted and saved in the receiving buffer, and the method also includes:

[0014] The FPGA at the simulated receiving side initiates a DMA operation to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0015] A second aspect of the present application provides a real-time simulation data transmission device, comprising:

[0016] The tail frame processing unit is used to determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1;

[0017] A data sending unit, used to send the data frame to be sent to the simulation receiving side through the FPGA of the simulation sending side based on DMA operation and optical fiber communication technology to obtain a received data frame;

[0018] The receiving judgment unit is used to judge whether the frame tail sequence number of the received data frame is increased through the FPGA of the simulated receiving side, and if so, extract the received data frame in the receiving buffer and save it.

[0019] Preferably, it also includes:

[0020] The buffer configuration unit is used to allocate a fixed-size buffer to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0021] Preferably, the data sending unit is specifically used for:

[0022] Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface;

[0023] The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame.

[0024] Preferably, it also includes:

[0025] The data reading unit is used to initiate a DMA operation through the FPGA of the simulated receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0026] A third aspect of the present application provides a real-time simulation data transmission device, the device comprising a processor and a memory;

[0027] The memory is used to store program code and transmit the program code to the processor;

[0028] The processor is used to execute the real-time simulation data transmission method described in the first aspect according to the instructions in the program code.

[0029] A fourth aspect of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store program code, and the program code is used to execute the real-time simulation data transmission method described in the first aspect.

[0030] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0031] In the present application, a real-time simulation data transmission method is provided, including: judging whether there is a data frame to be sent on the simulation sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1; sending the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology by the FPGA of the simulation sending side to obtain a received data frame; judging whether the frame tail sequence number of the received data frame is increased by the FPGA of the simulation receiving side, and if so, extracting and saving the received data frame in the receiving buffer.

[0032] The real-time simulation data transmission method provided by the present application can determine in real time whether there is a data frame to be sent on the simulation sending side, put the sequence number at the end of the frame, and increase the frame end sequence number of the data frame to be sent by 1 before sending the data. The simulation receiving side can directly detect new data by polling whether the frame end sequence number is increased without interrupting the operation, thereby reducing the time jitter caused by interrupting the switching of the CPU process and improving the real-time performance of data transmission. Therefore, the present application can solve the technical problem that the existing data transmission and reception does not consider the real-time performance of microsecond level, the time jitter is large, and it is difficult to meet the higher transmission requirements of the existing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A flowchart of a real-time simulation data transmission method provided in an embodiment of the present application;

[0034] Figure 2 A structural diagram of a real-time simulation data transmission device provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a real-time simulation data transmission system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] For easier understanding, see Figure 1 , an embodiment of a real-time simulation data transmission method provided by the present application includes:

[0038] Step 101: determine whether there is a data frame to be sent on the simulated sending side. If yes, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1.

[0039] Furthermore, step 101, before that, also includes:

[0040] A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0041] It should be noted that the operation of the simulated sending side to determine whether there are data frames to be sent can be performed in real time, and the simulated sending side will pre-configure a buffer for storing the data to be sent. In order to avoid time jitter caused by reallocation of memory during data transmission, this embodiment uses a fixed-size buffer allocation method to determine the size of the sending buffer of the simulated sending side. Similarly, the simulated receiving side also allocates a buffer based on this principle to obtain a fixed-size receiving buffer.

[0042] Placing the sequence number at the end of the data frame to be sent and increasing the sequence number of the end frame by 1 allows the receiving side to quickly and efficiently determine whether a new frame of data has been received by simply detecting whether the sequence number of the end frame has increased. The operation process is simple, the detection method is efficient, and the time jitter caused by complex process switching can be avoided, thereby improving the efficiency of real-time data transmission.

[0043] Step 102: Send the data frame to be sent to the simulated receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulated sending side to obtain a received data frame.

[0044] Further, step 102 includes:

[0045] By simulating the FPGA on the sending side, a DMA operation is initiated to read the data frames to be sent in the sending buffer into the FPGA through the pice8x interface;

[0046] The optical fiber communication technology of the multi-channel aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain the received data frame.

[0047] Both the simulated sending side and the simulated receiving side are deployed with FPGA, and both can realize data reading and data transmission and reception based on DMA operation. FPGA can determine the data packet size of the data frame to be sent and the location of the data buffer, that is, the memory address, according to the received control instruction; then actively initiate a DMA operation to read the data to be sent into the FPGA through the pice8x interface; during the data reading process, the data frame to be sent can be transmitted to the simulated receiving side through multiple optical fiber communications based on the aurora protocol to generate a received data frame; and it can be understood that the received data frame is stored in the receiving buffer, and the simulated receiving side can determine the data packet size and memory address and other information based on the received data frame in the receiving buffer.

[0048] Step 103: Determine whether the frame tail sequence number of the received data frame increases by simulating the FPGA on the receiving side. If so, extract the received data frame in the receiving buffer and save it.

[0049] Furthermore, step 103, before that, also includes:

[0050] By simulating the FPGA on the receiving side, a DMA operation is initiated to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0051] The simulated receiving side is configured with a real-time process for detecting the received data, that is, receiving data frames. The simulated receiving side also actively initiates a DMA operation after receiving the control instruction through the FPGA to read the received data frame in the receiving buffer through the pice8x interface to the corresponding FPGA, and then judges and analyzes the tail frame sequence number of the received data frame. If the tail frame sequence number increases, the received data frame in the receiving buffer is extracted. The extracted received data frame can be saved or copied to the specified area. The specific subsequent processing is not limited here. It can be understood that as long as the data in the receiving buffer is not written, the tail frame sequence number will not increase. If the tail frame sequence number is detected to increase, it means that a new frame of data has been received.

[0052] In addition, during this process, the simulated receiving side can also set a CPU core for data sending and receiving operations to realize data production and consumption, so that the data sending and receiving operations are not occupied by other computing tasks, thereby improving the real-time performance of data sending and receiving. Moreover, disabling the hyperthreading function on the simulated receiving side can also improve the real-time performance of data sending and receiving and reduce the time jitter caused by the switching of hyperthreading.

[0053] For easier understanding, see Figure 3, an application example of a real-time simulation data transmission system, wherein the real-time simulation node on the left is the simulation sending side, and the real-time simulation node on the right is the simulation receiving side; if the real-time simulation node on the left needs to send a new frame of data, the tail frame sequence number of the frame data is increased by 1, and then a control command is sent to the left FPGA, and the control command contains the data packet size and the memory address where the data is located. After receiving the control command, the left FPGA initiates a DMA operation to quickly read the data frame of the real-time simulation node into the FPGA through the pcie8x interface. While receiving the data frame of the real-time simulation node, the left FPGA transmits the received data frame to the right FPGA through multiple optical fiber communications using the aurora protocol. After receiving the frame data, the right FPGA actively initiates a DMA operation to send the frame data to the right real-time simulation node through the pcie x8 interface. The right real-time simulation node can detect the tail frame sequence number of the received data frame to determine whether a new data frame is received. There is a real-time process in the right real-time simulation node for detecting a newly received frame of data.

[0054] The real-time simulation data transmission method provided by the embodiment of the present application can determine in real time whether there is a data frame to be sent on the simulation sending side, put the sequence number at the end of the frame, and increase the sequence number of the end of the frame of the data frame to be sent by 1 before sending the data. The simulation receiving side can directly detect new data by polling whether the sequence number at the end of the frame has increased without interrupting the operation, thereby reducing the time jitter caused by interrupting the switching of the CPU process and improving the real-time performance of data transmission. Therefore, the embodiment of the present application can solve the technical problem that the existing data transmission and reception does not consider the real-time performance at the microsecond level, the time jitter is large, and it is difficult to meet the higher transmission requirements of the existing data.

[0055] For easier understanding, see Figure 2 The present application provides an embodiment of a real-time simulation data transmission device, comprising:

[0056] The tail frame processing unit 201 is used to determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1;

[0057] The data sending unit 202 is used to send the data frame to be sent to the simulated receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulated sending side to obtain a received data frame;

[0058] The receiving judgment unit 203 is used to judge whether the frame tail sequence number of the received data frame increases by simulating the FPGA of the receiving side. If so, the received data frame is extracted and stored in the receiving buffer.

[0059] Furthermore, it also includes:

[0060] The buffer configuration unit 204 is used to allocate a fixed-size buffer to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

[0061] Further, the data sending unit 202 is specifically configured to:

[0062] By simulating the FPGA on the sending side, a DMA operation is initiated to read the data frames to be sent in the sending buffer into the FPGA through the pice8x interface;

[0063] The optical fiber communication technology of the multi-channel aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain the received data frame.

[0064] Furthermore, it also includes:

[0065] The data reading unit 205 is used to initiate a DMA operation by simulating the FPGA on the receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

[0066] The present application also provides a real-time simulation data transmission device, the device comprising a processor and a memory;

[0067] The memory is used to store the program code and transmit the program code to the processor;

[0068] The processor is used to execute the real-time simulation data transmission method in the above method embodiment according to the instructions in the program code.

[0069] The present application also provides a computer-readable storage medium, which is used to store program codes, and the program codes are used to execute the real-time simulation data transmission method in the above method embodiment.

[0070] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0071] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0072] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0073] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for executing all or part of the steps of the method described in each embodiment of the present application through a computer device (which can be a personal computer, a server, or a network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (full name in English: Read-Only Memory, English abbreviation: ROM), random access memory (full name in English: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program codes.

[0074] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A real-time simulation data transmission method, characterized in that: include: Determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1; The FPGA of the simulated sending side sends the data frame to be sent to the simulated receiving side based on DMA operation and optical fiber communication technology to obtain a received data frame. The specific process is as follows: Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface; The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame; The FPGA on the simulated receiving side determines whether the frame tail sequence number of the received data frame increases. If so, the received data frame is extracted and saved in the receiving buffer.

2. The real-time simulation data transmission method according to claim 1, characterized in that: The step of determining whether there is a data frame to be sent on the simulated sending side, and if so, increasing the frame tail sequence number of the data frame to be sent in the sending buffer by 1, further includes: A fixed-size buffer is allocated to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

3. The real-time simulation data transmission method according to claim 1, characterized in that: The FPGA of the simulated receiving side is used to determine whether the frame tail sequence number of the received data frame is increased, and if so, the received data frame is extracted and saved in the receiving buffer, and the above also includes: The FPGA at the simulated receiving side initiates a DMA operation to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

4. A real-time simulation data transmission device, characterized in that: include: The tail frame processing unit is used to determine whether there is a data frame to be sent on the simulated sending side, and if so, increase the frame tail sequence number of the data frame to be sent in the sending buffer by 1; A data sending unit is used to send the data frame to be sent to the simulation receiving side based on DMA operation and optical fiber communication technology through the FPGA of the simulation sending side to obtain a received data frame. The data sending unit is specifically used to: Initiate a DMA operation through the FPGA of the simulated sending side to read the data frame to be sent in the sending buffer into the FPGA through the pice8x interface; The optical fiber communication technology of the multi-channel Aurora protocol is used to send the data frame to be sent in the FPGA to the simulation receiving side to obtain a received data frame; The receiving judgment unit is used to judge whether the frame tail sequence number of the received data frame is increased through the FPGA of the simulated receiving side, and if so, extract the received data frame in the receiving buffer and save it.

5. The real-time simulation data transmission device according to claim 4, characterized in that: Also includes: The buffer configuration unit is used to allocate a fixed-size buffer to the simulated sending side and the simulated receiving side to obtain a sending buffer and a receiving buffer.

6. The real-time simulation data transmission device according to claim 4, characterized in that: Also includes: The data reading unit is used to initiate a DMA operation through the FPGA of the simulated receiving side to read the received data frame in the receiving buffer into the FPGA through the pice8x interface.

7. A real-time simulation data transmission device, characterized in that: The device comprises a processor and a memory; The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the real-time simulation data transmission method according to any one of claims 1 to 3 according to the instructions in the program code.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store program codes, and the program codes are used to execute the real-time simulation data transmission method according to any one of claims 1 to 3.

Citation Information

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