A high power density integrated circuit module packaging method and its packaging structure

Abstract

A high power density integrated circuit module packaging method and its packaging structure belong to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic packaging shell, the chip assembly area is provided with a heat sink area and a functional area, the heat sink area and the functional area are provided as flat bottom pits, the power of the chips in the circuit is graded, a two-stage or more stepped structure is adopted, the chips are distributed from deep flat bottom pits to shallow flat bottom pits according to the power from large to small, the heat sink area is lower than the functional area, the power type chip with large power is assembled in the heat sink area, and the functional type chip with small power is assembled in the functional area. A metal through hole penetrating through the ceramic base body is arranged below the heat sink area or the functional area to realize shortest path heat dissipation and shortest path internal and external electrical connection. The problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of the existing high-power devices (assemblies or modules) are solved. It is widely used in the field of high-reliability power integrated circuit module integration technology.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device packaging technology, and more specifically to the field of power hybrid integrated circuit ceramic packaging technology. In particular, it relates to a high power density integrated circuit module packaging method and its packaging structure. Background Technology

[0002] Integrated packaging is the science and technology of establishing interconnections and suitable operating environments for electronic circuits. It serves as a bridge between chips, devices, components, and products. In the integrated circuit packaging industry, each generation of chips requires a new generation of packaging. As the feature size of integrated circuits shrinks and operating speeds increase, the industry is placing new and higher demands on integrated circuit packaging technology. Driven by the needs of precision-guided weapons, aerospace, automotive industries, and consumer electronics, traditional packaging processes are facing challenges. The semiconductor industry is rapidly developing towards high integration and small size. System-in-Package (SIP), with its advantages of large-scale, multi-chip, and 3D packaging, is receiving increasing attention. To meet these higher requirements, advanced packaging technologies such as SIP are increasingly being applied in navigation and guidance control. Using SIP for high-power device (component or module) packaging offers advantages such as high power density, high reliability, and high conversion efficiency. However, the heat dissipation design of high-power devices (components or modules) is a major problem limiting the power density and integration design of high-power devices. Heat dissipation measures are complex and bulky, making it difficult to improve product integration. High parasitic impedance and inductance also lead to high application costs and low reliability. Therefore, it is of great significance to realize the high power, integration and miniaturization of high power devices (components or modules) and hybrid integrated circuits, and to design a miniaturized and highly integrated ceramic part.

[0003] In view of this, the present invention is hereby proposed. Summary of the Invention

[0004] The technical problem to be solved by this invention is to address the issues of low power density, low integration, high parasitic impedance and inductance, low reliability, and high application cost of current high-power devices (components or modules).

[0005] The inventive concept of this invention is as follows: In the inner cavity assembly area of ​​the ceramic package shell, a heat sink area and a functional area are set up. The heat sink area and functional area are flat-bottomed recesses, graded according to the power of the chips in the circuit, using a stepped structure of two or more levels. The chips are distributed from high to low power, from deep to shallow flat-bottomed recesses. The heat sink area is lower than the functional area. High-power chips are assembled in the heat sink area, and low-power functional chips are assembled in the functional area. Metal vias penetrating the ceramic base body are provided below the heat sink area or functional area to achieve shortest path heat dissipation and shortest path internal and external electrical connections. High-conductivity and high-thermal-conductivity metal via materials are used in local areas of the package structure (critical parasitic parameter areas), penetrating the ceramic base body to achieve through-connection, greatly improving the heat dissipation efficiency of the product to the equipment base, reducing the product's parasitic impedance and inductive reactance, thereby improving product reliability. This enables high-power, integrated, and miniaturized power hybrid integrated circuit devices, meeting the high reliability, high integration, and technical requirements of this package form factor in research and production of power hybrid integrated circuit devices.

[0006] Therefore, the present invention provides a high power density hybrid integrated circuit module packaging method, such as... Figure 1-6 As shown. The encapsulation method is as follows:

[0007] (1) According to the circuit requirements of the hybrid integrated circuit module, a flat-bottomed recessed heat sink area 2 and a functional area 3 are set in the inner cavity assembly area of ​​the ceramic base body 1. The heat sink area 2 and the functional area 3 adopt a stepped structure of two levels or more, with the heat sink area 2 being lower than the functional area 3. The ceramic base body 1 is a multi-layered ceramic co-fired body. Each ceramic layer has metal through holes and interconnecting lines. The layers are electrically connected to each other through the metal through holes and interconnecting lines according to the set circuit.

[0008] (2) A corresponding heat sink chip welding metal layer 4 is made in the heat sink area 2, and a corresponding functional area chip welding metal layer 5 is made in the functional area 3, which is used to sinter the ceramic base with the chip after the metallization layer is plated.

[0009] (3) The heat sink area 2 and the functional area 3 are isolated by ceramic. According to the power of the chip in the circuit, the chip welding area is set as a flat-bottomed pit structure of different depths. The inner lead bonding area and the conductive strip 11 are plated with a metallization layer, which is set according to the chip welding area.

[0010] (4) The sealing ring 7 is an iron-nickel-cobalt alloy sealing ring. The sealing ring is located on the top of the annular frame 7 of the ceramic base body 1. The cover plate 10 is located on the sealing ring 7 and is sealed to the sealing ring.

[0011] (5) The bottom surface of the ceramic base body 1 is a bottom surface electrode 9 with a metallized layer, and the bottom surface electrode 9 is connected to the corresponding electrode of the chip welding metal layer in the inner cavity assembly area.

[0012] The packaging structure of the high power density hybrid integrated circuit module packaging method is as follows: Figure 1-6 As shown. Includes: ceramic base body 1, annular frame 101, ceramic isolation wall 102, heat sink area 2, functional area 3, heat sink area chip bonding metal layer 4, functional area chip bonding metal layer 5, package internal cavity 6, sealing ring 7, through metal via 8, bottom surface electrode 9, cover plate 10, inner lead bonding area and conductive strip 11.

[0013] The sealing ring 1 is located at the top of the annular frame 101 of the ceramic base body 1.

[0014] The ceramic base body 1 is a multi-layered ceramic co-fired body. Each ceramic layer has metal through holes and interconnecting lines. The layers are electrically connected to each other through the metal through holes and interconnecting lines according to the set circuit.

[0015] The ceramic base body 1 has one or more bottom surface electrodes 9 on its bottom surface, and the bottom surface electrodes 9 are connected to the corresponding electrode terminals of the internal cavity 6 of the package.

[0016] The ceramic base body 1 includes a raised annular frame 101 and an assembly area below the bottom of the annular frame. The assembly area includes a through-hole metal hole 8, a heat sink chip bonding metal layer 4, a functional area chip bonding metal layer 5, an inner lead bonding area, and a conductive strip 11.

[0017] The chip soldering metal layer 4 in the heat sink area and the chip soldering metal layer 5 in the functional area are separated by a ceramic isolation wall 102. According to the circuit performance requirements, each chip soldering metal layer is made in a flat-bottomed recessed area with a set depth.

[0018] The through-hole 8 is located directly below the chip bonding metal layer, vertically penetrating the ceramic base body 1. The inner surface of the through-hole 8 is connected to the back of the chip, and the outer surface of the through-hole 8 is connected to the corresponding bottom surface electrode 9.

[0019] The corresponding devices within the assembly area are connected to the inner lead bonding area 11 via bonding wires.

[0020] The cover plate 10 is located on top of the sealing ring 7 and is sealed to the sealing ring 7.

[0021] In summary, this invention features excellent insulation performance, ultra-small size, ultra-high integration, ultra-light weight, rapid heat dissipation, high reliability, and broad product coverage. It employs both overall and partial metal plating processes to address heat conduction, high current conduction, and bonding issues, thereby improving the high power density and reliability of the package. It can be widely used in various products with high reliability requirements, such as semiconductor devices, semiconductor power devices, and hybrid integrated circuits. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the longitudinal structure of the packaging structure.

[0023] Figure 2 This is a schematic diagram of the internal planar structure of the encapsulation structure.

[0024] Figure 3 This is a schematic diagram of the electrode layout on the bottom surface of the package structure.

[0025] Figure 4 This is a schematic diagram of the cross-sectional structure of the packaging.

[0026] Figure 5 This is a schematic diagram of the longitudinal side structure of the packaging structure.

[0027] Figure 6 This is a schematic diagram of the horizontal side structure of the packaging structure.

[0028] In the diagram: 1 is the ceramic base body, 101 is the annular frame, 102 is the ceramic isolation wall, 2 is the heat sink area, 3 is the functional area, 4 is the chip welding metal layer in the heat sink area, 5 is the chip welding metal layer in the functional area, 6 is the internal cavity of the package, 7 is the sealing ring, 8 is the through metal via, 9 is the bottom surface electrode, 10 is the cover plate, and 11 is the inner lead bonding area and conductor strip. Implementation

[0029] like Figure 1-6 As shown, taking a multi-channel high-voltage field-effect transistor module array as an example, the specific implementation of the high power density integrated circuit module packaging method and its packaging structure is as follows:

[0030] The heat sink area 2 and the functional area 3 adopt a two-stage stepped structure, with the heat sink area 2 being lower than the functional area 3.

[0031] The sealing ring 7 and the cover plate 10 are connected by parallel seam welding.

[0032] The heat sink area consists of six regions, the functional area consists of six regions, and the inner lead bonding area consists of twelve regions.

[0033] The bottom surface electrodes 9 are L-shaped and distributed along the outer casing on both sides of the ceramic base body 1, with 9 electrodes in each section. The vertical part is located on the side of the ceramic base body 1, and the horizontal part is located on the bottom surface of the ceramic base body 1.

[0034] (1) such as Figure 2As shown, the inner lead bonding area and conduction band are: A1, C1, A2, C2, A3, C3, A4, C4, A5, C5, A6, C6, respectively; the chip bonding metal layer (inner cavity metallization electrode area) in the heat sink area are: B1, B3, B5, B8, B10, B12, respectively; and the chip bonding metal layer (inner cavity metallization electrode area) in the functional area are: B2, B4, B6, B7, B9, B11, respectively.

[0035] (2) For example Figure 3 As shown, the bottom surface electrode 9 consists of 18 electrodes: A1-1, B1-1 / B2-1, C1-1, A2-1, B3-1 / B4-1, C2-1, A3-1, B5-1 / B6-1, C3-1, A4-1, B7-1 / B8-1, C4-1, A5-1, B9-1 / B10-1, C5-1, A6-1, B11-1 / B12-1, and C6-1.

[0036] The connection relationships between the bottom surface electrode and the inner cavity metallized electrode area are as follows: A1 and A1-1, B1 / B2 and B1-1 / B2-1, C1 and C1-1, A2 and A2-1, B3 / B4 and B3-1 / B4-1, C2 and C2-1, A3 and A3-1, B5 / B6 and B5-1 / B6-1, C3 and C3-1, A4 and A4-1, B7 / B8 and B7-1 / B8-1, C4 and C4-1, A5 and A5-1, B9 / B10 and B9-1 / B10-1, C5 and C5-1, A6 and A6-1, B11 / B12 and B11-1 / B12-1, C6 and C6-1.

[0037] (3) The metallization layer (external lead electrode, lead bonding area, chip welding area) is composed of multiple layers of metal materials. The surface material is pure gold, the second layer material is nickel, nickel cobalt or nickel phosphorus, and the third layer material is tungsten or molybdenum manganese. The surface and second layers are plated by electroplating. The third layer is made by printing metal paste onto ceramic and then curing it.

[0038] (4) The thickness range of each metal layer in the metallization layer of the external lead electrode, the lead bonding area, and the chip welding area is as follows: the thickness of the surface material gold is 1.3 to 5.7 μm and the purity is ≥99.9%; the thickness of the second layer material nickel, nickel cobalt or nickel phosphorus is 1.3 to 8.9 μm; and the thickness of the third layer material tungsten or molybdenum manganese is 5 to 30 μm.

[0039] (5) such as Figure 1 As shown, the key materials for each part of the encapsulation shell are: the sealing ring 7 is made of 4J42 / 4J29; the ceramic base body 1 is made of 95% or more Al2O3 ceramic or AlN ceramic; and the through-hole metal 8 is made of tungsten paste.

[0040] (6) The outer shell sealing ring and the cover plate are connected by parallel seam welding.

[0041] (1) Cleaning of the outer shell (base, cover)

[0042] First, the outer shell is wet-cleaned and then baked using vacuum or nitrogen: First, the outer shell is soaked in acetone for 10 minutes, then ultrasonically cleaned for 3 minutes, rinsed with regular water for 5 minutes, rinsed with deionized water for 10 minutes, dehydrated with alcohol, and then baked in a nitrogen oven at 60°C.

[0043] Next, the outer casing is cleaned with argon plasma: the argon plasma cleaning is performed with a power setting of 100W, an argon flow rate of ≤50SCCM, and a cleaning time of 180s. Each cleaning should be completed within 24 hours.

[0044] (2) Wet cleaning of the packaging mold and baking with vacuum or nitrogen: the method is the same as step (1).

[0045] (3) Prepare the power MOS chip, subsystem control chip and peripheral auxiliary control chip to be packaged, passive devices, and select welding materials (high temperature solder pads). Before use, the solder pads need to be plasma cleaned (the method is the same as step (1)).

[0046] (4) Assemble the chip: First, install the solder pads in each soldering area, then place the chip on the solder pads in each soldering area according to the set position requirements, then place the quartz press block on the chip, and finally place the assembled mold in a vacuum sintering furnace for high-temperature sintering.

[0047] (5) Place the module from step (4) into a vacuum sintering furnace: Under nitrogen conditions, heat to the preset temperature T1 at a set heating rate V1, hold for t1 time, then evacuate, and after evacuation for t2 time, refill with nitrogen; heat to the preset temperature T2 at a set heating rate V2, hold for t3 time, then evacuate again, and after evacuation for t4 time, refill with nitrogen; heat to the preset temperature T3 (maximum temperature) at a set heating rate V3, hold for t5 time, then begin cooling, set the cooling rate V4, and when the temperature drops below the melting point, begin filling with nitrogen. Finally, allow the furnace to cool naturally to complete the sintering of the device. The heating rates are: V1 > V2 > V3 > V4.

[0048] (6) After sintering, the bonding points on the chip are wire-bonded to the inner surface electrodes using bonding wires according to the circuit connection requirements to obtain a module with interconnected electrical properties.

[0049] (7) Place the module with electrical interconnection in step (6) into a parallel seam welding device, install a cover plate on the outer shell, and perform sealing welding between the outer shell sealing ring and the cover plate to realize the module packaging of the high power density integrated circuit module.

[0050] All the chips are silicon-based chips, and the back metallization layer is an Au layer or an Ag layer.

[0051] The solder material between the chip and the metal layer is AuSn or PbSnAg.

[0052] The eutectic welding temperature range of the AuSn or PbSnAg solder sheet is 320℃~350℃, the welding time is 30s~150s, and the welding atmosphere is vacuum.

[0053] The cover plate is a metal cover plate (composed of 4J42 or 4J29).

[0054] After the outer shell and cover plate are sealed airtightly by parallel seam welding, the internal moisture content is ≤5000ppm and the leakage rate is ≤1×10⁻⁶. -1 Pa·cm 3 / s.

[0055] The bonding wire is a silicon-aluminum wire with a diameter ≥380μm.

[0056] Finally, it should be noted that the above embodiments are merely examples for clear illustration. This invention includes, but is not limited to, the above embodiments, and it is neither necessary nor possible to exhaustively describe all possible implementations. Those skilled in the art can make other variations or modifications based on the above description. All implementation schemes that meet the requirements of this invention are within the protection scope of this invention.

Claims

1. A method for packaging a high power density integrated circuit module, characterized in that: In the inner cavity assembly area of ​​the ceramic package shell, the chip assembly area is set up with a heat sink area and a functional area. The heat sink area and the functional area are set up as flat-bottomed pits. According to the power of the chips in the circuit, a stepped structure of 2 levels or more is adopted. The chips are distributed from high to low power, from deep flat-bottomed pits to shallow flat-bottomed pits. The heat sink area is lower than the functional area. High-power power chips are assembled in the heat sink area, and low-power functional chips are assembled in the functional area. A metal through hole penetrating the ceramic base body is set below the heat sink area or the functional area to achieve the shortest path heat dissipation and the shortest path internal and external electrical connection. The encapsulation method is as follows: (1) According to the circuit requirements of the hybrid integrated circuit module, a heat sink area and a functional area with a flat bottom are set in the inner cavity assembly area of ​​the ceramic base body. The heat sink area and the functional area adopt a stepped structure of 2 levels or more, and the heat sink area is lower than the functional area. The ceramic base body is a multi-layer ceramic co-fired body. Each ceramic layer has metal through holes and interconnecting lines. The layers are electrically connected to each other through metal through holes and interconnecting lines according to the set lines. (2) Make a corresponding heat sink chip welding metal layer in the heat sink area and a corresponding functional area chip welding metal layer in the functional area, so that the ceramic base can be metallized and sintered with the chip. (3) The heat sink area and the functional area are isolated by ceramic. According to the power of the chip in the circuit, the chip welding area is set as a flat-bottomed pit structure of different depths. The inner lead bonding area and the conductive strip are plated with metallization layer, which is set according to the chip welding area. (4) The sealing ring is an iron-nickel-cobalt alloy sealing ring. The sealing ring is located at the top of the annular frame of the ceramic base body, and the cover plate is located on the sealing ring and is sealed to the sealing ring. (5) The bottom surface of the ceramic base body is a bottom surface electrode plated with a metallization layer, and the bottom surface electrode is connected to the corresponding electrode of the chip welding metal layer in the inner cavity assembly area.

2. The high power density integrated circuit module packaging method as described in claim 1, characterized in that, The specific implementation method is as follows: (1) Cleaning the outer casing First, the outer shell is wet-cleaned and then baked in vacuum or nitrogen: First, the outer shell is soaked in acetone for 10 minutes, then cleaned with ultrasonic low frequency for 3 minutes, rinsed with regular water for 5 minutes, rinsed with deionized water for 10 minutes, dehydrated with alcohol, and then baked in a nitrogen oven at 60°C. Next, the outer shell is cleaned with argon plasma: the argon plasma cleaning is performed with a power setting of 100W, an argon flow rate of ≤50SCCM, and a cleaning time of 180s. Each cleaning should be completed within 24 hours. (2) Wet cleaning of the packaging mold and baking with vacuum or nitrogen: the method is the same as step (1); (3) Prepare the power MOS chip, subsystem control chip and peripheral auxiliary control chip to be packaged, passive devices, and select high temperature solder pads as the welding material. Before use, the solder pads need to be plasma cleaned, and the method is the same as step (1). (4) Assemble the chip: First, install the solder pads in each soldering area, then place the chip on the solder pads in each soldering area according to the set position requirements, then place the quartz pressure block on the chip, and finally place the assembled mold in a vacuum sintering furnace for high-temperature sintering. (5) Place the module from step (4) into a vacuum sintering furnace: under nitrogen conditions, heat to the preset temperature T1 at the set heating rate V1, hold for t1 time, then evacuate, evacuate for t2 time, and then refill with nitrogen; heat to the preset temperature T2 at the set heating rate V2, hold for t3 time, then evacuate again, evacuate for t4 time, and then refill with nitrogen; heat to the preset maximum temperature T3 at the set heating rate V3, hold for t5 time, then begin cooling, set the cooling rate V4, and when the temperature drops below the melting point, begin filling with nitrogen, and finally cool naturally with the furnace to complete the sintering of the device; the relationship between the heating rates is: V1 > V2 > V3 > V4; (6) After sintering, the bonding points on the chip are wire-bonded to the inner surface electrodes using bonding wires according to the circuit connection requirements to obtain a module with interconnected electrical properties. (7) Place the module with electrical interconnection in step (6) into a parallel seam welding equipment, install a cover plate on the outer shell, and perform sealing welding between the outer shell sealing ring and the cover plate to realize the module packaging of the high power density integrated circuit module; The solder material between the chip and the metal layer is AuSn or PbSnAg; The eutectic welding temperature range of the AuSn or PbSnAg solder sheet is 320℃~350℃, the welding time is 30s~150s, and the welding atmosphere is vacuum. After the outer shell and cover plate are sealed airtightly by parallel seam welding, the internal moisture content is ≤5000ppm and the leakage rate is ≤1×10⁻⁶. -1 Pa·cm 3 / s.

3. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: include: Ceramic base body, ring frame, ceramic isolation wall, heat sink area, functional area, chip welding metal layer in heat sink area, chip welding metal layer in functional area, internal cavity of package, sealing ring, through metal via, bottom surface electrode, cover plate, inner lead bonding area and conductive strip. The sealing ring is located at the top of the annular border of the ceramic base body; The ceramic base body is a multi-layered ceramic co-fired body. Each ceramic layer has metal through holes and interconnecting lines. The layers are electrically connected to each other through the metal through holes and interconnecting lines according to the set circuit. The ceramic base body has one or more bottom surface electrodes, and the bottom surface electrodes are connected to the corresponding electrode terminals of the internal cavity of the package. The ceramic base body includes a raised annular frame and an assembly area below the bottom of the annular frame. The assembly area includes a through-hole metal via, a heat sink chip bonding metal layer, a functional area chip bonding metal layer, an inner lead bonding area, and a conductive strip. The chip soldering metal layer in the heat sink area and the chip soldering metal layer in the functional area are separated by a ceramic isolation wall. According to the circuit performance requirements, each chip soldering metal layer is made in a flat-bottomed recessed area of ​​different depths. The through-hole is located directly below the chip bonding metal layer, vertically penetrating the ceramic base body. The inner surface of the through-hole is connected to the back of the chip, and the outer surface of the through-hole is connected to the corresponding bottom surface electrode. Within the assembly area, the corresponding devices are connected to the inner lead bonding area via bonding wires; The cover plate is located above the sealing ring and is sealed to the sealing ring.

4. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The heat sink area and functional area adopt a two-stage stepped structure, with the heat sink area being lower than the functional area.

5. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The sealing ring and the cover plate are connected by parallel seam welding for sealing.

6. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The inner lead bonding areas and conduction bands are: A1, C1, A2, C2, A3, C3, A4, C4, A5, C5, A6, and C6, respectively; the chip bonding metal layers in the heat sink area are: B1, B3, B5, B8, B10, and B12, respectively; the chip bonding metal layers in the functional area are: B2, B4, B6, B7, B9, and B11, respectively; and the bottom surface electrodes are: A1-1, B1-1 / B2-1, C1-1, A2-1, B3-1 / B4-1, C2-1, A3-1, B5-1 / B6-1, C3-1, A4-1, B7-1 / B8-1, C4-1, A5-1, B9-1 / B10-1, C5-1, A6-1, B11-1 / B12-1, and C6-1, respectively. The connection relationships between the bottom surface electrode and the chip welding metal layer are as follows: A1 and A1-1, B1 / B2 and B1-1 / B2-1, C1 and C1-1, A2 and A2-1, B3 / B4 and B3-1 / B4-1, C2 and C2-1, A3 and A3-1, B5 / B6 and B5-1 / B6-1, C3 and C3-1, A4 and A4-1, B7 / B8 and B7-1 / B8-1, C4 and C4-1, A5 and A5-1, B9 / B10 and B9-1 / B10-1, C5 and C5-1, A6 and A6-1, B11 / B12 and B11-1 / B12-1, C6 and C6-1.

7. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The bottom surface electrodes are L-shaped and distributed along the outer casing on both sides of the ceramic base body, with nine electrodes on each side. The vertical portions are located on the side of the ceramic base body, and the horizontal portions are located on the bottom surface of the ceramic base body.

8. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The metal layer is composed of multiple layers of metal materials. The surface material is a gold layer, the second layer is a nickel layer, a nickel-cobalt layer, or a nickel-phosphorus layer, and the third layer is a tungsten layer or a molybdenum-manganese layer. The surface and second layers are plated by electroplating, and the third layer is made by printing a metal paste onto the ceramic and then curing it.

9. The packaging structure of the high power density integrated circuit module packaging method as described in claim 1, characterized in that: The thickness range of each metal layer in the metal layer is as follows: the thickness of the surface layer is 1.3 to 5.7 μm, the thickness of the second layer is 1.3 to 8.9 μm, and the thickness of the third layer is 5 to 30 μm; the material of the sealing ring is 4J42 / 4J29; the material of the ceramic base body is more than 95% Al2O3 ceramic or AlN ceramic; the material of the through-hole metal is tungsten paste.

Images