Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a substrate; a wiring layer located on a first surface of the substrate, including a first alignment mark and a conductive trace, the first alignment mark having a first coordinate position and a first preset relative position relative to the conductive trace; a first through hole penetrating the substrate to expose the first alignment mark; a second alignment mark located on a second surface of the substrate opposite to the first surface, having a second preset relative position relative to the first alignment mark, which can be used as a position reference when forming a second through hole penetrating the substrate, so that the orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace. The semiconductor device provided by the present disclosure has the advantages of high alignment accuracy, low manufacturing cost, high yield, etc., which is conducive to improving the electrical signal transmission performance and chip integration density, and reducing power consumption and transmission distance.

Description

Technical Field

[0001] The present disclosure relates to semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, in order to further reduce the size of integrated circuits, multi-layer integrated circuit chips are stacked, and through silicon via (TSV) technology is used to achieve vertical electrical interconnection between multi-layer chips, thereby realizing three-dimensional integration of chips. Three-dimensional integration technology can reduce chip power consumption, reduce interconnection delay, increase data transmission bandwidth, and make it possible to realize system-on-chip (SoC) with complex functions.

[0003] TSV process can be divided into via-first process, via-middle process and via-last process according to the different manufacturing time of device structure. The via-last process refers to making the via-last on the substrate after the wiring layer is formed. The via-last technology provides more possibilities for three-dimensional vertical interconnection with its advantages of being suitable for chips such as backside illumination (BSI).

[0004] In the via-last process, it is difficult to align the TSV formed later on the back side of the substrate with the conductive wiring formed earlier on the front side of the substrate. Summary of the invention

[0005] In order to solve the above problems, the embodiments of the present disclosure provide the following technical solutions.

[0006] According to one aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a wiring layer, the wiring layer being located on a first surface of the substrate, the wiring layer comprising a first alignment mark and a conductive trace, the first alignment mark having a first coordinate position and a first preset relative position relative to the conductive trace; a first through hole, the first through hole penetrating the substrate to expose the first alignment mark, the orthographic projection of the first through hole on the wiring layer covering the first alignment mark; and a second alignment mark, the second alignment mark being located on a second surface of the substrate opposite to the first surface, the second alignment mark having a second preset relative position relative to the first alignment mark, the second alignment mark being capable of being used as a position reference when forming a second through hole penetrating the substrate, so that the orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace.

[0007] In some embodiments, the device further includes the second through hole, wherein the second through hole is a rear through hole, and the position of the second through hole relative to the second alignment mark is determined according to the first coordinate position, the first preset relative position and the second preset relative position.

[0008] In some embodiments, a metal connector is filled in the second through hole, and one end of the metal connector is connected to the conductive trace.

[0009] In some embodiments, a buffer layer is provided between the substrate and the wiring layer, an end of the first through hole adjacent to the first alignment mark extends to the buffer layer, and an end of the second through hole adjacent to the conductive trace extends through the buffer layer to the wiring layer.

[0010] In some embodiments, the device further comprises: a carrier bonded to a surface of the wiring layer away from the substrate.

[0011] In some embodiments, the second alignment mark is an alignment mark that can be automatically recognized by a photolithography machine.

[0012] In some embodiments, the first alignment mark includes at least two alignment marks located at different positions of the wiring layer.

[0013] In some embodiments, the wiring layer includes a graphic area and a scribe line area, the conductive trace is located in the graphic area, and the orthographic projection of the second alignment mark on the wiring layer is located in the scribe line area of ​​the wiring layer.

[0014] In some embodiments, the first alignment mark includes at least two alignment marks located at different positions of the wiring layer.

[0015] According to one aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate; a wiring layer, the wiring layer being located on a first surface of the substrate, the wiring layer comprising a first alignment mark and a conductive trace; a first through hole and a second through hole penetrating the substrate, the orthographic projection of the first through hole on the wiring layer covering the first alignment mark, and the orthographic projection of the second through hole on the wiring layer at least partially overlapping with the conductive trace.

[0016] In some embodiments, the second through hole is formed using the first alignment mark as a position reference.

[0017] In some embodiments, the first alignment mark has a first coordinate position and a first preset relative position relative to the conductive trace, and the position of the second through hole is determined according to the first coordinate position and the first preset relative position.

[0018] In some embodiments, the first alignment mark has a first coordinate position, and the position of the first through hole is determined according to the first coordinate position.

[0019] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a wiring layer on a first surface of a substrate, the wiring layer comprising a first alignment mark and a conductive trace, the first alignment mark having a first coordinate position and a first preset relative position relative to the conductive trace; forming a first through hole penetrating the substrate from a second surface of the substrate opposite to the first surface, the orthographic projection of the first through hole on the wiring layer covering the first alignment mark; and forming a second alignment mark on the second surface of the substrate, the second alignment mark having a second preset relative position relative to the first alignment mark, the second alignment mark being capable of being used as a position reference when forming a second through hole penetrating the substrate, so that the orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace.

[0020] In some embodiments, the method further includes: forming the second through hole penetrating from the second surface of the substrate using the second alignment mark as a position reference.

[0021] In some embodiments, forming a second through hole penetrating the substrate from the second surface of the substrate using the second alignment mark as a position reference includes: determining the position of the second through hole relative to the first surface of the substrate based on the first coordinate position, the first preset relative position and the second preset relative position; preparing a second light shield according to the position of the second through hole relative to the first surface of the substrate, the second light shield including a through hole pattern and a fourth alignment mark for forming the second through hole; aligning the second light shield with the area to be exposed on the second surface of the substrate through the fourth alignment mark and the second alignment mark; and transferring the through hole pattern to the area to be exposed on the second surface by photolithography, and etching to form the second through hole.

[0022] In some embodiments, forming the first through hole penetrating the substrate includes: determining a first etching position on the second surface of the substrate according to the first coordinate position; and etching at the first etching position until penetrating the substrate to form the first through hole.

[0023] In some embodiments, forming the second alignment mark on the second surface of the substrate includes: preparing a first light shield, on which a third alignment mark corresponding to the first alignment mark and a mark pattern for forming the second alignment mark are provided, and the position of the mark pattern relative to the third alignment mark defines the second preset relative position; and while keeping the third alignment mark of the first light shield aligned with the first alignment mark, transferring the mark pattern to the second surface of the substrate to form the second alignment mark.

[0024] In some embodiments, the position of the mark pattern on the first light shield relative to the third alignment mark is determined based on the position of the conductive trace relative to the first alignment mark.

[0025] In some embodiments, the method further comprises: before forming the first through hole, bonding a carrier to a surface of the wiring layer away from the substrate, and thinning the substrate from a second surface of the substrate.

[0026] In the disclosed embodiment, the relative position relationship between the second alignment mark and the conductive trace on the first surface of the substrate is determined by the first preset relative position of the first alignment mark on the first surface of the substrate and the second alignment mark on the second surface of the substrate. When the second through hole penetrating the substrate is formed on the second surface of the substrate using the second alignment mark as a position reference, the position of the second through hole formed on the second surface of the substrate can be aligned with the conductive trace on the first surface of the substrate according to the relative position relationship between the second alignment mark and the conductive trace on the first surface, thereby achieving connection. In the above manner, the substrate can be used to determine the position of the second through hole without special treatment, and the alignment accuracy of the second through hole can be improved. In addition, during the manufacturing process, there is no need to use a special transparent carrier for bonding, and there is no need to use a special light source for alignment, which improves the compatibility of semiconductor device manufacturing equipment.

[0027] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a schematic structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 3 is a schematic structural diagram of a semiconductor device according to some other embodiments of the present disclosure;

[0032] Figures 4 to 7 is a schematic structural diagram of a semiconductor device according to some further embodiments of the present disclosure;

[0033] Figure 8 is a schematic diagram of the positions of a semiconductor device and a first light shield according to some embodiments of the present disclosure;

[0034] Fig. 9 is a schematic flow chart of a second through hole forming process according to some embodiments of the present disclosure;

[0035] Fig.10 is a schematic diagram of the positions of the semiconductor device and the second light shield according to some embodiments of the present disclosure;

[0036] Fig.11 is a schematic structural diagram of a semiconductor device according to some other embodiments of the present disclosure;

[0037] Fig.12 is a schematic diagram of a second through-hole forming process according to some embodiments of the present disclosure;

[0038] Fig.13 is a schematic structural diagram of a semiconductor device filled with metal connectors according to some embodiments of the present disclosure;

[0039] Fig.14 is a schematic structural diagram of a semiconductor device according to some other embodiments of the present disclosure.

[0040] Note that throughout the drawings, like reference numerals refer to like elements. DETAILED DESCRIPTION

[0041] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure and its application or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully express the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, the composition of the materials, the numerical expressions and the numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0042] The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The words "include" or "comprises" and similar words mean that the elements before the word include the elements listed after the word, and do not exclude the possibility of including other elements. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0043] In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be an intermediate component between the specific component and the first component or the second component. When a specific component is described as being connected to other components, the specific component may be directly connected to the other components without an intermediate component, or may not be directly connected to the other components but have an intermediate component.

[0044] All terms (including technical terms or scientific terms) used in the present disclosure have the same meanings as those understood by ordinary technicians in the field to which the present disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries, such as general dictionaries, should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined herein.

[0045] As mentioned above, in the via-last process of the TSV technology, it is difficult to align the TSV formed later on the back side of the substrate with the conductive wiring formed previously on the front side of the substrate.

[0046] Some related technologies use a transparent carrier made of special materials in the manufacturing process of semiconductor devices, so that the position of the conductive traces in the wiring layer on the front of the substrate can be observed from the surface where the substrate and the carrier are bonded, so as to determine the TSV position by means of double-sided alignment. In this way, the carrier material is mostly glass, which has poor electrical and thermal conductivity and is easy to affect the yield. In addition, when transporting semiconductor devices, most semiconductor device manufacturing equipment uses electrostatic adsorption transmission, which cannot be used for glass carriers, resulting in difficulty in transporting semiconductor devices and increasing the risk of semiconductor devices breaking.

[0047] Some other related technologies have modified the manufacturing equipment of semiconductor devices, installed a red light source, used infrared rays to read the alignment signal on the substrate, and determined the TSV position according to the alignment signal. This method requires the modification of the manufacturing equipment, which is costly and has low alignment accuracy.

[0048] The semiconductor device proposed in the present disclosure can realize the alignment of TSV formed by the via-last process and the conductive trace. Compared with the existing related technologies, the semiconductor device has at least one of the advantages of high alignment accuracy, low manufacturing cost, and high yield rate. Through the implementation of the via-last process, the interconnection distance can be effectively reduced, the integration density of semiconductor chips can be improved, which is conducive to improving the transmission performance of electrical signals, reducing the interconnection delay, and providing more possibilities for realizing three-dimensional vertical interconnection of active wafers.

[0049] Figure 1 is a schematic structural diagram of a semiconductor device according to some embodiments of the present disclosure.

[0050] In some embodiments, Figure 1 As shown, the semiconductor device 100 includes a substrate 101, a wiring layer 102 and a first through hole 105. The wiring layer 102 is located on the first surface S1 of the substrate 101. In the following, for the convenience of description, the first surface S1 with the wiring layer 102 may sometimes be referred to as the front side, and the two may be used interchangeably; the second surface S2 opposite thereto may be referred to as the back side, and the two may also be used interchangeably. The wiring layer 102 includes a first alignment mark 103 and a conductive trace 104. The first through hole 105 penetrates the substrate 101 to expose the first alignment mark 103. The orthographic projection of the first through hole 105 on the wiring layer 102 covers the first alignment mark 103. The semiconductor device 100 also includes a second alignment mark 106. The second alignment mark 106 is located on the second surface S2 (i.e., the "back side") of the substrate.

[0051] The first alignment mark 103 has a first coordinate position and a first preset relative position relative to the conductive trace 104. The second alignment mark 106 has a second preset relative position relative to the first alignment mark 103. The second alignment mark 106 can be used as a position reference when forming a second through hole 107 penetrating the substrate 101, so that the orthographic projection of the second through hole 107 on the wiring layer 102 at least partially overlaps with the conductive trace 104.

[0052] The first alignment mark 103 and the conductive trace 104 included in the wiring layer 102 can be formed independently of each other. The first alignment mark 103 and the conductive trace 104 can be located in different layers. In other embodiments, the first alignment mark 103 and the conductive trace 104 are formed in the same layer. In the case where the conductive trace 104 includes multiple layers of conductive connecting wires, the first alignment mark 103 can be in the same layer as a certain layer of conductive connecting wires in the conductive trace 104. In a further embodiment, the first alignment mark 103 and the conductive trace 104 (or a certain layer of conductive connecting wires therein) are formed simultaneously. The conductive trace 104 can be formed by electroplating metal (for example, copper). If the first alignment mark 103 and the conductive trace 104 are formed in the same layer at the same time, the first alignment mark 103 can also be formed by electroplating metal. In this way, the same mask can be used to prepare the conductive trace 104 and the first alignment mark 103 at one time, so that there is no need to prepare a separate mask for forming the first alignment mark 103, thereby saving processes and reducing preparation costs.

[0053] like Figure 1 As shown, the position of the second through hole 107 in the semiconductor device 100 is indicated by a dotted line. In some embodiments, the semiconductor device 100 can be further processed as shown in FIG. Figure 1 The second through hole 107 penetrating the substrate 101 is formed at the position of the dotted line shown. That is, since the second alignment mark 106 has the function of serving as a position reference, the semiconductor device 100 can form the second through hole 107 at any time later as needed. Figure 1 In the semiconductor device 100 shown, the dotted line position is only for illustration, and the second through hole 107 may not be actually formed at this time.

[0054] In the above embodiment, the relative position relationship between the second alignment mark 106 and the conductive trace 104 on the first surface of the substrate 101 is determined by the first preset relative position of the first alignment mark 103 located on the first surface S1 of the substrate 101 and the second alignment mark 106 located on the second surface S2 of the substrate 102. When the second through hole 107 penetrating the substrate 101 is formed on the second surface S2 of the substrate 101 with the second alignment mark 106 as the position reference, the position where the second through hole 107 is formed on the second surface S2 of the substrate 101 can be aligned with the conductive trace 104 on the first surface S1 of the substrate 101 according to the relative position relationship between the second alignment mark 106 and the conductive trace 104 on the first surface S1, thereby achieving connection. In the above manner, the substrate 101 can be used to determine the position of the second through hole without special processing, and the alignment accuracy of the second through hole 107 can be improved. In addition, no special light source is required for alignment during the manufacturing process, thereby improving the compatibility of manufacturing equipment of the semiconductor device 100.

[0055] In some embodiments, the material of the substrate may include at least one of the following semiconductor materials: Si (silicon), Ge (germanium), SiC (silicon carbide), SiGe (silicon germanium), and GaAs (gallium arsenide).

[0056] In order to more conveniently understand the technical solution proposed in the present disclosure, a method for manufacturing a semiconductor device will be introduced below.

[0057] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2 As shown, the method 200 for manufacturing a semiconductor device includes steps 201 to 205. In some embodiments, as Figure 1 The semiconductor device 100 shown is manufactured according to a manufacturing method 200 .

[0058] In step 201, a wiring layer is formed on the first surface of the substrate. Figure 3 Take the formation process of the wiring layer as an example to introduce it. Figure 3 FIG. 3 shows a schematic structural diagram of a semiconductor device 300 according to some other embodiments of the present disclosure, wherein a wiring layer 102 is formed on the first surface S1 of the substrate 101. Figure 3 As shown, the wiring layer 102 of the semiconductor device 300 includes a first alignment mark 103 and a conductive trace 104. The first alignment mark 104 has a first coordinate position and a first preset relative position relative to the conductive trace. The first coordinate position of the first alignment mark 104 can be determined with reference to the substrate plane. The first preset relative position of the conductive trace 104 and the first alignment mark 103 can be determined according to the layout design of the device or circuit in the wiring layer 102. When the first coordinate position and the first preset relative position are known, the position of the conductive trace 104 can be known.

[0059] In some embodiments, the first alignment mark 103 includes at least two alignment marks located at different positions of the wiring layer 102. The geometric figures of the two alignment marks can be a cross, a two-dimensional dot array, or any other two-dimensional pattern or a combination thereof. The geometric figures of different alignment marks can be the same or different. The alignment mark can be located at the edge position of the wiring layer, that is, the periphery of the conductive trace located in the central area. The first coordinate position of the first alignment mark 103 includes the coordinate position of each alignment mark. The coordinate position of each alignment mark can be the coordinate (x, y) of its orthographic projection on the substrate plane. When the wiring layer 102 is designed, the first coordinate position of the first alignment mark 103 and the relative position relationship of the first alignment mark relative to the conductive trace 104 to be connected to the second through hole (especially the metal connector therein) can be predetermined.

[0060] In some embodiments, Figure 3 As shown, a buffer layer 109 is first formed at the first surface S1 of the substrate 101, and then a wiring layer 102 is formed on the side of the buffer layer 109 away from the first surface S1 of the substrate 101. In other words, the buffer layer 109 is formed between the wiring layer 102 and the substrate 101. The buffer layer 109 can prevent the second through hole from directly extending to the wiring layer 102 when the second through hole is formed in the semiconductor device, resulting in reduced reliability.

[0061] Below Figure 4 Take the structure of the dielectric layer as an example to introduce. Figure 4 FIG. 4 is a schematic diagram of a semiconductor device 400 according to some other embodiments of the present disclosure. Figure 4 As shown, the wiring layer 102 of the semiconductor device 300 includes a dielectric layer 112 in addition to the first alignment mark 103 and the conductive trace 104. In some embodiments, the dielectric layer 112 includes a multi-layer structure formed of nitride or oxide. Figure 4 As shown, the dielectric layer 112 is composed of a first oxide layer 1121, a first nitride layer 1122, a second oxide layer 1123 and a second nitride layer 1124. These layer structures are formed layer by layer in the order from close to the first surface S1 to far from the first surface S2. The dielectric layer can be transparent, so as long as a first through hole penetrating the substrate is formed and the position of the first through hole can correspond to the position of the first alignment mark 112, the first alignment mark 112 surrounded by the dielectric layer 112 can be exposed from the back of the substrate to serve as a position reference.

[0062] In some embodiments, Figure 4 As shown, the wiring layer 102 further includes a pad (PAD) 114. The pad 114 corresponds to at least a portion of the conductive trace 109. The pad 114 can be formed above at least a portion of the conductive trace 109 (i.e., on a side further away from the first surface S1). In some embodiments, the pad 114 is made of aluminum (Al).

[0063] In some embodiments, when the wiring layer 102 includes a pad 114, the first alignment mark 103 can be formed in the same layer as the pad 114. The first alignment mark 103 can be formed together with the pad 114. The same mask can be used to simultaneously form the pad 114 and the first alignment mark 103. This avoids the need to design different masks for the pad 114 and the first alignment mark 103, respectively, and simplifies the process flow. Furthermore, the material of the first alignment mark 103 can be the same as that of the pad 114, for example, both are aluminum. In this way, the pad 114 and the first alignment mark 103 can be formed at the same time using the same material, saving manufacturing time. Moreover, aluminum is easy to electroplate over a large area, which is conducive to forming an easily identifiable first alignment mark 103.

[0064] In some embodiments, the buffer layer 109 is also a dielectric layer, and its material is the same as that of the dielectric layer 112 , which is also nitride or oxide.

[0065] Back to Figure 2 In some embodiments, the manufacturing method 200 further includes: after forming the first alignment mark, bonding the carrier to a surface of the wiring layer away from the substrate.

[0066] Below Figure 5 Taking as an example, the bonding between the carrier and the wiring layer is introduced. Figure 5 FIG. 5 is a schematic diagram of a semiconductor device 500 according to some other embodiments of the present disclosure. Figure 5 As shown, the carrier 110 is bonded to the surface of the wiring layer 102 away from the substrate 101. The bonding method can be temporary bonding or permanent bonding. In some implementations, the wiring layer 102 is bonded to the carrier 110 by bonding glue 111. The purpose of bonding to the carrier 110 is to protect, fix and support the semiconductor device 500, and reduce the probability of the semiconductor device 500 breaking.

[0067] In some embodiments, the carrier wafer 110 is bonded to the wiring layer 102 during the subsequent processing of the semiconductor device 500. When the semiconductor device 500 needs to be moved or fixed in some process steps, the carrier wafer 110 can be used to achieve this.

[0068] Back to Figure 2 In some embodiments, the manufacturing method 200 further includes: before forming the first through hole, thinning the substrate from the second surface to a preset thickness. Figure 5 Taking the semiconductor device 500 as an example, the substrate 101 can be polished so that the substrate 101 is thinned to a preset thickness. The preset thickness to which the substrate 101 is thinned is determined according to the depth of the second through hole. In some embodiments, the preset thickness is the same as the depth of the second through hole. By thinning the substrate 101, the thickness of the semiconductor device can be reduced, thereby reducing the difficulty of subsequent alignment and formation of through holes and reducing the volume of the semiconductor device.

[0069] In step 203, a first through hole is formed through the substrate from a second surface of the substrate opposite to the first surface to expose a first alignment mark. The orthographic projection of the first through hole on the wiring layer covers the first alignment mark.

[0070] Below Figure 6 The function of forming the first through hole is described as an example. Figure 6 FIG. 6 is a schematic diagram of a semiconductor device 600 according to some other embodiments of the present disclosure. Figure 6As shown, a first through hole 105 penetrating the substrate 101 is formed from the second surface S2 of the substrate 101 opposite to the first surface S1 to expose the first alignment mark 103, and the orthographic projection of the first through hole 105 on the wiring layer 102 covers the first alignment mark 103. In this step, by forming the first through hole 105 on the second surface S2 of the substrate 101, the first alignment mark 103 can also be observed from the direction of the second surface S2, which facilitates the subsequent positioning of the second alignment mark and / or the second through hole on the second surface S2 according to the first coordinate position of the first alignment mark 103.

[0071] In some embodiments, forming the first through hole 105 penetrating the substrate 101 includes: determining a first etching position on the second surface S2 of the substrate 101 according to the first coordinate position; etching at the first etching position until the substrate 101 is penetrated to form the first through hole 105. The first etching position can directly adopt the first coordinate position. The area of ​​the etching region can be larger than the area of ​​the first alignment mark 103, so that after the first through hole 105 is etched, the first alignment mark 103 can be completely exposed.

[0072] Figure 7 is a schematic diagram of the structure of a semiconductor device 700 according to some further embodiments of the present disclosure. Compared with the semiconductor device 600, the semiconductor device 700 is provided with a buffer layer 109 between the substrate 101 and the wiring layer 102. In this case, when the first through hole 105 is formed, one end of the first through hole 105 adjacent to the first surface S1 may extend to the buffer layer 109.

[0073] Back to Figure 2 In step 205, a second alignment mark is formed on the second surface of the substrate. The second alignment mark has a second preset relative position relative to the first alignment mark in step S201. The second alignment mark can be used as a position reference when forming a second through hole through the substrate, so that the orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace in step S201.

[0074] Reference Figure 1The process is described below. A second alignment mark 106 is formed on the second surface S2 of the substrate 101. The second alignment mark 106 has a second preset relative position relative to the first alignment mark 103. The second alignment mark 106 can be used as a position reference when forming a second through hole 107 penetrating the substrate 101, so that the orthographic projection of the second through hole 107 on the wiring layer 102 at least partially overlaps with the conductive trace 104. In this step, the relative position relationship between the second alignment mark 103 and the conductive trace 104 located on the first surface S1 of the substrate 101 is determined by the second preset relative position of the first alignment mark 103 located on the first surface S1 of the substrate 101 and the second alignment mark 106 located on the second surface S2 of the substrate. When the second through hole 107 penetrating the substrate 101 is formed on the second surface S2 of the substrate 101 using the second alignment mark 106 as a position reference, the position where the second through hole 107 is formed on the second surface S2 of the substrate can be aligned with the conductive trace 104 on the first surface S1 of the substrate 101 according to the relative position relationship between the second alignment mark 106 and the conductive trace 104 on the first surface S1, thereby achieving connection.

[0075] In the above manner, the position of the second through hole 107 can be determined without special processing of the substrate 101, and the alignment accuracy of the second through hole 107 can be improved. In addition, this method does not require the use of a special light source for alignment, thereby improving the compatibility of semiconductor device manufacturing equipment.

[0076] In some embodiments, in step 205, forming a second alignment mark on the second surface of the substrate may specifically include the following steps: preparing a first light shielding cover, on which a third alignment mark corresponding to the first alignment mark and a mark pattern for forming the second alignment mark are provided, and the position of the mark pattern relative to the third alignment mark defines the second preset relative position; while keeping the third alignment mark of the first light shield aligned with the first alignment mark, transferring the mark pattern to the second surface of the substrate to form the second alignment mark.

[0077] Figure 8 FIG. 1 is a schematic diagram showing the positions of a semiconductor device and a first light shield according to some embodiments of the present disclosure. Figure 8 An exemplary process of forming the second alignment mark is described below. First, prepare Figure 8The first light shield 11 shown. A third alignment mark 113 corresponding to the first alignment mark 103 is provided on the first light shield 11. The third alignment mark 113 is used to align with the first alignment mark 103. A mark pattern 116 for forming a second alignment mark 106 is also provided on the first light shield 11. The position of the mark pattern 116 relative to the third alignment mark 113 defines the second preset relative position described above. Then, while keeping the third alignment mark 113 of the first light shield 11 aligned with the first alignment mark 103, the mark pattern 116 is transferred to the second surface S2 of the substrate 101 of the semiconductor device 800 to form the second alignment mark 106. The second alignment mark 106 is formed using the first light shield 11, and the first light shield 11 is aligned with the first alignment mark 103 using the third alignment mark 113 to achieve the transfer of the second alignment mark 106. The above steps form the second alignment mark 106 on the second surface S2 of the substrate 101 , which is beneficial for further determining the position of the second through hole 107 on the second surface S2 according to the second alignment mark 106 .

[0078] In some embodiments, the position of the mark pattern on the first light shield relative to the third alignment mark is determined based on the position of the conductive trace relative to the first alignment mark. Figure 8 As shown, the position of the mark pattern 116 on the first light shield 11 relative to the third alignment mark 113 can be determined based on the relative position of the conductive trace 104 and the first alignment mark 103. In this way, if the relative position of the first alignment mark 103 and the conductive trace 104 is known, and the relative position of the third alignment mark 113 and the mark pattern 116 is known, the relative position of the conductive trace 104 relative to the second alignment mark 106 formed according to the mark image 116 can be determined.

[0079] In some embodiments, the wiring layer includes a graphic area and a cutting path area, the conductive trace is located in the graphic area, and the orthographic projection of the second alignment mark on the wiring layer is located in the cutting path area of ​​the wiring layer. The graphic area is an area for forming electronic devices. The cutting path area is an area for cutting the substrate and the wiring layer into individual chips. The second alignment mark is located in the cutting path area to avoid occupying the area of ​​the graphic area used to form electronic devices. Moreover, in the subsequent process of forming a semiconductor device from the semiconductor device, the semiconductor device will be cut, and the second alignment mark no longer plays a role in marking the relative position in the subsequent process, and can be at least partially removed during the cutting process.

[0080] In some embodiments, the manufacturing method 200 further includes forming a second through hole penetrating from the second surface of the substrate using the second alignment mark as a position reference. The second through hole formed at this time can be well aligned with the conductive trace to achieve connectivity between the two opposite surfaces of the substrate, thereby facilitating the improvement of the vertical integration of the semiconductor device.

[0081] In some embodiments, the aspect ratio of the second through hole may be 20:1, 15:1, 10:1, 5:1, etc., but is not limited to this range.

[0082] Fig. 9 A schematic flow chart of a method 900 for forming a second through hole according to a second alignment mark according to some embodiments of the present disclosure is shown. Fig.10 FIG. 2 shows a schematic diagram of the positions of the semiconductor device 1000 and the second light shield 22 in some embodiments of the present disclosure. Fig.10 The steps of method 900 are described as follows. Figure 2 A part of the manufacturing method 200 is performed after step 205, for realizing forming a second through hole penetrating the substrate from the second surface of the substrate using the second alignment mark as a position reference benchmark.

[0083] In step 902, the position of the second through hole 107 relative to the second alignment mark 106 is determined based on the first coordinate position of the first alignment mark 103 in the wiring layer 102, the first preset relative position of the first alignment mark 103 relative to the conductive trace 104, and the second preset relative position of the second alignment mark 106 relative to the first alignment mark 103.

[0084] In step 904, a second through hole 107 is prepared according to the position of the second alignment mark 106. Fig.10 The second light shielding mask 22 is shown. The second light shielding mask 22 includes a through hole pattern 117 forming the second through hole 107. The second light shielding mask 22 also includes a fourth alignment mark (not shown) for positioning the light shield.

[0085] In some embodiments, the second alignment mark 106 is an alignment mark that can be automatically recognized by the lithography machine. The second alignment mark 106 may have a periodic structure that can produce diffraction under the irradiation of the alignment laser. For example, the second alignment mark 106 is one of the scribe-line primary marks (SPM) or the multi-function scribe-line primary marks (VSPM). By adopting SPM or VSPM, the second alignment mark 106 can be automatically recognized by the mainstream lithography machine on the market, and has the advantage of high recognition accuracy. The second alignment mark 106 may include at least two alignment marks. For example, the second alignment mark 106 may include two alignment marks in mutually orthogonal directions, respectively used to calibrate the two orthogonal directions. The second alignment mark that can be automatically recognized by the lithography machine can avoid errors introduced by manual alignment, thereby effectively improving the alignment accuracy. In some cases, the alignment deviation can be reduced to a range of less than 1 micron.

[0086] In some embodiments, the second alignment mark 106 and the fourth alignment mark are both alignment marks that can be automatically recognized by the lithography machine. The lithography machine can realize automatic alignment of the light shield and the semiconductor device according to the coordinate positions of the second alignment mark 106 and the fourth alignment mark. It should be recognized that the alignment of the light shield and the semiconductor device here should be understood as the alignment of the projection of the pattern of the light shield on the semiconductor device with the area to be exposed of the semiconductor device.

[0087] In step 906 , the second light shield 22 is aligned with the to-be-exposed area of ​​the second surface S2 of the substrate 101 by using the fourth alignment mark and the second alignment mark 106 .

[0088] In some implementations, the lithography machine determines the position of the second light shield 22 according to the fourth alignment mark, fixes the second light shield 22, determines the position of the semiconductor device 1000 according to the second alignment mark 106, and moves the semiconductor device 1000 according to the relative position between the second light shield 22 and the semiconductor device 1000, so as to align the second light shield 22 with the semiconductor device 1000, more specifically, to automatically align the second light shield 22 with the area to be exposed on the second surface S2 of the substrate 101. It should be understood that the second alignment mark 106 and the fourth alignment mark are not necessarily aligned with each other in position. As long as the second alignment mark 106 and the fourth alignment mark can respectively determine the position of the semiconductor device 1000 and the second light shield 22, the projection of the pattern (e.g., the through hole pattern 117) on the second light shield 22 on the second surface S2 can be aligned with the area to be exposed on the second surface S2, so as to achieve exposure of the second through hole pattern through the second light shield 22.

[0089] In step 908, the through hole pattern 117 is transferred to the area to be exposed of the second surface S2 by photolithography, and etched to form the second through hole 107. Photoresist can be applied to the second surface S2 first. Through photolithography, the through hole pattern 117 is formed on the photoresist in the exposed area of ​​the second surface S2 to complete the transfer in step 908. Then, the second surface S2 after the transfer is deeply etched, so that the second through hole 107 can be formed.

[0090] Fig.11 is a schematic structural diagram of a semiconductor device according to some embodiments of the present disclosure.

[0091] exist Fig.11 In the embodiment, the semiconductor device 1100 has formed a second through hole 107, wherein the position of the second through hole 107 relative to the second alignment mark 106 is determined according to the first coordinate position, the first preset relative position and the second preset relative position.

[0092] In some embodiments, Fig.11 The semiconductor device 1100 is shown as Figure 1 The semiconductor device 100 shown is obtained after subsequent processing. Fig.11 In the embodiment shown, Figure 1 The second through hole 107 has been formed at the position of the dotted line shown. The relative position relationship between the second through hole 107 and the conductive trace 104 is successfully determined by two groups of alignment marks, so that the second through hole 107 and the conductive trace 104 are aligned.

[0093] Fig.12 A schematic diagram showing a second through-hole forming process according to some embodiments of the present disclosure is shown.

[0094] In some implementations, such as Fig.12 As shown, the second through hole of the semiconductor device 1200 is not directly connected to the wiring layer 102 during the formation process, but a front through hole 1071 extending to the buffer layer 109 is first formed, and an inner wall dielectric layer 115 is formed on the inner wall (including the side wall and the bottom) of the front through hole 1071, and the front through hole 1071 is further etched to remove part of the inner wall dielectric layer 115 at the bottom of the inner wall to form a side wall dielectric layer 118 and extend the second through hole 107 to the wiring layer 102.

[0095] In the above manner, the second through hole 107 can be prevented from extending directly to the conductive trace 102, thereby improving reliability. The sidewall dielectric layer 118 can isolate the metal connector 108 subsequently filled in the second through hole 107 from other conductive materials outside the conductive trace 104, so as to prevent the semiconductor device 1200 from having a conductive failure. The material of the sidewall dielectric layer 118 is an insulating material. In some embodiments, the material of the sidewall dielectric layer 118 and the dielectric layer 112 is the same, both of which are nitride or oxide.

[0096] In some embodiments, Fig.12 As shown, after the second via 107 is formed, one end of the second via 107 adjacent to the conductive trace 104 extends through the buffer layer 109 to the wiring layer 102 .

[0097] Back to Figure 2 In some embodiments, the manufacturing method 200 further includes filling a metal connector in the second through hole. Fig.13 FIG. 1 is a schematic diagram showing a structure of a semiconductor device 1300 filled with metal connectors according to some embodiments of the present disclosure. Fig.13 In the semiconductor device 1300 shown, the second through hole 107 is filled with a metal connector 108. One end of the metal connector 108 is connected to the conductive trace 104. Through the metal connector 108, the conductive trace 104 in the wiring layer 102 of the first surface S1 of the substrate 101 is electrically connected to the second surface S2 of the substrate 101.

[0098] In some embodiments, before filling the metal connector 108, a barrier layer and a seed layer are sequentially formed on the inner wall (including the sidewall and the bottom) of the second through hole 107. The main material for forming the barrier layer is Ta or TaN to prevent the diffusion of the metal connector into the dielectric layer. The main material used to form the seed layer is the same as the main material of the metal connector 108, but may be doped with different other metal elements. Through the conductive effect of the seed layer, the metal connector 108 can be formed by an electroplating process.

[0099] In some embodiments, before the metal connector 108 is filled, a sidewall dielectric layer (such as Fig.12 A sidewall dielectric layer 118 is shown, a barrier layer and a seed layer are formed on the sidewall dielectric layer and the bottom of the second through hole 107, and then a metal connector 108 is formed through the conductive effect of the seed layer.

[0100] Back to Figure 2 In some embodiments, the manufacturing method 200 further includes performing a wafer planarization process on the semiconductor device after filling the metal connector, so that the second surface of the substrate becomes flat to facilitate subsequent processing.

[0101] According to the manufacturing method 200 of the embodiment of the present disclosure, a back-through hole alignment method is provided, which realizes high-precision back-side alignment of the back-through hole process by transferring the alignment mark to the back side of the substrate, and finally realizes the interconnection between the back through hole and the front wiring layer of the semiconductor device. The method achieves high alignment accuracy by using a second alignment mark that can be automatically identified by a high-precision lithography machine. In addition, since the alignment mark is directly transferred to the back side of the substrate, there is no need to use a transparent carrier made of glass or a special light source to identify the alignment mark, which can be compatible with more manufacturing equipment and improve the stability and yield of the manufacturing process. In addition, the method does not need to use an infrared alignment function, and is therefore not limited by the film layer structure such as the metal wiring layer and the bonding layer in the front process.

[0102] In addition to the semiconductor device in the above-mentioned embodiment, the present disclosure also proposes another semiconductor device.

[0103] Fig.14 is a schematic structural diagram of a semiconductor device according to some other embodiments of the present disclosure.

[0104] In some embodiments, Fig.14 As shown, the semiconductor device 1400 includes: a substrate 1401; a wiring layer 1402, the wiring layer 1402 is located on the first surface S1 of the substrate 1401, and the wiring layer 1402 includes a first alignment mark 1403 and a conductive trace 1404; a first through hole 1405 and a second through hole 1407 passing through the substrate 1401, the orthographic projection of the first through hole 1405 on the wiring layer 1402 covers the first alignment mark 1403, and the orthographic projection of the second through hole 1407 on the wiring layer 1402 at least partially overlaps with the conductive trace 1404.

[0105] In the above embodiment, on the second surface S2 of the substrate 1401, the first alignment mark 1403 is observed through the first through hole 1405, which facilitates alignment on the second surface S2 through the first alignment mark 1403. The second through hole 1407 is formed at the second surface S2 of the substrate 1401, and corresponds to the conductive trace 1404 of the wiring layer 1402 on the first surface S1 of the substrate, so as to achieve communication between the two surfaces of the substrate 1401 through the second through hole 1407 in subsequent processing.

[0106] In some embodiments, the second through hole 1407 is formed with the first alignment mark 1403 as a position reference. The first alignment mark 1403 on the first surface S1 of the substrate 1401 can help determine the conductive trace 1404 located on the wiring layer 1402. On the second surface S2 of the substrate 1401, the first alignment mark 1403 is observed through the first through hole 1405, and the second through hole 1407 is also formed on the second surface S2. The above method allows the mark on the first surface S1 to be observed from the second surface S2 through the first through hole 1405, which facilitates alignment from the second surface S2.

[0107] In some embodiments, the first alignment mark 1403 has a first coordinate position and a first preset relative position relative to the conductive trace 1404, and the position of the second through hole 1407 is determined according to the first coordinate position and the first preset relative position. This allows the position of the conductive trace 1403 on the first surface S1 of the substrate 1401 to be determined from the second surface S2 of the substrate 1401 through the first through hole 505 according to the first alignment mark 1403. The above method can determine the position of the second through hole of the semiconductor device without special processing of the substrate, and when preparing the semiconductor device 1400, there is no need to modify the manufacturing equipment of the semiconductor device (for example, equip it with an additional special light source, etc.), which can improve the compatibility of the manufacturing equipment during the manufacturing process and reduce the manufacturing cost of the semiconductor device 1400.

[0108] In some embodiments, the first alignment mark 1403 has a first coordinate position, and the position of the first through hole 1405 is determined according to the first coordinate position. The existence of the first through hole 1405 allows the first alignment mark 1403 in the wiring layer 1402 on the first surface S1 of the substrate 1401 to be observed from the direction of the second surface S2 of the substrate 1401, so the first alignment mark 1403 needs to be covered during formation. The coordinate position can be used to accurately locate the position of the first through hole corresponding to the first alignment mark 1403 formed on the second surface S2 of the substrate 1401 so that the first alignment mark 1403 can be observed.

[0109] So far, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution disclosed here.

[0110] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A semiconductor device comprising: substrate; a wiring layer, the wiring layer being located on the first surface of the substrate, the wiring layer comprising a first alignment mark and a conductive trace, the first alignment mark having a first coordinate position and a first preset relative position relative to the conductive trace; a first through hole, wherein the first through hole penetrates the substrate to expose the first alignment mark, and an orthographic projection of the first through hole on the wiring layer covers the first alignment mark; and a second alignment mark, the second alignment mark being located on a second surface of the substrate opposite to the first surface, the second alignment mark having a second preset relative position relative to the first alignment mark, and the second alignment mark being capable of being used as a position reference when forming a second through hole penetrating the substrate so that an orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace.

2. The device according to claim 1 further comprises the second through hole, wherein the second through hole is a rear through hole, and the position of the second through hole relative to the second alignment mark is determined according to the first coordinate position, the first preset relative position and the second preset relative position.

3. The device according to claim 2, wherein: A metal connector is filled in the second through hole, and one end of the metal connector is connected to the conductive trace.

4. The device according to claim 2, wherein: A buffer layer is provided between the substrate and the wiring layer, an end of the first through hole adjacent to the first alignment mark extends to the buffer layer, and an end of the second through hole adjacent to the conductive trace extends through the buffer layer to the wiring layer.

5. The apparatus according to claim 1, further comprising: A carrier is bonded to a surface of the wiring layer away from the substrate.

6. The device according to claim 1, wherein: The second alignment mark is an alignment mark that can be automatically recognized by a photolithography machine.

7. The device according to claim 1, wherein: The first alignment mark includes at least two alignment marks located at different positions of the wiring layer.

8. The device according to claim 1, wherein: The wiring layer comprises a pattern area and a cutting path area, the conductive trace is located in the pattern area, and the orthographic projection of the second alignment mark on the wiring layer is located in the cutting path area of ​​the wiring layer.

9. A method for manufacturing a semiconductor device, comprising: forming a wiring layer on a first surface of the substrate, the wiring layer comprising a first alignment mark and a conductive trace, the first alignment mark having a first coordinate position and a first predetermined relative position relative to the conductive trace; forming a first through hole penetrating the substrate from a second surface of the substrate opposite to the first surface to expose the first alignment mark, wherein an orthographic projection of the first through hole on the wiring layer covers the first alignment mark; as well as A second alignment mark is formed on the second surface of the substrate, the second alignment mark having a second preset relative position relative to the first alignment mark, and the second alignment mark can be used as a position reference when forming a second through hole penetrating the substrate so that the orthographic projection of the second through hole on the wiring layer at least partially overlaps with the conductive trace.

10. The method according to claim 9, further comprising: The second through hole is formed penetrating from the second surface of the substrate by taking the second alignment mark as a position reference.

11. The method according to claim 10, wherein: The forming of a second through hole penetrating the substrate from the second surface of the substrate using the second alignment mark as a position reference comprises: Determine the position of the second through hole on the first surface of the substrate according to the first coordinate position, the first preset relative position and the second preset relative position; Prepare a second light shield according to the position of the second through hole on the first surface of the substrate, wherein the second light shield includes a through hole pattern for forming the second through hole and a fourth alignment mark; Aligning the second light shield with the area to be exposed on the second surface of the substrate by using the fourth alignment mark and the second alignment mark; and The through hole pattern is transferred to the area to be exposed on the second surface by photolithography, and then etched to form the second through hole.

12. The method according to claim 9, wherein: The forming of a first through hole penetrating the substrate comprises: Determine a first etching position on the second surface of the substrate according to the first coordinate position; Etching is performed at the first etching position until the substrate is penetrated to form the first through hole.

13. The method according to claim 9, wherein: The forming of a second alignment mark on the second surface of the substrate comprises: preparing a first light shield, on which a third alignment mark corresponding to the first alignment mark and a mark pattern for forming a second alignment mark are provided, and the position of the mark pattern relative to the third alignment mark defines the second preset relative position; and While the third alignment mark of the first light shield is aligned with the first alignment mark, the mark pattern is transferred to the second surface of the substrate to form the second alignment mark.

14. The method according to claim 13, wherein: The position of the mark pattern on the first light shield relative to the third alignment mark is determined based on the position of the conductive trace relative to the first alignment mark.

15. The method according to claim 9, further comprising: Before forming the first through hole, a carrier is bonded to a surface of the wiring layer away from the substrate, and the substrate is thinned from the second surface.

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