Minimum on-time circuit and DC-DC converter

Abstract

The present application is applicable to the technical field of DC-DC converters, and provides a minimum on-time circuit and a DC-DC converter. The minimum on-time circuit includes a first pulse width conversion unit, a second pulse width conversion unit and a logic unit. The first pulse width conversion unit is electrically connected to the second pulse width conversion unit and the logic unit, respectively, and the second pulse width conversion unit is electrically connected to the logic unit. The first pulse width conversion unit is used to output a first pulse signal of a first pulse width according to an input voltage pulse signal, the second pulse width conversion unit is used to output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit is used to output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal. The minimum on-time circuit provided in the present application can ensure the accuracy of the third pulse width of the third pulse signal output by the minimum on-time circuit, thereby ensuring the accuracy of the minimum on-time.

Description

Technical Field

[0001] The present application belongs to the technical field of DC-DC converters, and in particular, relates to a minimum on-time circuit and a DC-DC converter. Background Art

[0002] In the field of DC-DC converters, current detection is a widely used function. By detecting the current, functions such as current mode control, constant current output and overcurrent protection can be realized. In order to ensure effective current detection, the current is usually sampled and processed during the on-time of the switch tube, which takes a certain amount of time. Therefore, in order to ensure accurate detection of the current, the minimum on-time of the switch tube must not be less than the time required for current sampling and processing. Therefore, the accuracy of the minimum on-time output by the minimum on-time circuit is crucial for the current detection of the DC-DC converter. However, in the existing minimum on-time circuit, the square wave voltage output will change with the change of the input voltage pulse width, and the minimum on-time will also change accordingly. Especially when the input voltage pulse width is small, it may cause the problem of inaccurate minimum on-time. Summary of the invention

[0003] The embodiments of the present application provide a minimum on-time circuit and a DC-DC converter, which can solve the problem that the existing minimum on-time circuit may cause inaccurate minimum on-time when the input voltage pulse width is small.

[0004] In a first aspect, an embodiment of the present application provides a minimum on-time circuit, comprising a first pulse width conversion unit, a second pulse width conversion unit and a logic unit, wherein the first pulse width conversion unit is electrically connected to the second pulse width conversion unit and the logic unit respectively, and the second pulse width conversion unit is electrically connected to the logic unit;

[0005] The first pulse width conversion unit is used to output a first pulse signal of a first pulse width according to an input voltage pulse signal, the second pulse width conversion unit is used to output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit is used to output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal; wherein the third pulse width is the difference between the first pulse width and the second pulse width.

[0006] In a possible implementation of the first aspect, the first pulse width conversion unit includes a first switch tube, a second switch tube, a first resistor, a first capacitor and a first inverter, the gate of the first switch tube and the gate of the second switch tube are both used to receive the input voltage pulse signal, the source of the first switch tube is used to be electrically connected to a power supply, the drain of the first switch tube is electrically connected to the first end of the first resistor, the drain of the second switch tube is respectively electrically connected to the second end of the first resistor, the first end of the first capacitor and the input end of the first inverter, the source of the second switch tube and the second end of the first capacitor are both grounded, and the output end of the first inverter is respectively electrically connected to the second pulse width conversion unit and the logic unit.

[0007] In a possible implementation of the first aspect, the second pulse width conversion unit includes a third switch tube, a fourth switch tube, a second resistor and a second capacitor, the gate of the third switch tube is electrically connected to the gate of the fourth switch tube, the first pulse width conversion unit and the logic unit, the source of the third switch tube is used to be electrically connected to a power supply, the drain of the third switch tube is electrically connected to the first end of the second resistor and the first end of the second capacitor, the drain of the fourth switch tube is electrically connected to the second end of the second resistor, and the source of the fourth switch tube and the second end of the second capacitor are both grounded.

[0008] In a possible implementation of the first aspect, the second pulse width conversion unit also includes a second inverter and a third inverter, the input end of the second inverter is electrically connected to the drain of the third switch tube, the first end of the second resistor and the first end of the second capacitor, respectively, the output end of the second inverter is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the logic unit.

[0009] In a possible implementation of the first aspect, the logic unit includes a NAND gate, a first input end of the NAND gate is electrically connected to the first pulse width conversion unit for receiving the first pulse signal; a second input end of the NAND gate is electrically connected to the second pulse width conversion unit for receiving the second pulse signal; and an output end of the NAND gate is used to output the third pulse signal.

[0010] In a possible implementation of the first aspect, the minimum on-time circuit also includes a fourth inverter and a fifth inverter, the input end of the fourth inverter is used to receive the input voltage pulse signal, and the output end of the fourth inverter is electrically connected to the input end of the fifth inverter; the output end of the fifth inverter is electrically connected to the first pulse width conversion unit for outputting a filtered signal.

[0011] In a possible implementation of the first aspect, the minimum on-time circuit also includes a delay elimination unit, which is electrically connected to the first pulse width conversion unit and the logic unit, respectively, and is used to output a fourth pulse signal based on the filtered signal and the third pulse signal, and the fourth pulse signal and the filtered signal have rising edges at the same time.

[0012] In a possible implementation of the first aspect, the delay elimination unit includes a NOR gate, a sixth inverter and a seventh inverter, the input end of the sixth inverter is electrically connected to the logic unit, the output end of the sixth inverter is electrically connected to the first input end of the NOR gate, the second input end of the NOR gate is electrically connected to the first pulse width conversion unit, the output end of the NOR gate is electrically connected to the input end of the seventh inverter, and the output end of the seventh inverter is used to output the fourth pulse signal.

[0013] In a possible implementation of the first aspect, the delay elimination unit also includes an eighth inverter and a ninth inverter, the input end of the eighth inverter is electrically connected to the first pulse width conversion unit, the output end of the eighth inverter is electrically connected to the input end of the ninth inverter, and the output end of the ninth inverter is electrically connected to the second input end of the NOR gate.

[0014] In a second aspect, an embodiment of the present application provides a DC-DC converter, comprising the minimum on-time circuit described in any one of the first aspects.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0016] The minimum on-time circuit provided by the embodiment of the present application includes a first pulse width conversion unit, a second pulse width conversion unit and a logic unit. Among them, the first pulse width conversion unit is electrically connected to the second pulse width conversion unit and the logic unit respectively, and can output a first pulse signal of a first pulse width according to an input voltage pulse signal. The second pulse width conversion unit can output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit can output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal, wherein the third pulse width is the difference between the first pulse width and the second pulse width. It can be seen that compared with the traditional minimum on-time circuit including only the first pulse width conversion unit, the minimum on-time circuit provided by the embodiment of the present application further converts the first pulse signal by adding a second pulse width conversion unit, and outputs a second pulse signal. Then the logic unit is used to output the third pulse signal according to the first pulse signal and the second pulse signal. When the pulse width of the input voltage pulse signal changes, the first pulse width of the first pulse signal will change accordingly. The second pulse width of the second pulse signal changes according to the change of the first pulse width, and the difference between the first pulse width and the second pulse width is a fixed value. Since the third pulse width is the difference between the first pulse width and the second pulse width, the third pulse width is a fixed value and will not change with the pulse width of the input voltage pulse signal, thereby ensuring the accuracy of the third pulse width of the third pulse signal output by the minimum on-time circuit. Using the third pulse signal with the third pulse width to drive the switch tube can ensure that there is sufficient time for current sampling and processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 is a principle block diagram of a minimum on-time circuit provided in one embodiment of the present application;

[0019] Figure 2 1 is a circuit connection diagram of a minimum on-time circuit provided in an embodiment of the present application;

[0020] Figure 3 is a schematic diagram of voltage waveforms in a minimum on-time circuit provided in an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a voltage waveform in a minimum on-time circuit provided in another embodiment of the present application;

[0022] Figure 5is a principle block diagram of a minimum on-time circuit provided by another embodiment of the present application;

[0023] Figure 6 is a circuit connection diagram of a minimum on-time circuit provided by another embodiment of the present application;

[0024] Figure 7 It is a schematic diagram of voltage waveform in a minimum on-time circuit provided in another embodiment of the present application.

[0025] In the figure, 10 is a minimum on-time circuit; 101 is a first pulse width conversion unit; 102 is a second pulse width conversion unit; 103 is a logic unit; and 104 is a delay elimination unit. DETAILED DESCRIPTION

[0026] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0027] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0028] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0029] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0030] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0032] In the existing minimum on-time circuit, the square wave voltage output will change with the change of the input voltage pulse width, and the minimum on-time will also change accordingly. Especially when the input voltage pulse width is small, the minimum on-time may be inaccurate.

[0033] Based on the above problems, the minimum on-time circuit provided by the embodiment of the present application includes a first pulse width conversion unit, a second pulse width conversion unit and a logic unit. Among them, the first pulse width conversion unit is electrically connected to the second pulse width conversion unit and the logic unit respectively, and can output a first pulse signal of a first pulse width according to the input voltage pulse signal. The second pulse width conversion unit can output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit can output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal, wherein the third pulse width is the difference between the first pulse width and the second pulse width. It can be seen that compared with the traditional minimum on-time circuit including only the first pulse width conversion unit, the minimum on-time circuit provided by the embodiment of the present application further converts the first pulse signal by adding a second pulse width conversion unit, and outputs a second pulse signal. Then the logic unit is used to output the third pulse signal according to the first pulse signal and the second pulse signal. When the pulse width of the input voltage pulse signal changes, the first pulse width of the first pulse signal will change accordingly. The second pulse width of the second pulse signal changes according to the change of the first pulse width, and the difference between the first pulse width and the second pulse width is a fixed value. Since the third pulse width is the difference between the first pulse width and the second pulse width, the third pulse width is a fixed value and will not change with the pulse width of the input voltage pulse signal, thereby ensuring the accuracy of the third pulse width of the third pulse signal output by the minimum on-time circuit. Using the third pulse signal with the third pulse width to drive the switch tube can ensure that there is sufficient time for current sampling and processing.

[0034] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0035] Figure 1FIG. 1 shows a principle block diagram of a minimum on-time circuit 10 provided in an embodiment of the present application. Figure 1 As shown, the minimum on-time circuit 10 comprises a first pulse width conversion unit 101, a second pulse width conversion unit 102 and a logic unit 103. The first pulse width conversion unit 101 is electrically connected to the second pulse width conversion unit 102 and the logic unit 103 respectively, and the second pulse width conversion unit 102 is electrically connected to the logic unit 103.

[0036] Specifically, the first pulse width conversion unit 101 can output a first pulse signal of a first pulse width according to the input voltage pulse signal. The second pulse width conversion unit 102 can output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit 103 can output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal, wherein the third pulse width is the difference between the first pulse width and the second pulse width. It can be seen that, compared with the traditional minimum on-time circuit including only the first pulse width conversion unit 101, the minimum on-time circuit 10 provided in the embodiment of the present application further converts the first pulse signal by adding the second pulse width conversion unit 102, and outputs the second pulse signal. The logic unit 103 is then used to output the third pulse signal according to the first pulse signal and the second pulse signal. When the pulse width of the input voltage pulse signal changes, the first pulse width of the first pulse signal will change accordingly. The second pulse width of the second pulse signal changes according to the change of the first pulse width, and the difference between the first pulse width and the second pulse width is a fixed value. Since the third pulse width is the difference between the first pulse width and the second pulse width, the third pulse width is a fixed value and will not change with the pulse width of the input voltage pulse signal, thereby ensuring the accuracy of the third pulse width of the third pulse signal output by the minimum on-time circuit 10. Using the third pulse signal with the third pulse width to drive the switch tube can ensure that there is sufficient time for current sampling and processing.

[0037] It should be noted that the pulse width of the input voltage pulse signal changes, including the narrowing of the pulse width of the input voltage pulse signal and the widening of the pulse width of the input voltage pulse signal. For example, if the pulse width of the input voltage pulse signal widens, the first pulse width of the first pulse signal will also widen, because the second pulse width of the second pulse signal changes according to the change of the first pulse width, and the difference between the first pulse width and the second pulse width is a fixed value. Since the third pulse width is the difference between the first pulse width and the second pulse width, it can be ensured that the third pulse width will not change with the widening of the pulse width of the input voltage pulse signal, thereby ensuring the accuracy of the third pulse width of the third pulse signal output by the minimum on-time circuit 10, thereby ensuring the accuracy of the minimum on-time.

[0038] For example, designers can adjust the pulse width of the input voltage pulse signal according to actual conditions. If the pulse width of the input voltage pulse signal changes from 1us to 1.2us (widened by 0.2us), the first pulse width will also widen by 0.2us, and the second pulse width will also widen by 0.2us. The third pulse width is the difference between the first pulse width and the second pulse width, and remains a fixed value.

[0039] In one embodiment of the present application, Figure 2 As shown, the first pulse width conversion unit 101 includes a first switch tube M1, a second switch tube M2, a first resistor R1, a first capacitor C1 and a first inverter INV1. The gate of the first switch tube M1 and the gate of the second switch tube M2 are both used to receive an input voltage pulse signal. The source of the first switch tube M1 is used to be electrically connected to the power supply VDD. The drain of the first switch tube M1 is electrically connected to the first end of the first resistor R1. The drain of the second switch tube M2 is electrically connected to the second end of the first resistor R1, the first end of the first capacitor C1 and the input end of the first inverter INV1 respectively. The source of the second switch tube M2 and the second end of the first capacitor C1 are both grounded. The output end of the first inverter INV1 is electrically connected to the second pulse width conversion unit 102 and the logic unit 103 respectively.

[0040] Specifically, the first switch tube M1 and the second switch tube M2 are used as switch devices, and are both used to turn on or off according to the input voltage pulse signal, so as to control the flow of current in the first pulse width conversion unit 101. When the input voltage pulse signal is at a low level, the first switch tube M1 is turned on according to the low level signal, and the second switch tube M2 is turned off according to the low level, and the voltage (V2) at the connection point between the drain of the first switch tube M1 and the drain of the second switch tube M2 is pulled up. When the input voltage pulse signal is at a high level, the first switch tube M1 is turned off according to the high level, and the second switch tube M2 is turned on according to the high level, and the voltage (V2) at the connection point between the drain of the first switch tube M1 and the drain of the second switch tube M2 is pulled down. Therefore, the first switch tube M1 and the second switch tube M2 can invert the voltage of the input voltage pulse signal.

[0041] The function of the first resistor R1 and the first capacitor C1 is to make the transition of the V2 voltage smoother when it changes from a low level to a high level. Specifically, when the V2 voltage changes from a low level to a high level, the first capacitor C1 is in a charging state, and the first resistor R1 will limit the charging speed of the first capacitor C1. The first resistor R1 and the first capacitor C1 form a low-pass filter, so that the change of the V2 voltage becomes slower and smoother. By adjusting the capacity value of the first capacitor C1 and the resistance value of the first resistor R1, the rising speed of the V2 voltage can be adjusted, thereby achieving a smooth transition effect. The first inverter INV1 is used for when the V2 voltage rises slowly and the voltage is greater than the flip threshold of the first inverter INV1, the voltage (V3) at the output end of the first inverter INV1 and the connection point of the second pulse width conversion unit 102 is flipped from a high level to a low level, and the first pulse signal of the first pulse width, that is, the V3 voltage signal, can be obtained from the V2 voltage.

[0042] For example, the designer can select the type of the first switch tube M1 and the second switch tube M2 according to the actual situation, that is, both can use fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the first switch tube M1 can be selected as a PMOS tube, and the second switch tube M2 can be selected as an NMOS tube.

[0043] For example, the waveform diagram of the process in which the voltage V2 changes from a low level to a high level can be seen in Figure 3 As shown, the waveform in this process can be called a ramp wave. The calculation formula for the V2 voltage ramp wave is:

[0044]

[0045] Wherein, VDD is the power supply voltage output by the power supply VDD, R1 is the resistance value of the first resistor R1, C1 is the capacity value of the first capacitor C1, and t is the time required for the V2 voltage to change from a low level to a high level, that is, Figure 3 t1-t4 in.

[0046] In one embodiment of the present application, Figure 2 As shown, the minimum on-time circuit 10 also includes a fourth inverter INV4 and a fifth inverter INV5, the input end of the fourth inverter INV4 is used to receive an input voltage pulse signal, the output end of the fourth inverter INV4 is electrically connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is electrically connected to the gate of the first switch tube M1 and the gate of the second switch tube M2, respectively, for outputting a filtered signal.

[0047] Specifically, after the fourth inverter INV4 receives the input voltage pulse signal, it inverts the input voltage pulse signal and outputs it, that is, when the input voltage pulse signal is at a high level, the fourth inverter INV4 outputs a low level, and when the input voltage pulse signal is at a low level, the fourth inverter INV4 outputs a high level. After the fifth inverter INV5 receives the signal output by the fourth inverter INV4, it inverts the signal again and outputs it. At the same time, the fourth inverter INV4 and the fifth inverter INV5 are also used for filtering, and the input voltage pulse signal can be converted into a filtered signal (V1 voltage signal). It can achieve precise control of the first switch tube M1 and the second switch tube M2, ensuring that the first pulse width conversion unit 101 outputs a precise first pulse signal.

[0048] Combine the following Figure 2 A circuit connection diagram of the first pulse width conversion unit 101 and Figure 3 The voltage waveform diagram in FIG. 1 is used to describe the first pulse width conversion unit 101 in detail.

[0049] After the input voltage pulse signal VIN is input to the first pulse width conversion unit 101, the fourth inverter INV4 and the fifth inverter INV5 are used for inversion and filtering, so that the input voltage pulse signal VIN is converted into a V1 voltage signal (filtered signal). Then, the V1 voltage signal is inverted through the first switch tube M1 and the second switch tube M2, and the first resistor R1 and the first capacitor C1 are used to make the process of the V2 voltage signal changing from a low level to a high level (i.e., t1-t4) smoother during the process of the V1 voltage signal changing from a high level to a low level (i.e., t1-t4). Finally, the first inverter INV1 is used, and when the V2 voltage rises slowly and the voltage is greater than the flip threshold of the first inverter INV1 (i.e., t3), the V3 voltage signal flips from a high level to a low level, and finally a first pulse signal of a first pulse width is obtained, i.e., the V3 voltage signal.

[0050] It should be noted that, in the waveform diagram shown in the present application, the input voltage pulse signal VIN is a square wave signal, which is only used as an example and does not constitute any limitation on the working principle of the embodiment of the present application.

[0051] In one embodiment of the present application, Figure 2As shown, the second pulse width conversion unit 102 includes a third switch tube M3, a fourth switch tube M4, a second resistor R2 and a second capacitor C2. The gate of the third switch tube M3 is electrically connected to the gate of the fourth switch tube M4, the first pulse width conversion unit 101 and the logic unit 103 respectively. The source of the third switch tube M3 is used to be electrically connected to the power supply VDD. The drain of the third switch tube M3 is electrically connected to the first end of the second resistor R2 and the first end of the second capacitor C2 respectively. The drain of the fourth switch tube M4 is electrically connected to the second end of the second resistor R2. The source of the fourth switch tube M4 and the second end of the second capacitor C2 are both grounded.

[0052] Specifically, the third switch tube M3 and the fourth switch tube M4 are used as switch devices, and are both used to turn on or off according to the first pulse signal, so as to control the flow of current in the second pulse width conversion unit 102. When the first pulse signal is at a low level, the third switch tube M3 is turned on according to the low level signal, and the fourth switch tube M4 is turned off according to the low level, and the voltage (V4) at the connection point between the drain of the third switch tube M3 and the drain of the fourth switch tube M4 is pulled high. When the first pulse signal is at a high level, the third switch tube M3 is turned off according to the high level, and the fourth switch tube M4 is turned on according to the high level, and the voltage (V4) at the connection point between the drain of the third switch tube M3 and the drain of the fourth switch tube M4 is pulled low. Therefore, the third switch tube M3 and the fourth switch tube M4 can invert the voltage of the first pulse signal.

[0053] The second resistor R2 and the second capacitor C2 function to make the transition of the V4 voltage from a high level to a low level smoother. Specifically, in the process of the V4 voltage changing from a high level to a low level, the second capacitor C2 is in a discharging state, and the second resistor R2 will limit the discharge speed of the second capacitor C2. The second resistor R2 and the second capacitor C2 form a low-pass filter, so that the change of the V4 voltage becomes slower and smoother. By adjusting the capacity value of the second capacitor C2 and the resistance value of the second resistor R2, the drop speed of the V4 voltage can be adjusted, thereby achieving a smooth transition effect.

[0054] For example, the designer can select the types of the third switch tube M3 and the fourth switch tube M4 according to the actual situation, that is, both can use fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the third switch tube M3 can be selected as a PMOS tube, and the fourth switch tube M4 can be selected as an NMOS tube.

[0055] For example, the waveform diagram of the process in which the voltage V4 changes from a high level to a low level can be seen in Figure 3 As shown, the waveform in this process can be called a ramp wave. The calculation formula for the V4 voltage ramp wave is:

[0056]

[0057] Wherein, VDD is the power supply voltage output by the power supply VDD, R2 is the resistance value of the second resistor R2, C2 is the capacity value of the second capacitor C2, and t is the time required for the voltage of V4 to change from a high level to a low level, that is, Figure 3 The time period t0-t3 in .

[0058] In one embodiment of the present application, Figure 2 As shown, the second pulse width conversion unit 102 also includes a second inverter INV2 and a third inverter INV3, the input end of the second inverter INV2 is electrically connected to the drain of the third switch tube M3, the first end of the second resistor R2 and the first end of the second capacitor C2 respectively, the output end of the second inverter INV2 is electrically connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is electrically connected to the logic unit 103.

[0059] Specifically, the second inverter INV2 is used to flip the output end of the second inverter INV2 from a low level to a high level when the V4 voltage drops smoothly and the voltage is less than the flipping threshold of the second inverter INV2, and then invert and filter the voltage signal output by the second inverter INV2 through the third inverter INV3, so that the second pulse signal with a second pulse width can be obtained from the V4 voltage, that is, the V5 voltage signal.

[0060] Combine the following Figure 2 The circuit connection diagram of the second pulse width conversion unit 102 and Figure 3 The second pulse width conversion unit 102 is described in detail with reference to the voltage waveform diagram in FIG.

[0061] After the first pulse signal (V3 voltage signal) is input to the second pulse width conversion unit 102, the V3 voltage signal is inverted through the third switch tube M3 and the fourth switch tube M4, and the second resistor R2 and the second capacitor C2 are used to make the process of the V4 voltage signal changing from a high level to a low level (i.e., t0-t3) smoother during the process of the V3 voltage signal changing from a low level to a high level (i.e., t0-t3). Finally, the second inverter INV2 and the third inverter INV3 are used. When the V4 voltage drops slowly and the voltage is less than the flip threshold of the second inverter INV2 (i.e., t2), the output end of the second inverter INV2 flips from a low level to a high level, and then the voltage signal output by the second inverter INV2 is inverted and filtered through the third inverter INV3, and finally a second pulse signal of a second pulse width is obtained, i.e., a V5 voltage signal.

[0062] In one embodiment of the present application, Figure 2As shown, the logic unit 103 includes a NAND gate NAND, a first input end of the NAND gate NAND is electrically connected to the first pulse width conversion unit 101 for receiving a first pulse signal, a second input end of the NAND gate NAND is electrically connected to the second pulse width conversion unit 102 for receiving a second pulse signal, and an output end of the NAND gate NAND is used to output a third pulse signal.

[0063] Specifically, the NAND gate receives the first pulse signal (V3 voltage signal) and the second pulse signal (V5 voltage signal), and performs a NAND operation on the first pulse signal and the second pulse signal, that is, the first pulse signal and the second pulse signal are firstly ANDed, and then the result is NOT operated, and finally a third pulse signal (VOUT1 voltage signal) with a third pulse width is output. The specific operation logic of the NAND operation is: when the first pulse signal and the second pulse signal are both low levels, the output end of the NAND gate NAND outputs a high level; when the first pulse signal and the second pulse signal are both high levels, the output end of the NAND gate NAND outputs a low level; when the first pulse signal is high and the second pulse signal is low, the output end of the NAND gate NAND outputs a low level; when the first pulse signal is low and the second pulse signal is high, the output end of the NAND gate NAND outputs a low level.

[0064] For example, Figure 3 As shown, the pulse width of the third pulse signal (VOUT1 voltage signal) is equal to the difference between the pulse width of the V3 voltage signal and the pulse width of the V5 voltage signal. The pulse width of the VOUT1 voltage signal does not change with the pulse width of the input voltage pulse signal VIN. For example, Figure 4 As shown, taking the first cycle as an example, when the pulse width of the input voltage pulse signal VIN widens (the pulse width changes from t0-t1 to t0-t8), the pulse width of the V3 voltage signal will also widen (the pulse width changes from t0-t3 to t0-t9), and the pulse width of the V5 voltage signal will also widen (the pulse width changes from t2-t3 to t2-t9), but the pulse width of the VOUT1 voltage signal is still equal to the pulse width of the V3 voltage signal minus the pulse width of the V5 voltage signal (t0-t2), and will not change with the change of the pulse width of the input voltage pulse signal VIN. Thus, the accuracy of the voltage of the third pulse signal output by the minimum on-time circuit 10 is ensured, thereby ensuring the accuracy of the minimum on-time.

[0065] In summary, the minimum on-time circuit 10 provided in the above embodiment does not change the third pulse signal outputted by the input voltage pulse signal pulse width, thereby ensuring the accuracy of the minimum on-time. However, since the third pulse signal VOUT1 outputted after a series of transmissions such as the conversion of the input voltage pulse signal by the first pulse width conversion unit 101, the conversion of the second pulse width conversion unit 102, and the operation of the logic unit 103 will be delayed, the minimum on-time has a certain delay.

[0066] Based on the above problems, in one embodiment of the present application, Figure 5 As shown, the minimum on-time circuit 10 further includes a delay elimination unit 104, which is electrically connected to the first pulse width conversion unit 101 and the logic unit 103. The delay elimination unit 104 is used to output a fourth pulse signal according to the filtered signal and the third pulse signal, and the fourth pulse signal and the filtered signal have the same rising edge.

[0067] Specifically, during the signal transmission process, a certain delay will occur due to the response time of the circuit elements and the physical characteristics of the signal transmission. The delay elimination unit 104 can reduce or eliminate such delay through proper design and control, ensuring that the fourth pulse signal and the filter signal have the same rising edge, so that the output fourth pulse signal can respond to the change of the input voltage pulse signal more timely, thereby realizing synchronous output of the signal, which is conducive to the precise control of the minimum on-time.

[0068] In one embodiment of the present application, Figure 6 As shown, the delay elimination unit 104 includes a NOR gate NOR, a sixth inverter INV6 and a seventh inverter INV7, the input end of the sixth inverter INV6 is electrically connected to the logic unit 103, the output end of the sixth inverter INV6 is electrically connected to the first input end of the NOR gate NOR, the second input end of the NOR gate NOR is electrically connected to the first pulse width conversion unit 101, the output end of the NOR gate NOR is electrically connected to the input end of the seventh inverter INV7, and the output end of the seventh inverter INV7 is used to output a fourth pulse signal.

[0069] Specifically, the sixth inverter INV6 inverts the third pulse signal VOUT1 output by the logic unit 103 to obtain a voltage V6. The voltage V6 and the voltage V1 are input to the NOR gate NOR for NOR operation, and finally inverted and output by the seventh inverter INV7 to obtain a fourth pulse signal VOUT2.

[0070] It should be noted that in the minimum on-time circuit 10, the design of performing an OR operation on two signals (V6 voltage and V1 voltage) and finally performing an inversion operation can achieve more accurate pulse width control and more stable output. Specifically, by performing an OR operation on the two signals, the burrs or noise between the signals can be eliminated, thereby generating a more stable and cleaner output signal. The stability and consistency of the output pulse width under different working conditions can be ensured. The seventh inverter INV7 performs an inversion operation to further adjust the edge and duration of the pulse, thereby achieving more accurate pulse width control. It can also suppress adverse effects caused by signal edge effects. Among them, the edge effect may include the rise time, fall time or transition time of the signal, and the inversion operation can reduce the impact of these edge effects on the output signal, thereby improving the performance and stability of the circuit. At the same time, the inversion operation can also suppress interference signals from other signal sources or interference sources, and improve the anti-interference ability of the minimum on-time circuit 10.

[0071] In one embodiment of the present application, Figure 6 As shown, the delay elimination unit 104 also includes an eighth inverter INV8 and a ninth inverter INV9, the input end of the eighth inverter INV8 is electrically connected to the first pulse width conversion unit 101, the output end of the eighth inverter INV8 is electrically connected to the input end of the ninth inverter INV9, and the output end of the ninth inverter INV9 is electrically connected to the second input end of the NOR gate NOR.

[0072] Specifically, after the eighth inverter INV8 receives the first pulse signal, it inverts and outputs the first pulse signal, that is, when the first pulse signal is at a high level, the eighth inverter INV8 outputs a low level, and when the first pulse signal is at a low level, the eighth inverter INV8 outputs a high level. After the ninth inverter INV9 receives the signal output by the third inverter INV8, it inverts and outputs the signal again. At the same time, the eighth inverter INV8 and the ninth inverter INV9 are also used for filtering, and can convert the first pulse signal into a square wave signal (V7 voltage signal).

[0073] It should be noted that the functions of the eighth inverter INV8 and the ninth inverter INV9 are the same as those of the fourth inverter INV4 and the fifth inverter INV5, that is, the input end of the eighth inverter INV8 can be electrically connected to the input end of the fourth inverter INV4 to receive the input voltage pulse signal.

[0074] For example, Figure 7As shown, during the signal transmission process, due to the response time of the circuit elements and the physical characteristics of the signal transmission, a certain delay will be generated, so that the third pulse signal VOUT1 output by the logic unit 103 is delayed, so that the V6 voltage inverted and output by the sixth inverter INV6 is delayed. Performing a negative or operation on the V6 voltage and the V7 voltage can make the output voltage capture the rising edge of the V7 voltage, so that the fourth pulse signal VOUT2 inverted and output by the seventh inverter INV7 will not be delayed when the high level is flipped.

[0075] The present application also discloses a DC-DC converter, including the above-mentioned minimum on-time circuit 10, which can ensure the accuracy of the minimum on-time, thereby determining the on-time of the switch tube, ensuring sufficient time for current sampling and processing. At the same time, it can also eliminate the delay from input voltage to output voltage, thereby improving the response speed and stability of the system.

[0076] Since the processing and functions implemented by the DC-DC converter in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned minimum on-time circuit, for the details not fully described in this embodiment, reference can be made to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be made here.

[0077] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A minimum on-time circuit, characterized in that: It comprises a first pulse width conversion unit, a second pulse width conversion unit and a logic unit, wherein the first pulse width conversion unit is electrically connected to the second pulse width conversion unit and the logic unit respectively, and the second pulse width conversion unit is electrically connected to the logic unit; The first pulse width conversion unit is used to output a first pulse signal of a first pulse width according to an input voltage pulse signal, the second pulse width conversion unit is used to output a second pulse signal of a second pulse width according to the first pulse signal, and the logic unit is used to output a third pulse signal of a third pulse width according to the first pulse signal and the second pulse signal; wherein the third pulse width is the difference between the first pulse width and the second pulse width; and the third pulse width is a fixed value; The first pulse width conversion unit includes a first switch tube, a second switch tube, a first resistor, a first capacitor and a first inverter, the gate of the first switch tube and the gate of the second switch tube are both used to receive the input voltage pulse signal, the source of the first switch tube is used to be electrically connected to a power supply, the drain of the first switch tube is electrically connected to a first end of the first resistor, the drain of the second switch tube is electrically connected to a second end of the first resistor, a first end of the first capacitor and an input end of the first inverter respectively, the source of the second switch tube and the second end of the first capacitor are both grounded, and the output end of the first inverter is electrically connected to the second pulse width conversion unit and the first input end of the logic unit respectively; The second pulse width conversion unit includes a third switch tube, a fourth switch tube, a second resistor and a second capacitor, the gate of the third switch tube is electrically connected to the gate of the fourth switch tube, the output end of the first pulse width conversion unit and the first input end of the logic unit respectively, the source of the third switch tube is used to be electrically connected to the power supply, the drain of the third switch tube is electrically connected to the first end of the second resistor and the first end of the second capacitor respectively, the drain of the fourth switch tube is electrically connected to the second end of the second resistor, and the source of the fourth switch tube and the second end of the second capacitor are both grounded; The second pulse width conversion unit further includes a second inverter and a third inverter, the input end of the second inverter is electrically connected to the drain of the third switch tube, the first end of the second resistor and the first end of the second capacitor respectively, the output end of the second inverter is electrically connected to the input end of the third inverter, and the output end of the third inverter is electrically connected to the second input end of the logic unit; The minimum on-time circuit further includes a fourth inverter and a fifth inverter, wherein the input end of the fourth inverter is used to receive the input voltage pulse signal, and the output end of the fourth inverter is electrically connected to the input end of the fifth inverter; the output end of the fifth inverter is electrically connected to the input end of the first pulse width conversion unit, and is used to output a filtered signal; The minimum on-time circuit also includes a delay elimination unit, which is electrically connected to the input end of the first pulse width conversion unit and the output end of the logic unit, respectively. The delay elimination unit is used to output a fourth pulse signal based on the filtered signal and the third pulse signal, and the fourth pulse signal and the filtered signal have rising edges at the same time.

2. The minimum on-time circuit according to claim 1, characterized in that: The logic unit includes a NAND gate, a first input end of the NAND gate is electrically connected to the output end of the first pulse width conversion unit, and is used to receive the first pulse signal; a second input end of the NAND gate is electrically connected to the second pulse width conversion unit, and is used to receive the second pulse signal; and an output end of the NAND gate is used to output the third pulse signal.

3. The minimum on-time circuit according to claim 1, characterized in that: The delay elimination unit includes a NOR gate, a sixth inverter and a seventh inverter, the input end of the sixth inverter is electrically connected to the output end of the logic unit, the output end of the sixth inverter is electrically connected to the first input end of the NOR gate, the second input end of the NOR gate is electrically connected to the input end of the first pulse width conversion unit, the output end of the NOR gate is electrically connected to the input end of the seventh inverter, and the output end of the seventh inverter is used to output the fourth pulse signal.

4. The minimum on-time circuit according to claim 3, characterized in that: The delay elimination unit also includes an eighth inverter and a ninth inverter, the input end of the eighth inverter is electrically connected to the input end of the first pulse width conversion unit, the output end of the eighth inverter is electrically connected to the input end of the ninth inverter, and the output end of the ninth inverter is electrically connected to the second input end of the NOR gate.

5. A DC-DC converter, characterized in that: The invention comprises the minimum on-time circuit as described in any one of claims 1 to 4.

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