Chip packaging manufacturing method and chip

Abstract

The present invention relates to a chip packaging manufacturing method, comprising the following steps: S10, depositing a stop layer on the bottom wafer of the upstream unit of the packaging; S20, depositing an oxide layer on the stop layer; S30, opening a through silicon via by an etching process, the etching depth of which reaches the stop layer; S40, etching the stop layer, the etching depth of which reaches the metal layer. The present invention solves the technical problem of excessive etching of the metal layer during chip packaging in the prior art.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a chip packaging manufacturing method and a chip. Background Art

[0002] In the traditional 3D packaging process, the formation of TSV on the silicon substrate using plasma etching process is a key technology. The purpose of this technology is to create vertical connections in the silicon wafer, so that the circuit layers can communicate directly, thereby achieving more efficient electronic signal transmission and more compact integrated circuit layout. This high aspect ratio through-hole structure is crucial to achieving higher density and performance integrated circuits.

[0003] However, there are significant technical challenges in this process. When TSV penetrates the metal layer, due to the lack of precise control means, the etching process may be excessive, resulting in damage to the metal layer (i.e., the "eating through" phenomenon). This situation not only affects the structural integrity of the TSV, but may also damage the underlying circuit layer. On the other hand, if the etching is insufficient, the TSV may not successfully penetrate the metal layer, resulting in circuit interconnection failure. These problems directly affect the performance and reliability of 3D ICs and are key challenges in the development of 3D packaging technology. Summary of the invention

[0004] In view of the deficiencies existing in the related art, the present invention provides a chip packaging manufacturing method to solve the technical problem of excessive etching of the metal layer during chip packaging.

[0005] According to the first aspect of the present application, a chip packaging manufacturing method is provided, and in a possible implementation manner, the method includes the following steps: S10, depositing a stop layer on the bottom wafer of the upstream unit of the package; S20, depositing an oxide layer on the stop layer; S30, opening a through silicon via through an etching process, the etching depth of which reaches the stop layer; S40, etching the stop layer, the etching depth of which reaches the metal layer.

[0006] In a possible implementation, in step S10, depositing a stop layer includes: S11, depositing a layer of silicon nitride precursor material on the bottom wafer using a chemical vapor deposition method; S12, heat treating the silicon nitride precursor material to form a stop layer.

[0007] In a possible implementation manner, the thickness of the stop layer ranges from 100 Å to 600 Å.

[0008] In one possible implementation, a stop layer is deposited before the first metal layer process on the bottom wafer.

[0009] In a possible implementation, the formation of the through silicon via is completed by an ion etching process.

[0010] In a possible implementation manner, the depth of the through silicon via is less than or equal to 100 um.

[0011] In a possible implementation manner, the material of the stop layer is silicon nitride or SiCN containing N element.

[0012] In one possible implementation, the formation of through silicon vias is completed in the stack of the bottom wafer and the top wafer to achieve interconnection.

[0013] In a possible implementation, the method is used for a logic process chip in a 3D advanced packaging process.

[0014] According to another aspect of the present application, a chip is provided. In a possible implementation manner, the chip is manufactured by any of the above chip packaging manufacturing methods.

[0015] Based on the above technical scheme, the chip packaging manufacturing method of the embodiment of the present invention adds an etching stop layer before the metal layer of the bottom wafer to provide a clear etching endpoint, making the etching process more precise and controllable, protecting the metal layer, reducing etching defects, ensuring the integrity and functionality of the circuit, and improving the qualified rate of packaged products. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 A schematic diagram of a chip packaging manufacturing method;

[0018] Figure 2 Schematic diagram of chip structure before etching through silicon vias;

[0019] Figure 3 A schematic diagram of the chip structure after etching through silicon vias to the barrier layer;

[0020] Figure 4 Schematic diagram of the chip structure from etching the barrier layer to the metal layer.

[0021] In the figure:

[0022] 10. Metal layer; 20. Stop layer; 30. Through silicon via; 40. Top metal layer; 50. Shallow trench isolation structure; 60. Silicon substrate; 70. Oxide layer. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] In the description of the present invention, it should be understood that the terms "center", "lateral", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0025] The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In order to solve the technical problem of over-etching of the metal layer during chip packaging in the prior art, the present application provides a chip packaging manufacturing method.

[0028] According to the first aspect of the present application, a chip packaging manufacturing method is provided. Figure 1 In a possible implementation, the following steps are included: S10, depositing a stop layer on the bottom wafer of the upstream unit of the package; S20, depositing an oxide layer on the stop layer; S30, opening a through silicon via through an etching process, the etching depth of which reaches the stop layer; S40, etching the stop layer, the etching depth of which reaches the metal layer.

[0029] Among them, the etch stop layer adopts plasma etching process with source power ranging from 800-1000w, C4F8:O2 ratio controlled ≤1:1 and gas pressure controlled 50-80mt ​​to control the thickness / precision of etching so that the etching can accurately reach the metal layer.

[0030] See also Figure 2 , Figure 3 and Figure 4 , is a schematic diagram of the chip product structure of the chip packaging manufacturing method in the above-mentioned embodiment in different steps.

[0031] In the above scheme, the specific operation of depositing the stop layer 20 in step S10 of the chip packaging manufacturing method is to apply chemical vapor deposition (CVD) technology on the bottom wafer to selectively deposit a silicon nitride layer as the stop layer 20, and the stop layer covers part or all of the metal layer 10. This step involves precise control of deposition parameters such as temperature, gas flow rate and reaction time to ensure uniformity and required thickness of the stop layer.

[0032] Next, in step S20, an oxide layer 70 is deposited on the stop layer by atomic layer deposition (ALD) technology. Figure 2 As shown, to improve the stability and etching resistance of the overall structure. Figure 3 In step S30 , the opening of the TSV 30 uses precise photolithography technology and dry etching process, such as reactive ion etching (RIE), to ensure that the position, shape and depth of the TSV are precisely controlled.

[0033] See also Figure 4 In step S40, the stop layer is etched using C4F8 or C4F6 plasma etching technology. The etching process is precisely controlled by adjusting the plasma source power (within the range of 800-1000W), the ratio of C4F8:O2 (controlled below 1:1) and the gas pressure (50-80mt) to ensure that the obtained etching depth and thickness meet the design requirements and finally reach the metal layer of the bottom wafer.

[0034] The above solution also includes filling copper in the etched through holes to achieve electrical connection between chips.

[0035] In a possible implementation, in step S10, depositing a stop layer includes: S11, depositing a layer of silicon nitride precursor material on the bottom wafer using a chemical vapor deposition method; S12, heat treating the silicon nitride precursor material to form a stop layer.

[0036] In the above scheme, the process of depositing the stop layer in step S10 further includes the following steps: First, in step S11, a silicon nitride precursor material is uniformly deposited on the bottom wafer using chemical vapor deposition (CVD) technology. In this process, the type (such as silane and ammonia) and proportion of the reaction gas, as well as the temperature and pressure of the reaction chamber are controlled to ensure the uniformity and purity of the silicon nitride layer. Subsequently, in step S12, the deposited silicon nitride precursor material is heat-treated. This step is performed at high temperature to enhance the crystallinity and stability of the silicon nitride layer, and finally form a stop layer as an etching control layer. Accurate control of temperature and time during the heat treatment process is crucial to ensure the quality of the stop layer.

[0037] In a possible implementation manner, the thickness of the stop layer ranges from 100 Å to 600 Å.

[0038] In the above scheme, the key to determining the thickness of the stop layer is to control the parameters in the deposition process. In implementation, precise control of the thickness of the stop layer can be achieved by precisely controlling the reaction time, gas flow, reaction temperature and pressure in the chemical vapor deposition (CVD) process. For stop layers with a thickness ranging from 100A to 600A, such control ensures sufficient etching accuracy while maintaining structural integrity and functionality. Especially in the production of high-precision chip packaging, a stop layer in this thickness range can effectively control the etching process, avoid damage to the underlying material, and ensure the precise opening of the through hole.

[0039] In the above scheme, the thickness of the stop layer 20 ranges from 100 Å to 600 Å, and the stop layer can effectively control the next step of oxide layer deposition and through silicon via etching process. This thickness range can ensure sufficient strength to withstand subsequent processing steps, and can also maintain sufficient flexibility to adapt to different design requirements. Proper selection of the thickness of the stop layer is a key factor in ensuring the accuracy and quality of chip packaging.

[0040] In one possible implementation, a stop layer is deposited before the first metal layer process on the bottom wafer.

[0041] In this embodiment, the deposition of the stop layer occurs before the first metal layer process of the bottom wafer. This arrangement helps to protect the integrity of the wafer in subsequent processes, while providing a stable and reliable foundation for the formation of the metal layer 10. This step plays a vital role in the entire packaging manufacturing process, especially in achieving high-precision and high-reliability 3D packaging structures.

[0042] In a possible implementation, the through silicon via 30 is formed by an ion etching process.

[0043] In this solution, the through silicon via 30 is formed by ion etching, which is an efficient method for precisely controlling the shape and depth of the through-hole. The ion etching process can provide highly controllable etching rate and accuracy, which is critical to the quality and consistency of the through silicon via. By finely adjusting the energy and direction of the ion beam, the shape and size of the through-hole can be precisely controlled, thereby ensuring that the performance of the through-hole meets the design requirements.

[0044] In a possible implementation manner, the depth of the through silicon via 30 is less than or equal to 100 um.

[0045] In this embodiment, the control of the TSV depth is critical to the performance of the entire package. TSVs with a depth of less than or equal to 100um help maintain the structural integrity and strength of the package, while also facilitating efficient thermal management and electrical signal transmission. This depth control ensures the stability and reliability of the chip during the packaging process, which is particularly critical for high-performance packaging applications.

[0046] In a possible implementation manner, the material of the stop layer 20 is silicon nitride or SiCN containing N element.

[0047] In this solution, silicon nitride SiN or silicon carbon nitride SiCN containing N element is selected as the stop layer material. These materials have excellent physical and chemical stability and can remain stable in high temperature and corrosive environments. The use of these materials improves the reliability and durability of the entire packaging process, especially in the face of complex manufacturing environments and harsh usage conditions.

[0048] In one possible implementation, the formation of through silicon vias is completed in the stack of the bottom wafer and the top wafer to achieve interconnection.

[0049] This implementation emphasizes the importance of TSVs in achieving interconnection between the bottom wafer and the top wafer. By forming TSVs during the stacking of the two wafers, efficient and high-density interconnection can be achieved, which is critical to improving the performance and reducing the size of the entire package. This interconnection technology is a key step in achieving high-performance 3D packaging, especially for high-performance logic chips that require high-density interconnection.

[0050] In a possible implementation, the method is used for logic process chips in 3D advanced packaging processes, wherein the top wafer process can cover all key nodes of logic chip processes (90nm to 7nm).

[0051] In this solution, the above packaging method is applicable to logic Logic process chips in 3D advanced packaging processes. This method can handle all key process nodes from 90nm to 7nm, showing extremely high flexibility and applicability. The application of this technology provides an effective packaging solution for high-performance, high-density logic chips, meeting the needs of current and future chip technology development.

[0052] According to another aspect of the present application, a chip is provided. In a possible implementation manner, the chip is manufactured by any of the above chip packaging manufacturing methods.

[0053] See also Figure 4 In the above scheme, the chip is deposited with a stop layer 20 on the bottom wafer of the upstream unit of the package, and the stop layer covers part or all of the metal layer 10; an oxide layer is deposited on the stop layer 20; a through silicon via 30 is opened through an etching process, and the through silicon via is placed above the metal layer 10, and the etching depth reaches the stop layer 20; the stop layer 20 is etched, and the etching depth reaches the metal layer 10, so that the through silicon via 30 accurately reaches the metal layer 10. Damage caused by excessive etching is avoided, the quality of the packaged product is guaranteed, and the yield rate is improved.

[0054] In the above solution, a shallow trench isolation (STI) structure 50 and a top metal layer 40 (TM) connected to the metal layer 10 are formed on the silicon substrate 60 .

[0055] In this scheme, the chip produced by any of the above chip packaging manufacturing methods has excellent performance and reliability. This chip can meet the strict requirements of modern electronic devices for high performance, high integration and low power consumption. The chip manufacturing method ensures the accuracy and quality of the packaging, providing a solid foundation for the performance of electronic devices.

[0056] Finally, it should be noted that: the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0057] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention is described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A chip packaging manufacturing method, characterized in that: The steps include: S10, depositing a stop layer on the bottom wafer of the upstream unit of the package before the first metal layer process of the bottom wafer; the thickness of the stop layer ranges from 100Å to 600Å; The material of the stop layer is silicon nitride or SiCN containing N element, and the deposition stop layer includes: S11, depositing a layer of silicon nitride precursor material on the bottom wafer using a chemical vapor deposition method; S12, thermally treating the silicon nitride precursor material to form a stop layer; S20, depositing an oxide layer on the stop layer; S30, opening a through silicon via by an ion etching process, wherein the depth of the through silicon via is less than or equal to 100 um, and the etching depth reaches the stop layer; S40, etching stop layer, the etching depth is to reach the metal layer; the etching stop layer adopts the plasma etching process, the power range of the plasma source is 800-1000w, the C4F8:O2 ratio is controlled to be ≤1:1, and the gas pressure is controlled at 50-80mt.

2. The chip packaging manufacturing method according to claim 1, characterized in that: Through Silicon Via formation is done in the stack of bottom and top wafers to achieve interconnection.

3. The chip packaging manufacturing method according to claim 1, characterized in that: This method is used for logic process chips in 3D packaging technology.

4. A chip, characterized in that: The chip packaging method is manufactured by any one of claims 1 to 3.

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