Heat dissipation structure of semiconductor device and preparation method thereof

Abstract

The embodiment of the present application provides a heat dissipation structure of a semiconductor device and a preparation method thereof, wherein the heat dissipation structure includes: a thermoelectric module, located on one side of the semiconductor device, the thermoelectric module is used to transfer the heat generated by the semiconductor device according to the thermoelectric effect; a heat sink structure, located on the side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module, the heat sink structure includes a substrate and a plurality of fins, wherein: the substrate is in contact with the thermoelectric module; the plurality of fins are distributed in multiple rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are staggered. Through this application, the problem of semiconductor devices lacking efficient heat dissipation technology to maintain the ambient temperature of the internal structure is solved, thereby achieving the effect of stabilizing the internal ambient temperature of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to a heat dissipation structure of a semiconductor device and a method for preparing the same. Background Art

[0002] Semiconductor devices constructed with three-dimensional (3D) packaging have obvious advantages over semiconductor devices constructed with traditional two-dimensional packaging. Three-dimensional integration does not depend on the characteristic size of the device and can be applied to any process node. Therefore, the integration of semiconductor devices can be linearly improved by using three dimensions.

[0003] However, while constructing semiconductor devices in three dimensions, the power density and the thermal resistance from the device to the environment are increased, thus significantly exacerbating heat accumulation. The main factor of failure and aging of electronic devices comes from thermal stress. Large-scale thermal cycles can cause plastic deformation of interconnections in IC chips and packages. Currently available cooling solutions include: traditional air-cooled heat sinks, thermal through-silicon via technology (TSV), microchannel heat dissipation, etc. Traditional air-cooled heat sinks install the heat sink at the top or bottom of the 3D stack and dissipate heat to the environment through convection. When these high-performance chips are stacked together, due to the dual factors of high heat generation and difficulty in heat dissipation, the traditional air heat dissipation method cannot meet the heat dissipation requirements. Thermal TSV has no electrical properties, and the sidewall material is usually made of silicon dioxide, which has limited heat dissipation efficiency. Microchannel heat dissipation technology has not yet been fully realized in engineering applications, and reliability issues need to be further studied. Therefore, there is a strong need for efficient cooling technology to maintain a relatively low and evenly distributed circuit temperature environment to achieve the best and reliable design and application of three-dimensional semiconductor devices. Summary of the invention

[0004] The embodiments of the present application provide a heat dissipation structure of a semiconductor device and a method for preparing the same, so as to at least solve the problem in the related art that semiconductor devices using three-dimensional construction lack efficient heat dissipation technology to maintain the ambient temperature of the internal structure.

[0005] According to one embodiment of the present application, a heat dissipation structure of a semiconductor device is provided, comprising: a thermoelectric module, located on one side of the semiconductor device, the thermoelectric module being used to transfer heat generated by the semiconductor device according to the thermoelectric effect; a heat sink structure, located on a side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module, the heat sink structure comprising a substrate and a plurality of fins, wherein: the substrate is in contact with the thermoelectric module; the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in an alternating manner.

[0006] In an exemplary embodiment, the length of the fin in the first direction is at least greater than the length of the fin in the second direction, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate.

[0007] In an exemplary embodiment, a ratio of a length of the fin in a third direction to a length of the fin in the first direction is 5.5-7, and the third direction is perpendicular to the substrate.

[0008] In an exemplary embodiment, the thermoelectric module includes: a plurality of first conductive layers, which are spaced apart and located on a side of the substrate away from the fins, the first conductive layer having a first surface on a side away from the substrate, the first conductive layer having opposite first and second ends in a second direction, the first surface having a first region near the first end, the first surface having a second region near the second end, a third region between the first region and the second region, the second direction being perpendicular to the first direction and parallel to the substrate, and the first direction being parallel to the substrate; a plurality of first type doped regions in contact with the first region; a plurality of second type doped regions in contact with the second region; a plurality of second conductive layers, which are located on a side of the first conductive layer away from the substrate, the second conductive layer being in contact with the first type doped regions and the second type doped regions on adjacent first conductive layers; an insulating layer, a portion of the insulating layer being located between the second conductive layer and the substrate, and another portion of the insulating layer being located in the third region and in contact with the second conductive layer.

[0009] In an exemplary embodiment, the thermoelectric module further includes: a first heat conducting layer located on a side of the substrate away from the fins; and a second heat conducting layer located on a side of the semiconductor device close to the second conductive layer.

[0010] In an exemplary embodiment, the heat dissipation structure also includes a heat conduction module, the heat conduction module includes multiple side surfaces, a first side surface has a recessed structure, the recessed structure is recessed toward a central area of ​​the heat conduction module, the first side surface is any side surface of the multiple side surfaces, and the recessed structure is used to place the semiconductor device.

[0011] In an exemplary embodiment, the heat conduction module has a plurality of the thermoelectric modules and a plurality of the heat sink structures on a plurality of the side surfaces other than the first side surface, the thermoelectric modules correspond to the heat sink structures one-to-one, and the side surfaces correspond to the thermoelectric modules one-to-one.

[0012] In an exemplary embodiment, the number of the fins is 50-100.

[0013] In an exemplary embodiment, the cross-sections of the fin in a first direction and a second direction include: a rectangle and a polygon, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate.

[0014] In an exemplary embodiment, the material of the fins includes a thermally conductive material.

[0015] According to another embodiment of the present application, a method for preparing a heat dissipation structure of a semiconductor device is provided, comprising:

[0016] A heat sink module is provided, wherein the heat sink structure comprises a substrate and a plurality of fins, wherein: the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in a staggered manner; and a thermoelectric module is formed on the substrate, and the thermoelectric module is used to transfer heat generated by the semiconductor device according to the thermoelectric effect.

[0017] In an exemplary embodiment, the preparation method includes: forming a plurality of first conductive layers distributed at intervals on the substrate, the plurality of first conductive layers having opposite first ends and second ends along a second direction, the first conductive layer having a first region near the first end, the first conductive layer having a second region near the second end, the second direction being perpendicular to the first direction and parallel to the substrate, and the first direction being parallel to the substrate; forming a thermoelectric layer on the substrate, the thermoelectric layer covering the first conductive layer; forming a plurality of first type doping regions and a plurality of second type doping regions in the thermoelectric layer, the first type doping regions and the second type doping regions being in contact with the same first conductive layer; forming a plurality of second conductive layers on the thermoelectric layer, the second conductive layers being located on a side of the first conductive layer away from the substrate, and the second conductive layers being in contact with adjacent first type doping regions and second type doping regions on adjacent first conductive layers.

[0018] In an exemplary embodiment, the step of forming the thermoelectric layer and the first conductive layer includes: sequentially forming a first conductive preparation layer and a thermoelectric preparation layer on a side of the substrate away from the fin; and performing a first patterning process on the first conductive preparation layer and the thermoelectric preparation layer to obtain a thermoelectric layer and a first conductive layer.

[0019] In an exemplary embodiment, a first ion implantation is performed into the thermoelectric layer located in the first region, and a second ion implantation is performed into the thermoelectric layer located in the second region to form a first type doping region and a second type doping region, the first type doping region and the second type doping region are located one by one on both sides of a first gap along the second direction, and the first gap is located between adjacent thermoelectric layers.

[0020] In an exemplary embodiment, after the step of forming multiple first-type doping regions and multiple second-type doping regions, the preparation method further includes: forming a first sub-insulating layer in the first gap; forming a second conductive preparation layer on the first sub-insulating layer, the second conductive preparation layer covering the first sub-insulating layer; performing a second patterning process on the second conductive preparation layer to form multiple second conductive layers, the second conductive layer covering the first sub-insulating layer; forming a second sub-insulating layer on the side of the first-type doping region and the second-type doping region away from the first sub-insulating layer, the first sub-insulating layer and the second sub-insulating layer forming the insulating layer.

[0021] In an exemplary embodiment, before the step of forming the first conductive layer, the preparation method further includes: depositing a first thermal conductive material on the substrate to form a first thermal conductive layer, and after the step of forming the first conductive layer, the first conductive layer is located on a side of the first thermal conductive layer facing away from the substrate.

[0022] In an exemplary embodiment, after the step of forming the insulating layer, the preparation method further comprises: depositing a second heat-conducting material on a side of the insulating layer facing away from the substrate to form a second heat-conducting layer.

[0023] Since the heat dissipation structure of the semiconductor device in the present application includes a thermoelectric module and a heat sink structure, the thermoelectric module uses the thermoelectric effect to quickly transfer the heat generated by the semiconductor device to the heat sink structure, realizing active heat dissipation from the semiconductor device to the heat sink structure; the heat sink module includes at least two rows of staggered fins, which increases the heat dissipation area of ​​the heat sink structure, realizes passive heat dissipation from the heat sink structure to the air, and then realizes efficient heat dissipation of the semiconductor device, which can effectively maintain the ambient temperature of the internal structure of the semiconductor device. Therefore, through this application, the problem of the lack of efficient heat dissipation technology to maintain the ambient temperature of the internal structure of the semiconductor device using three-dimensional construction in the related technology can be solved, and the purpose of stabilizing the internal ambient temperature of the semiconductor device using three-dimensional construction can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a partial cross-sectional structure of a heat dissipation structure of a semiconductor device according to an embodiment of the present application;

[0025] Figure 2 yes Figure 1 A schematic top view of a heat dissipation structure of a semiconductor device;

[0026] Figure 3 is a schematic diagram of a partial cross-sectional structure of another heat dissipation structure of a semiconductor device according to an embodiment of the present application;

[0027] Figure 4 is a schematic diagram of a partial cross-sectional structure of a heat dissipation structure of a multi-dimensional semiconductor device according to an embodiment of the present application;

[0028] Figure 5 is a schematic diagram of a partial cross-sectional structure of another heat dissipation structure of a multi-dimensional semiconductor device according to an embodiment of the present application;

[0029] Figure 6 yes Figure 4 or Figure 5 A schematic diagram of a partial bottom-up structure of a heat dissipation structure of a multi-dimensional semiconductor device;

[0030] Figure 7 It is a schematic flow chart of a method for preparing a heat dissipation structure of a semiconductor device according to an embodiment of the present application;

[0031] Figure 8 is Figure 7 In a method for preparing a heat dissipation structure of a semiconductor device, a schematic diagram of a cross-sectional structure of a substrate after providing a heat sink structure is provided;

[0032] Fig. 9 is Figure 8 A schematic diagram of a cross-sectional structure of a substrate after a first heat conducting layer, a first conductive preparation layer and a thermoelectric preparation layer are formed on the heat sink structure provided in the embodiment;

[0033] Fig.10 It will be Fig. 9 A schematic diagram of a cross-sectional structure of a substrate after the first conductive preparation layer and the thermoelectric preparation layer formed in the process are patterned to obtain the first conductive layer and the thermoelectric layer;

[0034] Fig.11 is Fig.10 A schematic diagram of a cross-sectional structure of a substrate after a first type doping layer and a second type doping layer are formed on the thermoelectric layer formed in the embodiment of the present invention;

[0035] Fig.12 It will be Fig.11 A schematic diagram of a cross-sectional structure of a substrate after a first sub-insulating layer is formed between the first type doped layer and the second type doped layer formed in the substrate, and a second conductive preparatory layer is formed on the first sub-insulating layer;

[0036] Fig.13 Yes Fig.12 The second conductive preparation layer formed in Fig.10 A schematic diagram of a cross-sectional structure of a substrate after patterning the thermoelectric layer formed in the process, removing the thermoelectric layer and forming a second conductive layer;

[0037] Fig.14 is Fig.13A schematic diagram of a cross-sectional structure of a substrate after a second sub-insulating layer is formed on both sides of the first type doped layer and the second type doped layer;

[0038] Fig.15 is Fig.13 Schematic diagram of the cross-sectional structure of the substrate after a second thermal conductive layer is formed on the second conductive layer formed in the embodiment of the present invention.

[0039] The above drawings include the following reference numerals:

[0040] 10. Semiconductor device; 20. Thermoelectric module; 21. First conductive layer; 210. First conductive preparation layer; 22. First type doping region; 23. Second type doping region; 24. Second conductive layer; 240. Second conductive preparation layer; 25. Insulating layer; 251. First sub-insulating layer; 252. Second sub-insulating layer; 26. First thermal conductive layer; 27. Second thermal conductive layer; 30. Heat sink structure; 31. Substrate; 32. Fins; 40. Thermal conduction module; 41. Thermoelectric layer; 410. Thermoelectric preparation layer. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0044] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0046] It should be noted that the drawings in the embodiments of the present invention are partial schematic diagrams, and only the areas involved in the device in the present application are used as illustrations. In addition, the illustrations provided in the present embodiment only illustrate the basic concept of the present application in an illustrative manner. Although the illustrations only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout form may also be more complicated.

[0047] In this embodiment, a heat dissipation structure of a semiconductor device is provided, such as Figure 1 and Figure 2 As shown, it includes: a thermoelectric module 20, located on one side of the semiconductor device 10, and the thermoelectric module 20 is used to transfer the heat generated by the semiconductor device 10 according to the thermoelectric effect; a heat sink structure 30, located on the side of the thermoelectric module 20 away from the semiconductor device 10, and in contact with the thermoelectric module 20, the heat sink structure 30 includes a substrate 31 and a plurality of fins 32, wherein: the substrate 31 is in contact with the thermoelectric module 20; the plurality of fins 32 are distributed in a plurality of rows on the substrate 31, the plurality of fins 32 in each row are distributed at intervals, and the fins 32 in at least two adjacent rows are distributed in an alternating manner.

[0048] Through the above embodiments, a thermoelectric module and a heat sink structure are arranged on the surface of the semiconductor device. When the temperature of the semiconductor device is too high, the thermoelectric module will trigger the thermoelectric effect, thereby actively conducting the heat of the semiconductor device. The heat conducted to the heat sink structure is passively dissipated into the air through the staggered fins, thereby keeping the temperature of the semiconductor structure stable.

[0049] In the above embodiment, Figure 1 As shown, a thermoelectric module 20 and a heat sink structure 30 are arranged on the semiconductor device 10, and the temperature of the semiconductor device 10 is transferred to the air in a gradient manner, such as Figure 2 As shown, the fins 32 in the heat sink structure 30 are on the substrate 31 , and the fins 32 between adjacent rows are staggered, thereby increasing the heat dissipation area between the fins 32 and achieving efficient heat dissipation of the semiconductor device 10 .

[0050] In one alternative, Figure 2 As shown, the length of the fin 32 in the first direction X is at least greater than the length of the fin 32 in the second direction Y. The second direction Y is perpendicular to the first direction X and parallel to the substrate 31 . The first direction X is parallel to the substrate 31 .

[0051] In the above embodiment, Figure 2As shown, the cross-section of the fin 32 in the direction along the heat sink structure pointing to the thermoelectric module is a rectangle, the cross-section has a length L in a first direction X parallel to the substrate 31, and has a width W in a direction perpendicular to the first direction X and parallel to the substrate 31, the length L of the cross-section of the fin 32 is at least greater than the width W, and the length relationship between the length L and the width W can maximize the surface area of ​​the cross-section of the fin 32, thereby improving the heat dissipation efficiency.

[0052] In one alternative, Figure 1 and Figure 2 As shown, the ratio of the length of the fin 32 in the third direction Z to the length of the fin 32 in the first direction X is 5.5-7, and the third direction Z is perpendicular to the substrate 31 .

[0053] In the above embodiment, the setting of the height H, length L and width W of the above-mentioned fins makes the fins have a larger Nusselt number, which can enhance the convective heat transfer capacity of the heat sink structure and improve the heat dissipation efficiency of the heat dissipation structure; the staggered fin-type fins further enhance the heat transfer, significantly improve the heat transfer effect by increasing the heat dissipation surface area and turbulence, and realize efficient passive heat dissipation.

[0054] In the above embodiment, Figure 1 and Figure 2 As shown, the fin 32 has a height H in the third direction Z perpendicular to the substrate 31, and the ratio of the height H to the length L in the first direction X can be 5.5-7. When the ratio of the height H to the length L is less than 5.5, the contact area between the heat sink structure 30 and the air is small, which reduces the heat dissipation efficiency; when the ratio of the height H to the length L exceeds 7, the height H of the fin 32 will be too high, resulting in poor mechanical strength. The second direction Y is perpendicular to the first direction X and the third direction Z, respectively.

[0055] In one alternative, Figure 3As shown, the thermoelectric module 20 includes: a plurality of first conductive layers 21, which are spaced apart and located on a side of the substrate 31 away from the fin 32, the first conductive layer 21 having a first surface on a side away from the substrate 31, the first conductive layer 21 having a first end and a second end opposite to each other in a second direction Y, the first surface having a first region near the first end, the first surface having a second region near the second end, and a third region between the first region and the second region, the second direction Y being perpendicular to the first direction X and parallel to the substrate 31, and the first direction X Parallel to the above-mentioned substrate 31; multiple first-type doping regions 22, in contact with the above-mentioned first area; multiple second-type doping regions 23, in contact with the above-mentioned second area; multiple second conductive layers 24, located on the side of the above-mentioned first conductive layer 21 away from the above-mentioned substrate 31, the above-mentioned second conductive layer 24 is in contact with the above-mentioned first-type doping regions 22 and the above-mentioned second-type doping regions 23 on the adjacent first conductive layer 21; insulating layer 25, a part of the above-mentioned insulating layer 25 is located between the above-mentioned second conductive layer 24 and the above-mentioned substrate 31, and another part of the above-mentioned insulating layer 25 is located in the above-mentioned third area and in contact with the above-mentioned second conductive layer 24.

[0056] In the above embodiment, Figure 3 As shown, the thermoelectric module 20 includes a first conductive layer 21, a first type doping region 22, a second type doping region 23, a second conductive layer 24 and an insulating layer 25. The first conductive layer 21 has a plurality of intervals located on the surface of the substrate 31 away from the fin 32, and has a first end and a second end opposite to each other in the second direction Y. The first surface has a first region and a second region in local regions near the first end and the second end, respectively. The first region and the second region have a first type doping region 22 and a second type doping region 23, respectively. The first type doping region 22 and the second type doping region 23 are in contact with the second conductive layer 24 on a side away from the first conductive layer 21. The second conductive layer 24 is located as a whole on a side away from the first type doping region 22 and the second type doping region 23. The second conductive layer 24 is located near the substrate 31. A second surface is provided on one side of the semiconductor device 10, and a second conductive layer 24 located near the edge of the semiconductor device 10 is only in contact with the first type doping region 22, or only in contact with the second type doping region 23, and the remaining second conductive layer 24 has two opposite ends in the second direction Y, and the above-mentioned second surface has a fourth region and a fifth region near the above-mentioned two ends, respectively, and the fourth region and the fifth region are in contact with the first type doping region 22 and the second type doping region 23, respectively; a portion of the insulating layer 25 is located between the second conductive layer 24 and the substrate 31, and another portion of the insulating layer 25 is located between the first type doping region 22 and the second type doping region 23, and is in contact with the first conductive layer 21 and the second conductive layer 24, respectively.

[0057] When the temperature of the semiconductor device rises, there is a temperature difference between the side of the thermoelectric module close to the semiconductor device and the side away from the semiconductor device, and an induced electromotive force is generated in the path in the thermoelectric module. The holes in the first doping type area will flow from the high-temperature side to the low-temperature side, flowing through the first conductive layer to the second doping type area. In this process, the heat of the semiconductor device is transferred from the second conductive layer to the first conductive layer, and the first conductive layer transfers the heat to the heat sink structure and then transfers the heat to the air.

[0058] In one alternative, Figure 3 As shown, the thermoelectric module 20 further includes: a first heat conducting layer 26 located on a side of the substrate 31 away from the fins 32 ; and a second heat conducting layer 27 located on a side of the semiconductor device 10 close to the second conductive layer 24 .

[0059] In the above embodiment, Figure 3 As shown, during the process of the thermoelectric module 20 conducting the temperature of the semiconductor device 10, the semiconductor device 10 is in direct contact with the first heat-conducting layer 26 of the thermoelectric module 20, and the first heat-conducting layer 26 transfers the heat to the inside of the thermoelectric module 20. The thermoelectric module 20 transfers the above heat to the heat sink structure 30 through the second heat-conducting layer 27, and the second heat-conducting layer 27 is in direct contact with the substrate 31 of the heat sink structure 30. The first heat-conducting layer 26 and the second heat-conducting layer 27 improve the efficiency of heat transfer of the semiconductor device. The materials of the first heat-conducting layer and the second heat-conducting layer can be any one or more of graphite, ceramics and polystyrene, and this application does not make specific limitations.

[0060] In one alternative, Figures 4 to 6 As shown, the heat dissipation structure further includes a heat conduction module, which includes a plurality of side surfaces, a first side surface having a recessed structure, the recessed structure being recessed toward a central area of ​​the heat conduction module, the first side surface being any side surface of the plurality of side surfaces, and the recessed structure being used to place the semiconductor device 10.

[0061] In one alternative, Figures 4 to 6 As shown, the heat conduction module has a plurality of the thermoelectric modules 20 and a plurality of the heat sink structures 30 on a plurality of the side surfaces other than the first side surface, the thermoelectric modules 20 correspond one-to-one to the heat sink structures 30, and the side surfaces correspond one-to-one to the thermoelectric modules 20.

[0062] In the above embodiment, Figure 4 As shown, in the perspective of the first coordinate system, the four surfaces of the heat conduction module are provided with thermoelectric modules 20 and heat sink structures 30, wherein due to the different ways in which the heat dissipation structures are placed on the heat conduction module, Figure 4The thermoelectric module 20 and the heat sink structure 30 are presented at different angles. The placement method can be adjusted according to the actual situation and is not specifically limited. The perspective of the first coordinate system is: the first direction X points to the inside of the paper, the second direction Y points to the right, and the third direction Z points upward. Figure 5 As shown, in the perspective of the second coordinate system, the thermoelectric modules 20 and the heat sink structure 30 are arranged on the four surfaces of the heat conduction module, and the perspective of the second coordinate system is: the first direction X points to the right, the second direction Y points outside the paper, and the third direction Z points upward. The material of the above-mentioned heat conduction module can be any one or more of graphite, ceramic and polystyrene, and this application does not make specific limitations.

[0063] like Figure 6 As shown, Figure 6 for Figure 4 or Figure 5 It is important to note that Figure 6 The bottom surface of the heat conduction module 40 is not provided with the thermoelectric module 20 and the heat sink structure 30, and can be bonded with other supporting structures. Figure 6 In the figure, the first direction X points to the right, the second direction Y points upward, and the third direction Z points into the paper, the only difference is the viewing angle. Figure 4 and Figure 5 The thermoelectric module 20 and the heat sink structure 30 on the heat conduction module are not necessarily placed at the same angle. Figure 4 The fins on the left and right sides shown in the figure are widths, but they can also be shown as lengths. Figure 4 and Figure 5 This is just an illustration, and there may be other configurations. Figures 4 to 6 The fin cross section is shown in only one row or column.

[0064] In an optional solution, the number of the fins is 50 to 100; the material of the fins includes a thermal conductive material.

[0065] In the above embodiment, the number of fins distributed on the substrate can be 50 to 100, and the materials of the fins and the substrate can be materials with high thermal conductivity such as aluminum and copper. The number of fins distributed and the materials of the fins and the substrate can be reasonably selected according to actual conditions, and this application does not make any specific limitations.

[0066] In an optional solution, the cross-sections of the fins in the first direction and the second direction include: rectangles and polygons, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate.

[0067] In the above embodiment, the cross-section of the fin in the direction from the heat sink structure to the thermoelectric module can be rectangular or polygonal. The cross-sectional shape of the fin can be reasonably selected according to actual conditions, and this application does not make any specific limitation.

[0068] In an embodiment of the present application, thermoelectric modules and heat sink structures can be provided on the five surfaces of the heat conduction module. The heat conduction module conducts the heat of the semiconductor device to the thermoelectric module, and the thermoelectric module cools the heat conduction module. The combination of the thermoelectric module and the heat sink structure enhances the heat dissipation performance of the heat dissipation structure.

[0069] In this embodiment, a method for preparing the heat dissipation structure of the semiconductor device is provided. Figure 7 is a flow chart of a method for preparing the heat dissipation structure of the semiconductor device according to an embodiment of the present application, such as Figure 7 As shown, the process includes the following steps:

[0070] Step S102, providing a heat sink module, wherein the heat sink structure comprises a substrate and a plurality of fins, wherein: the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in a staggered manner;

[0071] Step S104 , forming a thermoelectric module on the substrate, wherein the thermoelectric module is used to transfer heat generated by the semiconductor device according to the thermoelectric effect.

[0072] Through the above steps, the provided heat sink structure has staggered fins between adjacent rows, the staggered distribution increases the heat dissipation area of ​​the fins and the turbulence has excellent heat transfer effect, and a thermoelectric module is prepared on the substrate of the heat sink structure. The thermoelectric module actively transfers the heat of the semiconductor device to the heat sink structure, and the heat sink structure passively dissipates the heat through the staggered fins, further solving the problem in the related art that semiconductor devices using three-dimensional construction lack efficient heat dissipation technology to maintain the ambient temperature of the internal structure, thereby improving the heat dissipation efficiency of the heat dissipation structure.

[0073] The exemplary embodiments of the method for preparing the heat dissipation structure of the semiconductor device provided by the present application will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0074] First, perform the above step S102, such as Figure 8 As shown, a heat sink structure 30 is provided, and the heat sink structure 30 includes a substrate 31 and a plurality of fins 32, wherein: the plurality of fins 32 are distributed in a plurality of rows along a first direction on the substrate 31, the plurality of fins 32 in each row are distributed at intervals, and the fins 32 in at least two adjacent rows are distributed in an alternating manner, and the first direction is parallel to the substrate 31.

[0075] Specifically, the materials of the substrate and fins of the heat sink module can be materials with high heat dissipation efficiency such as aluminum and copper. The fins are arranged on the substrate in a staggered distribution type to increase the heat dissipation area of ​​the heat sink module.

[0076] After the step of providing the heat sink module is performed, step S104 is performed to form a thermoelectric module on the substrate, wherein the thermoelectric module is used to transfer the heat generated by the semiconductor device according to the thermoelectric effect.

[0077] In an optional solution, the step of forming a thermoelectric module on a substrate includes: Figures 9 to 13 As shown, a plurality of first conductive layers 21 distributed at intervals are formed on the substrate 31, the plurality of first conductive layers 21 have opposite first ends and second ends along the second direction Y, the first conductive layer 21 has a first region near the first end, the first conductive layer 21 has a second region near the second end, the second direction Y is perpendicular to the first direction and parallel to the substrate 31, and the first direction is parallel to the substrate 31; a thermoelectric layer 41 is formed on the substrate 31, the thermoelectric layer 41 covers the first conductive layer 21; a plurality of first type doping regions 22 and a plurality of second type doping regions 23 are formed in the thermoelectric layer 41, the first type doping regions 22 and the second type doping regions 23 are in contact with the same first conductive layer 21; a plurality of second conductive layers 24 are formed on the thermoelectric layer 41, the second conductive layers 24 are located on the side of the first conductive layer 21 away from the substrate 31, and the second conductive layers 24 are in contact with adjacent first type doping regions 22 and second type doping regions 23 on adjacent first conductive layers 21.

[0078] In the above embodiment, Figures 9 to 11 As shown, the substrate 31 is first planarized, and a plurality of spaced first conductive layers 21 and a plurality of spaced thermoelectric layers 41 are formed on the substrate 31. The plurality of first conductive layers 21 and the plurality of thermoelectric layers 41 are arranged along the second direction Y. A first type doping region 22 and a second type doping region 23 are formed in the thermoelectric layer 41. The first type doping region 22 contacts the first region of the first conductive layer 21, and the second type doping region 23 contacts the second region of the first conductive layer 21.

[0079] In one alternative, Fig. 9 As shown, before the step of forming the first conductive layer, the preparation method further includes: depositing a first thermal conductive material on the substrate 31 to form a first thermal conductive layer 26, such as Fig.10 As shown, after the step of forming the first conductive layer 21 , the first conductive layer 21 is located on the side of the first heat conductive layer 26 facing away from the substrate 31 .

[0080] In the above embodiment, the material of the first thermal conductive layer can be silicon dioxide, with a thickness of 10-40 nm, and the growth method can be any one of physical vapor deposition process, chemical vapor deposition process and electroplating, which is not specifically limited in this application. The material of the first conductive layer can be copper, aluminum and silicide, etc., with a thickness of 50 nm-1000 nm, and the growth method can be any one of magnetron sputtering and electroplating, and the material, thickness and growth method of the first conductive layer are not specifically limited in this application.

[0081] In one alternative, Figures 9 and 10 As shown, the steps of forming the above-mentioned thermoelectric layer 41 and the above-mentioned first conductive layer 21 include: sequentially forming a first conductive preparation layer 210 and a thermoelectric preparation layer 410 on the side of the above-mentioned substrate 31 away from the above-mentioned fins 32; performing a first patterning process on the above-mentioned first conductive preparation layer 210 and the above-mentioned thermoelectric preparation layer 410 to obtain the thermoelectric layer 41 and the first conductive layer 21.

[0082] In the above embodiment, Fig. 9 As shown, the first conductive preparation layer 210 and the above-mentioned thermoelectric preparation layer 410 are sequentially formed on the first thermal conductive layer 26. Fig.10 As shown, the first conductive preparation layer and the thermoelectric preparation layer are subjected to a first patterning process to form a plurality of grooves in the first conductive preparation layer and the thermoelectric preparation layer, thereby obtaining a first conductive layer 21 and a thermoelectric layer 41 .

[0083] In one alternative, Fig.11 As shown, the steps of forming multiple first-type doping regions 22 and multiple second-type doping regions 23 include: performing a first ion implantation into the thermoelectric layer 41 located in the first region, and performing a second ion implantation into the thermoelectric layer 41 located in the second region to form first-type doping regions 22 and second-type doping regions 23, wherein the first-type doping regions 22 and the second-type doping regions 23 are located one-to-one on both sides of the first gap along the second direction Y, and the first gap is located between adjacent thermoelectric layers 41.

[0084] In the above embodiment, Fig.11 As shown, on both sides of the groove are specific areas of thermoelectric material, into which different types of doping ions are respectively injected to form a first type doping area 22 and a second type doping area 23.

[0085] In the above embodiment, ion implantation is used to implant N-type and P-type doping ions into specific areas of the thermoelectric material, and the implantation dose is 1e 19 cm -2 ~1e 20 cm -2The injection energy is 50~1000keV, and the thermoelectric material includes any one or more of polysilicon, SiGe, Be2Te3, GeBiTe, PbTe, diamond and SiC, but is not limited to the above types, and this application does not make specific limitations.

[0086] In one alternative, Figures 12 to 15 As shown, after the step of forming multiple first-type doping regions 22 and multiple second-type doping regions 23, the preparation method also includes: forming a first sub-insulating layer 251 in the above-mentioned first gap; forming a second conductive preparation layer 240 on the above-mentioned first sub-insulating layer 251, and the above-mentioned second conductive preparation layer 240 covers the above-mentioned first sub-insulating layer 251; performing a second patterning treatment on the above-mentioned second conductive preparation layer 240 to form multiple second conductive layers 24, and the above-mentioned second conductive layer 24 covers the above-mentioned first sub-insulating layer 251; forming a second sub-insulating layer 252 on the side of the above-mentioned first-type doping region 22 and the above-mentioned second-type doping region 23 away from the above-mentioned first sub-insulating layer 251, and the above-mentioned first sub-insulating layer 251 and the above-mentioned second sub-insulating layer 252 form the above-mentioned insulating layer 25.

[0087] In the above embodiment, Fig.12 As shown, a first sub-insulating layer 251 is formed in the groove, and a planarization process is performed, and a second conductive preparatory layer 240 is formed on the first sub-insulating layer 251, as shown in FIG. Fig.13 As shown, the second conductive preparation layer and the thermoelectric layer are patterned, and the thermoelectric layer is removed to form a second conductive layer 24, as shown in FIG. Fig.14 As shown, a second sub-insulating layer 252 is formed on the side of the first type doping region 22 away from the first sub-insulating layer 251 and on the side of the second type doping region 23 away from the first sub-insulating layer 251 , and the first sub-insulating layer 251 and the second sub-insulating layer 252 form the insulating layer 25 .

[0088] In one alternative, Fig.15 As shown, after the step of forming the above-mentioned insulating layer, the above-mentioned preparation method further includes: depositing a second heat-conducting material on a side of the above-mentioned insulating layer away from the above-mentioned substrate 31 to form a second heat-conducting layer 27.

[0089] In the above embodiment, Fig.15 As shown, a second heat conducting layer 27 is formed on the second sub-insulating layer 252 and the second conductive layer 24 .

[0090] In the above embodiment, the material of the second thermal conductive layer can be silicon dioxide with a thickness of 10-40 nm, and the growth method can be any one of physical vapor deposition process, chemical vapor deposition process and electroplating, which is not specifically limited in this application.

[0091] It should be noted that Figures 9 to 15All structures not mentioned in the description are related to Figure 1 The structural description is consistent with that in , and no repetition is made.

[0092] Exemplarily, a mask is coated on the surface of the thermoelectric preparation layer, and the thermoelectric preparation layer is etched by reactive ion etching (RIE) until a groove is formed in the first thermal conductive layer to form a thermoelectric layer and a first conductive layer; a first sub-insulating layer is grown in the groove to fill the groove, and then the first sub-insulating layer is planarized by chemical mechanical polishing. The insulating layer material is generally a low thermal conductivity material, including but not limited to any one or more of SiO2, SiOH, porous ultra-low dielectric constant materials and air bridges.

[0093] It should be noted that the above-mentioned semiconductor devices include three-dimensional integrated circuits, which may include different chip types. The chips can not only be stacked vertically but also arranged horizontally. The preparation of three-dimensional integrated circuits is completed according to standard chip manufacturing processes, the vertical stacking of different chips is achieved through a bonding process, and the electrical connection between layers is achieved through silicon vias.

[0094] In the above embodiment, the three-dimensional integrated circuit can also be combined with the back of the thermoelectric module through a bonding process, and the prepared three-dimensional integrated circuit surface and the back of the thermoelectric module are surface treated to remove surface impurities; the three-dimensional integrated circuit is bonded to the thermoelectric module to achieve the combination of the two. The bonding process can adopt traditional metal bonding, and the bonding metal material can be a material with high thermal conductivity and good plasticity, such as Au and Cu. A certain temperature and a certain bonding pressure are applied to the bonding material to achieve bonding; the bonding process can also be achieved by surface activation bonding, that is, nitrogen or oxygen is used to activate the surface of the three-dimensional integrated circuit and the back of the thermoelectric module, and the activated three-dimensional integrated circuit surface and the back of the thermoelectric module are aligned and bonded, and annealing treatment is performed.

[0095] The heat dissipation structure of the semiconductor device and the preparation method thereof of the present application will be specifically described below in combination with specific embodiments and comparative examples.

[0096] Example 1

[0097] The heat dissipation structure of semiconductor devices includes:

[0098] A thermoelectric module is located on one side of a semiconductor device, and the thermoelectric module comprises: a plurality of first conductive layers, a plurality of first type doped regions, a plurality of second type doped regions, a plurality of second conductive layers, an insulating layer, a first heat conducting layer and a second heat conducting layer, wherein the plurality of first conductive layers are spaced apart and located on a side of the substrate away from the fins, the first conductive layer has a first surface on a side away from the substrate, the first conductive layer has a first end and a second end opposite to each other in a second direction, the first surface has a first region near the first end, the first surface has a second region near the second end, a third region is between the first region and the second region, and the second direction is parallel to the first region. The direction is perpendicular and parallel to the substrate, and the first direction is parallel to the substrate; multiple first-type doped regions are in contact with the first region; multiple second-type doped regions are in contact with the second region; multiple second conductive layers are located on the side of the first conductive layer away from the substrate, and the second conductive layer is in contact with the first-type doped regions and the second-type doped regions on the adjacent first conductive layer; a portion of the insulating layer is located between the second conductive layer and the substrate, and another portion of the insulating layer is in contact with the third region and the second conductive layer, and the first thermal conductive layer is located on the side of the substrate away from the fin; the second thermal conductive layer is located on the side of the semiconductor device close to the second conductive layer. The thickness of the first conductive layer and the second conductive layer are both 100nm, and the material is aluminum. The injection dosage of the first-type doped region is 1e 19 cm -2 The injected material is SiGe, and the injection amount of the second type doping area is 1e 19 cm -2 The injected material is PbTe, the thickness of the insulating layer is 400nm, the material is SiO2, the thickness of the first thermal conductive layer and the second thermal conductive layer are both 30nm, and the material is SiO2.

[0099] The heat sink structure is located on the side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module. The heat sink structure includes a substrate and a plurality of fins, wherein: the substrate is in contact with the thermoelectric module; the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in an alternating manner. The substrate is made of copper with a thickness of 5nm, the fins are made of copper, the number is 60, the length:width ratio is 2, and the height:length ratio is 5.5.

[0100] Example 2

[0101] The heat dissipation structure of semiconductor devices includes:

[0102] A thermoelectric module is located on one side of a semiconductor device, and the thermoelectric module comprises: a plurality of first conductive layers, a plurality of first type doped regions, a plurality of second type doped regions, a plurality of second conductive layers, an insulating layer, a first heat conducting layer and a second heat conducting layer, wherein the plurality of first conductive layers are spaced apart and located on a side of the substrate away from the fins, the first conductive layer has a first surface on a side away from the substrate, the first conductive layer has a first end and a second end opposite to each other in a second direction, the first surface has a first region near the first end, the first surface has a second region near the second end, a third region is between the first region and the second region, and the second direction is parallel to the first region. The direction is perpendicular and parallel to the substrate, and the first direction is parallel to the substrate; multiple first-type doped regions are in contact with the first region; multiple second-type doped regions are in contact with the second region; multiple second conductive layers are located on the side of the first conductive layer away from the substrate, and the second conductive layer is in contact with the first-type doped regions and the second-type doped regions on the adjacent first conductive layer; a portion of the insulating layer is located between the second conductive layer and the substrate, and another portion of the insulating layer is in contact with the third region and the second conductive layer, and the first thermal conductive layer is located on the side of the substrate away from the fin; the second thermal conductive layer is located on the side of the semiconductor device close to the second conductive layer. The thickness of the first conductive layer and the second conductive layer are both 100nm, and the material is aluminum. The injection dosage of the first-type doped region is 1e 19 cm -2 The injected material is SiGe, and the injection amount of the second type doping area is 1e 19 cm -2 The injected material is PbTe, the thickness of the insulating layer is 400nm, the material is SiO2, the thickness of the first thermal conductive layer and the second thermal conductive layer are both 30nm, and the material is SiO2.

[0103] The heat sink structure is located on the side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module. The heat sink structure includes a substrate and a plurality of fins, wherein: the substrate is in contact with the thermoelectric module; the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in an alternating manner. The substrate is made of copper with a thickness of 5nm, the fins are made of copper, the number is 60, the length:width ratio is 2, and the height:length ratio is 6.

[0104] Example 3

[0105] The heat dissipation structure of semiconductor devices includes:

[0106] A thermoelectric module is located on one side of a semiconductor device, and the thermoelectric module comprises: a plurality of first conductive layers, a plurality of first type doped regions, a plurality of second type doped regions, a plurality of second conductive layers, an insulating layer, a first heat conducting layer and a second heat conducting layer, wherein the plurality of first conductive layers are spaced apart and located on a side of the substrate away from the fins, the first conductive layer has a first surface on a side away from the substrate, the first conductive layer has a first end and a second end opposite to each other in a second direction, the first surface has a first region near the first end, the first surface has a second region near the second end, a third region is between the first region and the second region, and the second direction is parallel to the first region. The direction is perpendicular and parallel to the substrate, and the first direction is parallel to the substrate; multiple first-type doped regions are in contact with the first region; multiple second-type doped regions are in contact with the second region; multiple second conductive layers are located on the side of the first conductive layer away from the substrate, and the second conductive layer is in contact with the first-type doped regions and the second-type doped regions on the adjacent first conductive layer; a portion of the insulating layer is located between the second conductive layer and the substrate, and another portion of the insulating layer is in contact with the third region and the second conductive layer, and the first thermal conductive layer is located on the side of the substrate away from the fin; the second thermal conductive layer is located on the side of the semiconductor device close to the second conductive layer. The thickness of the first conductive layer and the second conductive layer are both 100nm, and the material is aluminum. The injection dosage of the first-type doped region is 1e 19 cm -2 The injected material is SiGe, and the injection amount of the second type doping area is 1e 19 cm -2 The injected material is PbTe, the thickness of the insulating layer is 400nm, the material is SiO2, the thickness of the first thermal conductive layer and the second thermal conductive layer are both 30nm, and the material is SiO2.

[0107] The heat sink structure is located on the side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module. The heat sink structure includes a substrate and a plurality of fins, wherein: the substrate is in contact with the thermoelectric module; the plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in an alternating manner. The substrate is made of copper with a thickness of 5nm, the fins are made of copper, the number is 60, the length:width ratio is 2, and the height:length ratio is 7.

[0108] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the above methods of each embodiment of the present application.

[0109] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a heat dissipation structure of a semiconductor device, characterized in that: include: A heat sink structure is provided, the heat sink structure comprising a base plate and a plurality of fins, wherein: The plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in a staggered manner; forming a thermoelectric module on the substrate, wherein the thermoelectric module is used to transfer heat generated by the semiconductor device according to the thermoelectric effect; The preparation method comprises: forming a first conductive preparation layer and a thermoelectric preparation layer in sequence on a side of the substrate away from the fin; performing a first patterning process on the thermoelectric preparation layer and the first conductive preparation layer in sequence to obtain a first gap, a plurality of spaced-apart thermoelectric layers and a stack of first conductive layers, wherein the first gap is located between stacks of adjacent thermoelectric layers and first conductive layers; a plurality of first conductive layers have opposite first ends and second ends along a second direction, the first conductive layer has a first region near the first end, the first conductive layer has a second region near the second end, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate; forming a plurality of first-type doping regions and a plurality of second-type doping regions in the thermoelectric layer. doped regions, the first type doped regions and the second type doped regions are in contact with the same first conductive layer; the steps of forming a plurality of first type doped regions and a plurality of second type doped regions include: performing a first ion implantation into the thermoelectric layer located in the first region, and performing a second ion implantation into the thermoelectric layer located in the second region to form the first type doped regions and the second type doped regions, the first type doped regions and the second type doped regions being located one-to-one on both sides of the first gap along the second direction; forming a plurality of second conductive layers on the thermoelectric layer, the second conductive layers being located on a side of the first conductive layer away from the substrate, and the second conductive layers being in contact with adjacent first type doped regions and second type doped regions on adjacent first conductive layers.

2. The preparation method according to claim 1, characterized in that: After the step of forming a plurality of first-type doping regions and a plurality of second-type doping regions, the preparation method further comprises: forming a first sub-insulating layer in the first gap; forming a second conductive preparation layer on the first sub-insulating layer, wherein the second conductive preparation layer covers the first sub-insulating layer; performing a second patterning process on the second conductive preparation layer to form a plurality of second conductive layers, wherein the second conductive layers cover the first sub-insulating layer; A second sub-insulating layer is formed on a side of the first type doping region and the second type doping region away from the first sub-insulating layer, and the first sub-insulating layer and the second sub-insulating layer form the insulating layer.

3. The preparation method according to claim 1, characterized in that: Before the step of forming the first conductive layer, the preparation method further comprises: A first heat-conducting material is deposited on the substrate to form a first heat-conducting layer. After the step of forming the first conductive layer, the first conductive layer is located on a side of the first heat-conducting layer away from the substrate.

4. The preparation method according to claim 2, characterized in that: After the step of forming the insulating layer, the preparation method further comprises: A second heat-conducting material is deposited on a side of the insulating layer facing away from the substrate to form a second heat-conducting layer.

5. A heat dissipation structure of a semiconductor device prepared by the preparation method according to any one of claims 1 to 4, characterized in that: include: A thermoelectric module is located on one side of the semiconductor device, and is used to transfer heat generated by the semiconductor device according to the thermoelectric effect; A heat sink structure is located on a side of the thermoelectric module away from the semiconductor device and in contact with the thermoelectric module, the heat sink structure comprising a substrate and a plurality of fins, wherein: The substrate is in contact with the thermoelectric module; The plurality of fins are distributed in a plurality of rows on the substrate, the plurality of fins in each row are distributed at intervals, and the fins in at least two adjacent rows are distributed in a staggered manner.

6. The heat dissipation structure according to claim 5, characterized in that: The length of the fin in the first direction is at least greater than the length of the fin in the second direction, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate.

7. The heat dissipation structure according to claim 6, characterized in that: The ratio of the length of the fin in the third direction to the length of the fin in the first direction is 5.5-7, and the third direction is perpendicular to the substrate.

8. The heat dissipation structure according to claim 5, characterized in that: The thermoelectric module comprises: A plurality of first conductive layers are spaced apart and located on a side of the substrate away from the fin, the first conductive layer having a first surface on the side away from the substrate, the first conductive layer having a first end and a second end opposite to each other in a second direction, the first surface having a first area near the first end, the first surface having a second area near the second end, and a third area between the first area and the second area, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate; a plurality of first type doped regions, contacting the first region; a plurality of second type doped regions, contacting the second region; A plurality of second conductive layers, located on a side of the first conductive layer away from the substrate, wherein the second conductive layers are in contact with the first type doped regions and the second type doped regions on adjacent first conductive layers; An insulating layer, a portion of the insulating layer is located between the second conductive layer and the substrate, and another portion of the insulating layer is located in the third region and in contact with the second conductive layer.

9. The heat dissipation structure according to claim 8, characterized in that: The thermoelectric module further comprises: A first heat-conducting layer, located on a side of the substrate facing away from the fins; The second heat-conducting layer is located on a side of the semiconductor device close to the second conductive layer.

10. The heat dissipation structure according to claim 9, characterized in that: The heat dissipation structure also includes a heat conduction module, which includes multiple side surfaces, and a recessed structure in a first side surface, wherein the recessed structure is recessed toward a central area of ​​the heat conduction module, the first side surface is any side surface of the multiple side surfaces, and the recessed structure is used to place the semiconductor device.

11. The heat dissipation structure according to claim 10, characterized in that: The heat conduction module has a plurality of the thermoelectric modules and a plurality of the heat sink structures on a plurality of the side surfaces other than the first side surface, the thermoelectric modules correspond to the heat sink structures one by one, and the side surfaces correspond to the thermoelectric modules one by one.

12. The heat dissipation structure according to claim 5, characterized in that: The number of the fins is 50 to 100.

13. The heat dissipation structure according to claim 5, characterized in that: The cross-section of the fin in the first direction and the second direction includes a rectangle, the second direction is perpendicular to the first direction and parallel to the substrate, and the first direction is parallel to the substrate.

14. The heat dissipation structure according to claim 5, characterized in that: The material of the fins includes a thermally conductive material.

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