Approximate adder tree design method, adder tree circuit structure and chip

Abstract

The invention discloses an approximate adder tree design method, an adder tree circuit structure and a chip, and relates to the field of chip technology. Specifically, the method comprises performing preliminary approximate operations on input data by sequentially and alternately setting an OR circuit structure and an OR and AND circuit structure; in the second layer, an OR adder structure for retaining the carry result of the first layer and performing an OR operation with the result of the current layer and a half adder, OR and AND adder structure for performing a half adder, OR and AND operation on the result of the previous layer are alternately provided; in the third layer to the penultimate layer, a half adder, a full adder, a half adder, an OR structure and a half adder, a full adder, an OR and AND structure are alternately provided, and the corresponding two structures in the same layer are alternately arranged; in the last layer of the adder, a half adder, a full adder, a half adder, an OR structure are used to complete the final summation operation, so as to reduce the area and power consumption overhead of the calculation in the digital memory.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an approximate adder tree design method, an adder tree circuit structure and a chip. Background Art

[0002] In recent years, deep neural network-based reasoning has gained a lot of research attention due to its unprecedented accuracy in a range of cognitive tasks such as image classification, object detection, speech recognition, and language processing. However, due to the large-scale multiplication and accumulation operations in deep neural networks, computer systems face new problems related to data-centric computing as the network size grows rapidly. The traditional von Neumann architecture separates the processing and storage of data, and with the adoption of data-centric computing such as machine learning, data transmission between the two physically separated units becomes increasingly expensive, dominating the overall latency and energy consumption.

[0003] At present, in order to meet the high parallelism requirements of multiplication and accumulation operations, a variety of suitable AI accelerators have been proposed to cooperate with traditional processing units (CPU or GPU). Although these accelerators optimize data flow, the memory wall bottleneck caused by the separation of computing units and memory units still exists, resulting in huge power consumption and additional area overhead.

[0004] In the past decade, in-memory computing, which processes and stores data at the same location, has been shown to be a promising approach to reduce the data movement required for high-throughput multiplication and accumulation operations, provide high bandwidth, and meet the high parallelism requirements of multiplication and accumulation operations. According to the paradigm of data encoding and processing, in-memory computing is mainly divided into analog in-memory computing that uses Kirchhoff's laws to perform calculations and digital in-memory computing that uses all-digital circuits to perform calculations. Among them, analog in-memory computing has low overhead such as area and power consumption, high energy efficiency, but is easily affected by temperature, voltage, etc., and has low precision. It is suitable for application scenarios that require low power consumption and do not require high precision. In contrast, digital in-memory computing has low error, high precision, and better robustness, and can avoid inaccuracies caused by process variations, data conversion overhead, and poor scalability of analog circuits. However, digital in-memory computing has high power consumption per unit area, and has encountered new problems in terms of power and area. For example, a CMOS full adder unit requires 28 transistors, and the area and power consumption overhead are relatively large. It is only suitable for application scenarios with high precision and low requirements on power consumption.

[0005] Therefore, how to reduce the area and power consumption of digital memory chip calculations has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The main purpose of the present invention is to provide an approximate adder tree design method, an adder tree circuit structure and a chip, aiming to reduce the area and power consumption of digital in-memory calculations.

[0007] In order to achieve the above object, the present invention proposes an approximate adder tree design method for performing addition operations in digital signal processing, comprising the following steps:

[0008] S10: in the first layer of the adder tree, performing a preliminary approximate operation on the input data by alternately setting the OR circuit structure and the OR and AND circuit structure in sequence;

[0009] S20: In the second layer of the adder tree, a high-order retaining or adding structure for retaining the carry result of the first layer and performing an OR operation with the result of the current layer and a half adder or or adding structure for performing a half adder or or and operation on the result of the previous layer are alternately provided;

[0010] S30: In the third layer to the second to last layer of the adder, half adders, full adders, half adders, or structures and half adders, full adders, or, and structures are alternately arranged, and the corresponding two structures are alternately arranged in the same layer;

[0011] S40: In the last layer of the adder, a half adder, a full adder, a half adder, or a structure is used to complete the final summation operation and output an approximate result to reduce the area and power consumption of the calculation in the digital memory.

[0012] In one embodiment of the present application, the OR and AND circuit structure includes:

[0013] Two input terminals, respectively used to receive 1-bit numbers to be added;

[0014] An OR gate, connected to two input terminals, for summing two input 1-bit numbers; and

[0015] An AND gate, connected to two input terminals, is used to determine whether two 1-bit numbers have a carry.

[0016] In one embodiment of the present application, the half adder, full adder, half adder, or structure includes a half adder, a full adder, a half adder, and an OR gate arranged in sequence; wherein the number of full adders is equal to the level of the current half adder, full adder, half adder, or structure minus three.

[0017] In one embodiment of the present application, the half adder, full adder, or, and structure includes a half adder, a full adder, and an or, and gate arranged in sequence; wherein the number of full adders is equal to the level of the current half adder, full adder, or, and structure minus two.

[0018] The present application also discloses an adder tree circuit structure, which is produced by using any of the above-mentioned approximate adder tree design methods.

[0019] The present application also discloses a chip, comprising the adder tree circuit structure as described above.

[0020] With the above technical solution, the traditional half adder has 14 transistors, while the OR circuit structure in the present application has 4 transistors, and the OR and AND circuit structure has 8 transistors. When the OR circuit structure and the OR and AND circuit structure are alternately arranged, there are only 6 transistors on average, which is 8 transistors less than the traditional half adder. Therefore, the number of transistors is reduced, and the area and power consumption are reduced. The traditional half adder outputs 2 bits, the approximate half adder structure 1 outputs 1 bit, and the approximate half adder structure 2 outputs 2 bits, and the number of data bits output is also reduced. Therefore, by using two approximate half adder structures alternately, the number of data bits is reduced, and the calculation process is further simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0022] Figure 1 This is a schematic diagram of the process structure of the first embodiment of the present invention;

[0023] Figure 2 It is a schematic diagram of the approximate adder tree structure;

[0024] Figure 3 It is a schematic diagram of the approximate half adder structure;

[0025] Figure 4 This is a schematic diagram of the in-memory computing core architecture;

[0026] Figure 5 Schematic diagram of the computational flow of the in-memory computing core based on the approximate adder tree. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the present invention and do not constitute a limitation to the present invention.

[0028] like Figures 1 to 5 As shown, in order to achieve the above purpose, the present invention proposes an approximate adder tree design method for performing addition operations in digital signal processing, comprising the following steps:

[0029] S10: in the first layer of the adder tree, performing a preliminary approximate operation on the input data by alternately setting the OR circuit structure and the OR and AND circuit structure in sequence;

[0030] S20: In the second layer of the adder tree, a high-order retaining or adding structure for retaining the carry result of the first layer and performing an OR operation with the result of the current layer and a half adder or or adding structure for performing a half adder or or or and operation on the result of the previous layer are alternately provided;

[0031] S30: in the third layer to the second to last layer of the adder, half adders, full adders, half adders, or structures and half adders, full adders, or, and structures are alternately arranged, and the corresponding two structures are alternately arranged in the same layer;

[0032] S40: In the last layer of the adder, a half adder, a full adder, a half adder, or a structure is used to complete the final summation operation and output an approximate result to reduce the area and power consumption of the calculation in the digital memory.

[0033] Specifically, the OR circuit structure consists of an OR logic gate, with two 1-bit signals as input. When at least one of the inputs is 1, the output is 1, otherwise the output is 0.

[0034] The OR and AND circuit structure consists of an OR gate and an AND gate. The OR gate is used to obtain the sum without considering the carry, while the AND gate is used to determine whether a carry occurs. The OR and AND circuit has two inputs and two outputs, one output is the sum, and the other output is the carry.

[0035] The high-order retention or adder structure is used to retain the high-order carry from the previous layer and perform an OR operation on the output results of the two OR logic gates in the previous layer.

[0036] The half adder, OR, and AND adder structure consists of a half adder, an OR gate, and an AND gate. The half adder structure consists of an XOR gate (for summing) and an AND gate (for generating a carry). The half adder, OR gate, and AND gate process the result from the previous layer and generate a carry.

[0037] In the first layer of the adder tree, the input data is divided into multiple bit pairs. For each pair of bit data, or circuit structure with two bits as input, if at least one of the two input bits is 1, the output is 1; if both input bits are 0, the output is 0. This structure is used to quickly determine whether at least one of the two input bits is 1, providing a basis for the subsequent simplified calculation.

[0038] The OR and AND circuit structure consists of an OR gate and an AND gate. The OR gate outputs whether there is a 1 in the two input bits; the AND gate outputs a value indicating whether both bits are 1. If so, it means there is a carry. This combination provides the subsequent layers with the ability to detect carries in the same position.

[0039] In the second layer of the adder tree, the high-bit retention in the OR adder structure is responsible for retaining the carry result of the previous layer and performing an OR operation on the output of the OR gate of the previous layer through the OR gate.

[0040] In the second layer, the OR gate in the half adder, OR, and adder structure is responsible for ORing the output of the OR gate in the previous layer, and the AND gate is responsible for ANDing the output of the OR gate in the previous layer. The result and the output of the AND gate in the previous layer enter the half adder for calculation, and two outputs are obtained, generating a new carry. The OR and AND logic of the half adder, OR, and adder structure cooperates with the half adder to not only process the sum, but also participate in the generation of the carry.

[0041] From the third layer to the penultimate layer, the half adder, full adder, half adder, or OR gate in the structure is responsible for ORing the output of the OR gate of the previous layer. The half adder is responsible for calculating the corresponding bits of the two outputs of the previous layer. The result obtained by the XOR of the half adder is retained, and the result obtained by the AND gate enters the full adder. At the same time, the full adder also inputs the corresponding bits of the two outputs of the previous layer, and so on. The last half adder inputs the carry of the full adder and the highest bit of the previous layer.

[0042] From the third layer to the penultimate layer, in the half adder, full adder, OR, and AND structures, the OR gate is responsible for ORing the output of the OR gate of the previous layer, and the AND gate is responsible for ANDing the output of the OR gate of the previous layer. The result obtained by the AND gate enters the full adder. At the same time, the full adder also inputs the corresponding bits of the two outputs of the previous layer, and so on. The last half adder inputs the carry of the full adder and the highest bit of the previous layer.

[0043] The last layer of half adders, full adders, half adders, or structures take the form of carry-free adders, which ultimately collect all the carry and sum information, and work together through half-add operations and OR and logic to provide a more complete summary of carries and sums, and ultimately output an approximate sum.

[0044] The following are some examples:

[0045] Assume that the input number is 1011010010100110101011010110100010, where the number of 1s is 16, that is, the output result of the exact adder tree is 16.

[0046]

[0047] The calculation process of the approximate adder tree is simplified into a table. Now input the 32-bit number from high to low into the approximate adder tree. The calculation process and analysis are as follows:

[0048] (1) The first layer is composed of 32 1-bit inputs, with two 1-bit numbers in a group. They are alternating between OR, OR, and AND to obtain 1-bit and 2-bit outputs respectively. The final output of the first layer is 111_100_101_101_111_101_101_001 ('_' separates a group of alternating output results).

[0049] (2) In the second layer, the output result of the alternating structure of the previous layer also needs to be calculated alternately, which is 1-bit plus 2-bit, and the high-bit is retained alternately, or, half adder, or, and, respectively, to obtain 2-bit and 3-bit outputs. The final output result of the second layer is 11001_01011_11011_01001.

[0050] (3) Similarly, the output of the third layer is 0110101_1010011, and the output of the fourth layer is 011101001.

[0051] (4) Finally, in the fifth layer, the 4-bit number and the 5-bit number of the upper layer output are added together without carrying. The final output result is 01111, which is 15, only 1 less than the exact result. The error is very small and can be eliminated through subsequent processing, such as adding 1 to the result.

[0052] By adopting the above technical scheme, the traditional half adder has 14 transistors, while the OR circuit structure in the present application has 4 transistors, and the OR and AND circuit structure has 8 transistors. When the OR circuit structure and the OR and AND circuit structure are alternately arranged, there are only 6 transistors on average, which is 8 transistors less than the traditional half adder. Therefore, the number of transistors is reduced, and the area and power consumption are reduced. The traditional half adder outputs 2 bits, the approximate half adder structure 1 outputs 1 bit, and the approximate half adder structure 2 outputs 2 bits, and the number of data bits output is also reduced. Therefore, by adopting the scheme of alternating the two approximate half adder structures, the number of data bits is reduced, and the calculation process is further simplified.

[0053] In one embodiment of the present application, the OR and AND circuit structure includes:

[0054] Two input terminals, respectively used to receive 1-bit numbers to be added;

[0055] An OR gate, connected to two input terminals, for summing two input 1-bit numbers; and

[0056] An AND gate, connected to two input terminals, is used to determine whether two 1-bit numbers have a carry.

[0057] Specifically, the OR and AND circuits have two input terminals, each of which receives a binary bit (1 or 0) to be added, usually represented as A and B.

[0058] The OR gate is a basic logic gate with two inputs, used to implement the logical OR function. Input terminals A and B are connected to the OR gate, and its logical expression is A+B. The output is based on the truth table of the OR gate: when at least one of A and B is 1, the output is 1; otherwise, the output is 0. This output can be regarded as part of the addition result, that is, the sum without considering the carry.

[0059] The AND gate is a basic logic gate with two inputs that implements the logical AND function. Inputs A and B are also connected to the AND gate, and its logical expression is A⋅B. The output is 1 if and only if both inputs A and B are 1; in all other cases, the output is 0. This output indicates whether a carry is generated when A and B are added. The carry result is carried forward in the next layer.

[0060] When two 1-bit numbers are input into the OR and AND circuit structure, the two numbers are sent to the OR gate and the AND gate respectively.

[0061] The OR gate sums the two bits, and logically summing means implementing a logical OR function. This corresponds to the bitwise summing in binary addition. The AND gate determines whether the two bits are both 1, and if so, outputs 1 to indicate that a carry is required. This corresponds to the carry that results if both bits are 1 in binary addition. Therefore, the OR gate provides the sum of the two bits, while the AND gate provides an indication of whether a carry is required.

[0062] With the above technical solution, the OR circuit structure has 4 transistors, and the OR / AND circuit structure has 8 transistors. When the OR circuit structure and the OR / AND circuit structure are alternately arranged, there are only 6 transistors on average, which is 8 transistors less than the traditional half adder. Therefore, the number of transistors is reduced, and the area and power consumption are reduced.

[0063] In one embodiment of the present application, the half adder, full adder, half adder, or structure includes a half adder, a full adder, a half adder, and an OR gate arranged in sequence; wherein the number of full adders is equal to the level of the current half adder, full adder, half adder, or structure minus three.

[0064] Specifically, a half adder consists of an XOR gate and an AND gate. The XOR gate is used to obtain a sum without considering the carry, while the AND gate is used to determine whether a carry occurs. A half adder has two inputs and two outputs, one output is the sum and the other is the carry. A full adder consists of two half adders and an OR gate. A full adder can receive two addends and a carry input and produce a sum output and a carry output. A full adder can take into account the carry from the previous operation. The OR gate is one of the basic logic gates used to implement a logical OR operation. When either of the two inputs is 1, the output is 1; otherwise, the output is 0.

[0065] Data processing begins with the OR gate, which calculates the two bits of the input. Next, the half adder, which calculates the two bits of the input without considering the carry. According to the design of the half adder, it outputs a preliminary sum and a signal whether a carry occurred.

[0066] Next, multiple full adders (the number depends on the level minus three) process the addition of higher bits in turn, while calculating the carry from the lower bits together with the two digits to be added. The output of the full adder includes a sum and a new carry signal.

[0067] Finally, a half adder calculates the carry of the full adder and the highest bit input of the previous layer to obtain a sum output and a carry output.

[0068] With the above technical solution, since the full adder can handle the carry from the lower bit, the adder structure can continuously transfer the carry to the higher bit when performing multi-bit addition, which can reduce the calculation delay and improve the accuracy of arithmetic operations. By combining the half adder and the full adder, the solution can flexibly handle the carry in different situations, which means that the operation speed is guaranteed while maintaining high precision.

[0069] In one embodiment of the present application, the half adder, full adder, or, and structure includes a half adder, a full adder, and an or, and gate arranged in sequence; wherein the number of full adders is equal to the level of the current adder tree minus two.

[0070] Specifically, the circuit first starts calculating through the OR and AND structures. The OR gate calculates the OR of the two input bits and retains them. The AND gate calculates the AND of the two input bits and generates a carry signal.

[0071] Next, the full adder takes three inputs: the two bits to be added and a carry bit from the AND gate. The full adder outputs a sum and a carry signal. The sum is the XOR of all three inputs, implemented by two half adders and an OR gate. The number of full adders is the number of half adder, OR, and AND adder structures minus two.

[0072] Finally, the half adder is used to perform summation, calculate the carry of the full adder and the highest bit input of the previous layer, and obtain a sum output and a carry output.

[0073] By adopting the above technical solution, by associating the number of full adders with the current level, the design can be automatically adjusted according to the data width to be processed, providing a method to balance complexity and performance. The combined use of half adders and full adders allows addition and carry to be processed at different speeds at different stages, thereby reducing the delay on certain paths and improving the operation speed of the overall circuit.

[0074] The present application also discloses an adder tree, which is produced by using any of the above-mentioned approximate adder tree design methods.

[0075] The present application also discloses a chip, comprising the adder tree as described above.

[0076] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for designing an approximate adder tree, characterized in that: For performing addition operation in digital signal processing, comprising the following steps: S10: in the first layer of the adder tree, performing a preliminary approximate operation on the input data by alternately setting the OR circuit structure and the OR and AND circuit structure in sequence; S20: In the second layer of the adder tree, a high-order retaining or adding structure for retaining the carry result of the first layer and performing an OR operation with the result of the current layer and a half adder or or adding structure for performing a half adder or or or and operation on the result of the previous layer are alternately provided; S30: in the third layer to the second to last layer of the adder, half adders, full adders, half adders, or structures and half adders, full adders, or, and structures are alternately arranged, and the corresponding two structures are alternately arranged in the same layer; S40: In the last layer of the adder, a half adder, a full adder, a half adder, or a structure is used to complete the final summation operation and output an approximate result to reduce the area and power consumption of the calculation in the digital memory.

2. The approximate adder tree design method as claimed in claim 1, characterized in that: The or and circuit structure comprises: Two input terminals, respectively used to receive 1-bit numbers to be added; An OR gate, connected to two input terminals, for summing two input 1-bit numbers; and An AND gate, connected to two input terminals, is used to determine whether two 1-bit numbers have a carry.

3. The approximate adder tree design method as claimed in claim 1, characterized in that: The half adder, full adder, half adder, or structure includes a half adder, a full adder, a half adder, and an OR gate arranged in sequence; wherein the number of full adders is equal to the level of the current half adder, full adder, half adder, or structure minus three.

4. The approximate adder tree design method as claimed in claim 1, characterized in that: The half adder, full adder, or, and structure comprises a half adder, a full adder, and an or, and gate arranged in sequence; wherein the number of full adders is equal to the level of the current half adder, full adder, or, and structure minus two.

5. An adder tree circuit structure, characterized in that: The method is produced by using the approximate adder tree design method as claimed in any one of claims 1 to 4.

6. A chip, characterized in that: Comprising the adder tree circuit structure as claimed in claim 5.

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