A signal equalization circuit, interface, system on chip and server

Abstract

The embodiments of the present application relate to the field of chip design technology, and more specifically, to a signal equalization circuit, an interface, a system on chip, and a server, which are intended to achieve high-speed signal transmission while eliminating interference between signals. The circuit includes: a master / slave processing unit circuit, a coefficient weighting unit circuit, and a polling unit circuit; the master / slave processing unit circuit is used to receive an input signal, split the input signal into four sub-signals, and output the four sub-signals to the coefficient weighting unit circuit; the coefficient weighting unit circuit is used to receive the four sub-signals, perform weighted processing on the four sub-signals, and obtain an output signal; the polling unit circuit is used to control the signal transmission between the master / slave processing unit circuit and the coefficient weighting unit circuit.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of chip design, and in particular to a signal equalization circuit, an interface, a system on chip, and a server. Background Art

[0002] When designing high-speed interface chips, extremely high requirements are placed on the signal transmission rate of the chip. In high-speed serial links, in order to ensure the transmission rate while avoiding broadband problems such as signal integrity caused by the channel, equalization technology is used to compensate for the attenuation of the high-frequency components of the signal caused by the transmission line.

[0003] The signal equalization circuit in the related art adopts a series structure, which has a simple structure and is limited by the frequency of the process medium, making it difficult to achieve high-speed transmission. In addition, there is serious inter-code interference between the front and rear signals in this structure, which directly affects the equalization effect. Summary of the invention

[0004] The embodiments of the present application provide a signal equalization circuit, an interface, a system on a chip, and a server, which are intended to achieve high-speed signal transmission while eliminating interference between signals.

[0005] A first aspect of an embodiment of the present application provides a signal equalization circuit, characterized in that the circuit comprises: a master / slave processing unit circuit, a coefficient weighting unit circuit, and a polling unit circuit;

[0006] The master / slave processing unit circuit is used to receive an input signal, split the input signal into four sub-signals, and output the four sub-signals to the coefficient weighting unit circuit;

[0007] The coefficient weighting unit circuit is used to receive the four-path sub-signals, perform weighted processing on the four-path sub-signals, and obtain an output signal;

[0008] The polling unit circuit is used to control the signal transmission between the master / slave processing unit circuit and the coefficient weighting unit circuit;

[0009] Among them, each differential unit in the coefficient weighting unit circuit receives one of the four sub-signals according to the gear position corresponding to the current moment, and performs weighted processing on the four sub-signals according to the weight corresponding to each differential unit to obtain the output signal.

[0010] Optionally, the master / slave processing unit circuit includes a master processing unit circuit and a slave processing unit circuit;

[0011] The main processing unit circuit is used to split the input signal into a first path signal and a third path signal;

[0012] The slave processing unit circuit is used for splitting the input signal into a second path signal and a fourth path signal.

[0013] Optionally, the main processing unit circuit includes a first-level main processing unit circuit and a second-level main processing unit circuit;

[0014] The first-stage main processing unit circuit is used to convert the input signal into a first output sub-signal;

[0015] The second-stage main processing unit circuit is used for receiving the first output sub-signal, and splitting the first output sub-signal into the first path sub-signal and the third path sub-signal.

[0016] Optionally, the slave processing unit circuit includes a first-level slave processing unit circuit and a second-level slave processing unit circuit;

[0017] The first-stage slave processing unit circuit is used to convert the input signal into a second output sub-signal;

[0018] The second-stage slave processing unit circuit is used for receiving the second output sub-signal, and splitting the second output sub-signal into the second path sub-signal and the fourth path sub-signal.

[0019] Optionally, the first-level main processing unit circuit includes a first trigger and a second trigger;

[0020] The output terminal of the first trigger is connected to the input terminal of the second trigger.

[0021] Optionally, the second-level main processing unit circuit includes a fifth trigger, a sixth trigger, a seventh trigger, and an eighth trigger;

[0022] An input terminal of the fifth trigger is connected to an output terminal of the second trigger;

[0023] The output terminal of the fifth trigger is connected to the input terminal of the sixth trigger;

[0024] An input terminal of the seventh trigger is connected to an output terminal of the second trigger;

[0025] The output terminal of the seventh flip-flop is connected to the input terminal of the eighth flip-flop.

[0026] Optionally, the first-stage slave processing unit circuit includes a third trigger and a fourth trigger;

[0027] The output terminal of the third trigger is connected to the input terminal of the fourth trigger.

[0028] Optionally, the second-stage slave processing unit circuit includes a ninth trigger, a tenth trigger, an eleventh trigger, and a twelfth trigger;

[0029] The input terminal of the ninth trigger is connected to the output terminal of the fourth trigger;

[0030] The output terminal of the ninth trigger is connected to the input terminal of the tenth trigger;

[0031] The input terminal of the eleventh trigger is connected to the output terminal of the fourth trigger;

[0032] The output terminal of the eleventh flip-flop is connected to the input terminal of the twelfth flip-flop.

[0033] Optionally, the coefficient weighting unit circuit includes a first differential unit, a second differential unit, a third differential unit, a fourth differential unit, and a signal amplitude control resistor;

[0034] The first differential unit is used to receive a first path of sub-signals among the four paths of sub-signals;

[0035] The second differential unit is used to receive a fourth path of sub-signals among the four paths of sub-signals;

[0036] The third differential unit is used to receive a third path of sub-signals among the four paths of sub-signals;

[0037] The fourth differential unit is used to receive the second path sub-signal among the four paths sub-signals;

[0038] The signal amplitude control resistor is used to control the swing amplitude of the output signal;

[0039] The signal amplitude control resistor is connected to the first differential unit, the second differential unit, the third differential unit, and the fourth differential unit.

[0040] Optionally, the first differential unit includes a first differential input port, a second differential input port, and a first constant current source;

[0041] The first differential input port is used to receive the positive signal of the first path signal;

[0042] The second differential input port is used to receive the negative signal of the first path signal;

[0043] The first constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0044] Optionally, the second differential unit includes a third differential input port, a fourth differential input port, and a second constant current source;

[0045] The third differential input port is used to receive the positive signal of the fourth path signal;

[0046] The fourth differential input port is used to receive the negative signal of the fourth path signal;

[0047] The second constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0048] Optionally, the third differential unit includes a fifth differential input port, a sixth differential input port, and a third constant current source;

[0049] The fifth differential input port is used to receive the positive signal of the third path signal;

[0050] The sixth differential input port is used to receive the negative signal of the third path signal;

[0051] The third constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0052] Optionally, the fourth differential unit includes a seventh differential input port, an eighth differential input port, and a fourth constant current source;

[0053] The seventh differential input port is used to receive the positive signal of the second path signal;

[0054] The eighth differential input port is used to receive the negative signal of the second path signal;

[0055] The fourth constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0056] Optionally, the polling unit circuit includes a rising edge detection unit, a counter unit, a modulo 4 unit, a base conversion unit, and a shift unit.

[0057] Optionally, the rising edge detection unit is used to detect a clock signal sent by a clock circuit;

[0058] When the rising edge detection unit detects that the clock circuit sends a clock signal, the rising edge detection unit sends notification information to the counter unit.

[0059] Optionally, the counter unit is used to record the number of rising edge signals of the clock signal;

[0060] When receiving the notification information sent by the rising edge detection unit, the counter unit increases the number of recorded rising edge signals by one.

[0061] Optionally, the modulo 4 unit is used to limit the polling unit circuit to a reception time of four rising edge signals as one shift cycle.

[0062] Optionally, the base conversion unit is used to convert a decimal number into a binary number;

[0063] The base conversion unit obtains the decimal number recorded in the counter unit;

[0064] The base conversion unit converts the decimal number into a binary number.

[0065] Optionally, the shift unit is used to control signal transmission of the four sub-signals;

[0066] The shift unit switches the four sub-signals to corresponding interfaces according to the binary number obtained by the base conversion unit.

[0067] A second aspect of the embodiment of the present application provides an interface, the interface comprising the signal equalization circuit as described in the first aspect of the embodiment of the present application;

[0068] A third aspect of the embodiment of the present application provides a system on chip, the system on chip includes implementing communication through an interface, the interface in the system on chip includes the signal equalization circuit as described in the first aspect of the embodiment of the present application;

[0069] A fourth aspect of an embodiment of the present application provides a server, wherein the server runs a system on a chip. The communication interface of the system on a chip in the server includes the signal equalization circuit as described in the first aspect of the embodiment of the present application.

[0070] Optionally, the polling unit circuit is a digital circuit running in the signal equalization circuit.

[0071] The signal equalization circuit provided by the present application is adopted, and the circuit includes a master / slave processing unit circuit, a coefficient weighting unit circuit, and a polling unit circuit; the master / slave processing unit circuit is used to receive an input signal, split the input signal into four sub-signals, and output the four sub-signals to the coefficient weighting unit circuit; the coefficient weighting unit circuit is used to receive the four sub-signals, perform weighted processing on the four sub-signals, and obtain an output signal; the polling unit circuit is used to control the signal transmission between the master / slave processing unit circuit and the coefficient weighting unit circuit. The present application utilizes the master-slave structure technology to design a master / slave processing unit circuit. The master-slave structure technology divides a single data transmission path into multiple paths, and uses the half-rate structure technology to halve the clock frequency of the traditional equalization circuit, thereby reducing the difficulty of designing the clock circuit and the impact of clock jitter data on the signal. For the signal on each path, only one part is collected at the same time, and these parts will not be interfered by the previous and next signals. Based on the polling technology, a coefficient weighting unit circuit and a polling unit circuit are designed to realize weighted processing of signals on multiple paths. While ensuring high-speed transmission of the signal, interference between signals is eliminated, thereby improving the signal compensation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0073] Figure 1 is a structural schematic diagram of a signal equalization circuit proposed in an embodiment of the present application;

[0074] Figure 2 is a schematic diagram of the circuit structure of a master / slave processing unit proposed in an embodiment of the present application;

[0075] Figure 3 is a timing diagram proposed in an embodiment of the present application;

[0076] Figure 4 It is a schematic diagram of the circuit structure of a coefficient weighting unit proposed in an embodiment of the present application;

[0077] Figure 5 It is a schematic diagram of the circuit structure of a polling selection unit proposed in an embodiment of the present application;

[0078] Figure 6 This is the traditional NRZ FEE circuit structure diagram. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0080] The traditional NRZ (Non-Return to Zero, FFEFeed Feedback Equalization) circuit structure is as follows Figure 6 As shown, Figure 6 This is a diagram of the traditional NRZ FEE circuit structure. In the figure, the 4-tap FEE circuit structure includes 3 delay units (T), 4 multipliers and 1 adder. The circuit has a delay line composed of 3 delay units, which is connected by a tap coefficient (c i , i =-1~2) for input signal ( V in1 ) is weighted and then amplitude superposition is performed to achieve signal compensation. This circuit structure is simple and is limited by the process cutoff frequency, making it difficult to achieve high-speed transmission rate. The delay line is a linear structure, and there is serious inter-code interference between the front and rear signals, which directly affects the equalization effect.

[0081] refer to Figure 1 , Figure 1 Schematic diagram of the structure of the signal equalization circuit proposed in one embodiment of the present application. Figure 1 As shown, the circuit includes:

[0082] A master / slave processing unit circuit, a coefficient weighting unit circuit, and a polling unit circuit. The master / slave processing unit circuit is used to receive an input signal, split the input signal into four sub-signals, and output the four sub-signals to the coefficient weighting unit circuit. The coefficient weighting unit circuit is used to receive the four sub-signals, perform weighted processing on the four sub-signals, and obtain an output signal. The polling unit circuit is used to control signal transmission between the master / slave processing unit circuit and the coefficient weighting unit circuit.

[0083] In this embodiment, the signal equalization circuit (FFE, Feed Forward Equalization) is a feed forward equalization circuit. The signal equalization circuit is at the transmitting end of the high-speed chip, and uses the waveform of the received signal itself to correct the received signal, that is, equalizes the collected signal waveform. When equalizing the signal waveform, it generates a delay and weighting of the input signal.

[0084] In this embodiment, the master / slave processing unit circuit is used to receive an input signal and split the input signal into four sub-signals. The four sub-signals after splitting are actually the same as the input signal. The master / slave processing unit circuit also outputs the four split sub-signals to the coefficient weighting unit circuit respectively.

[0085] In this embodiment, the coefficient weighting unit circuit is used to receive the four-way sub-signals sent by the master / slave processing unit circuit, and perform weighted processing on the four-way sub-signals to obtain output signals. The coefficient weighting unit circuit has four differential units. For the received four-way sub-signals, the corresponding differential units are used to receive the four-way sub-signals. Each differential unit has a corresponding weight coefficient, and a corresponding weight coefficient is assigned to each signal, thereby completing the compensation of the signal.

[0086] In this embodiment, the polling unit circuit is a digital circuit running on the signal equalization circuit. The polling unit circuit is used to control the signal transmission between the input / output processing unit circuit and the coefficient weighting unit circuit. The polling unit circuit can control the connection relationship between the input / output processing unit circuit, thereby ensuring that each signal path is input into the corresponding differential unit at the corresponding time, thereby eliminating interference between signals.

[0087] Among them, each differential unit in the coefficient weighting unit circuit receives one of the four sub-signals according to the gear position corresponding to the current moment, and performs weighted processing on the four sub-signals according to the weight corresponding to each differential unit to obtain the output signal.

[0088] In this embodiment, the signal equalization circuit is divided into two master / slave processing circuits according to the positions of the pre-mark, main mark and post-mark in the coefficient weighting circuit. Each processing circuit includes two signal transmission paths. The main processing unit circuit outputs the first path signal and the third path signal, and the slave processing unit circuit outputs the second path signal and the fourth path signal. In the master / slave processing power supply circuit, each transmission path can realize the signal transmission function, and the half-rate structure is used to reduce the clock frequency. The half-rate structure is to divide the circuit into two-level processing units, including the first-level processing unit circuit and the second-level processing unit circuit. The circuit is actually composed of D flip-flops. This can widen the signal cycle and improve the signal establishment time and holding time. The coefficient weighting circuit receives the multiplexed signal (two or more signals), and the received signal is weighted with the tap coefficient of each differential unit, and then the weighted signal is output. The tap coefficient is an important parameter in the digital filter, which is used to control the weight ratio of different input signals in the output filter output. The polling unit circuit controls the interconnection of the master / slave processing unit circuit and the coefficient weighting unit circuit by detecting the input signal frequency to assist the coefficient weighting unit circuit to realize the weighted processing of the signal. The clock signal required by the signal equalization circuit is provided by the clock circuit, which is an oscillating circuit that produces accurate movement like a clock. Any work is in time sequence. The circuit used to generate this time is the clock circuit. The clock circuit is generally composed of a crystal oscillator, a crystal oscillator control chip and a capacitor. The clock signal (Clock Signal) is the basis of sequential logic and is used to determine when the state in the logic unit is updated. It is a signal quantity with a fixed cycle and is independent of operation. The clock signal has a fixed clock frequency, which is the reciprocal of the clock cycle. In electronic, especially signal synchronous digital circuits, the clock signal is a special signal oscillating between high and low states. The signal is used like a metronome to coordinate the actions of digital circuits. The digital clock signal is basically a square wave voltage.

[0089] In this embodiment, the clock signal required by the signal equalization circuit is provided by the clock circuit. Assuming that the clock frequency of the input signal is f0, the frequencies of the first-level structure and the second-level structure in the master / slave processing circuit are f1 and f2 respectively, and the frequency relationship is f0=2f1=4f2. It can be seen that compared with the traditional signal equalization circuit, the frequency required by the signal equalization circuit in this embodiment is one-fourth of the traditional signal equalization circuit, which effectively reduces the frequency of the clock circuit and is more conducive to signal compensation.

[0090] In this embodiment, the master / slave processing unit circuit includes a master processing unit circuit and a slave processing unit circuit. The master processing unit circuit is used to split the input signal into a first path signal and a third path signal; the slave processing unit circuit is used to split the input signal into a second path signal and a fourth path signal.

[0091] In this embodiment, reference Figure 2 , Figure 2 is a schematic diagram of the circuit structure of the master / slave processing unit proposed in an embodiment of the present application, such as Figure 2 As shown, the master / slave processing unit circuit includes a master processing unit circuit and a slave processing unit circuit.

[0092] The main processing unit circuit is used for splitting the input signal into a first path signal and a third path signal.

[0093] In this embodiment, Figure 2 As shown, the main processing unit receives an input signal and splits the input signal into a first path sub-signal (D01) and a third path sub-signal (D03).

[0094] The slave processing unit circuit is used for splitting the input signal into a second path signal and a fourth path signal.

[0095] In this year's embodiment, Figure 2 As shown, the input signal is received from the processing unit circuit, and the input signal is differentially divided into a second path signal (DO2) and a fourth path signal (D04).

[0096] The main processing unit circuit includes a first-level main processing unit circuit and a second-level main processing unit circuit.

[0097] In this embodiment, each transmission path in the master / slave processing circuit uses a half-rate structure to achieve signal cycle widening. The half-rate structure is divided into a first-level processing unit circuit and a second-level processing unit circuit, both of which are implemented using a D flip-flop (DFF) triggered by the rising edge and the falling edge. The D flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit for constituting a variety of sequential circuits and an important unit circuit in digital logic circuits. Therefore, the D flip-flop is widely used in digital systems and computers. The flip-flop has two stable states, namely 0 and 1. Under the action of certain external signals, it can flip from one stable state to another stable state. The D flip-flop has a flip-flop composed of an integrated flip-flop and a gate circuit. There are two triggering modes: level triggering and edge triggering. The former can be triggered when CP (clock pulse) = 1, and the latter is mostly triggered at the leading edge of CP (positive jump 0→1). The next state of the D flip-flop depends on the state of the D terminal before the trigger, that is, the next state = D. Therefore, it has two functions of setting 0 and setting 1. For edge-triggered D flip-flops, since the circuit has a blocking function during CP=1, the data state change at the D terminal during CP=1 will not affect the output state of the flip-flop. D flip-flops are widely used and can be used for digital signal storage, shift storage, frequency division and waveform generator, etc. Figure 2The triggers without circles are triggered on the rising edge of the clock, and the triggers with circles are triggered on the falling edge of the clock.

[0098] The first-stage main processing unit circuit is used to convert the input signal into a first output sub-signal.

[0099] In this embodiment, the input signal is divided into two paths after entering the master / slave processing unit circuit. One path enters the first trigger (DFF1) in the first-level master processing unit circuit, and then passes through the second trigger (DFF2) from the first-level master processing unit circuit to the second-level master processing unit. When it is output from the second trigger of the first-level master processing unit, it is converted into the first output sub-signal (D11).

[0100] The second-stage main processing unit circuit is used for receiving the first output sub-signal, and splitting the first output sub-signal into the first path sub-signal and the third path sub-signal.

[0101] In this embodiment, the second-level main processing unit receives the first output sub-signal, and the first output sub-signal is split into two paths. One path enters the first output sub-signal and enters the fifth trigger (DFF5), and then enters the sixth trigger (DFF6). The other path enters the seventh trigger (DFF7), and then enters the eighth trigger (DFF8), outputting the first path sub-signal (DO1) and the third path sub-signal (D03).

[0102] The slave processing unit circuit includes a first-level slave processing unit circuit and a second-level slave processing unit circuit.

[0103] In this embodiment, the first-level slave processing unit circuit is a first-level circuit in the slave processing unit circuit, and the second-level slave processing unit circuit is a second-level circuit in the slave processing unit circuit.

[0104] The first-stage slave processing unit circuit is used to convert the input signal into a second output sub-signal.

[0105] In this embodiment, the input signal is divided into two paths after entering the master / slave processing unit circuit, one of which enters the third trigger (DFF3) in the first-level slave processing unit circuit, and then passes through the fourth trigger (DFF4), and then outputs the second path signal D12.

[0106] In this embodiment, the second-stage slave processing unit circuit is used to receive the second output sub-signal, and split the second output sub-signal into the second path sub-signal and the fourth path signal.

[0107] In this embodiment, the second stage receives the second output sub-signal from the processing unit circuit, and the second output sub-signal is split into two paths, one path enters the ninth trigger (DFF9), and then enters the tenth trigger (DFF10), and outputs the second sub-signal DO2, and the other path enters the eleventh trigger (DFF11), and then enters the twelfth trigger (DFF12), and outputs the fourth sub-signal DO4.

[0108] The first-stage main processing unit circuit includes a first trigger and a second trigger.

[0109] The output terminal of the first trigger is connected to the input terminal of the second trigger.

[0110] The second-stage main processing unit circuit includes a fifth trigger, a sixth trigger, a seventh trigger, and an eighth trigger.

[0111] An input terminal of the fifth trigger is connected to an output terminal of the second trigger.

[0112] The output terminal of the fifth flip-flop is connected to the input terminal of the sixth flip-flop.

[0113] An input terminal of the seventh trigger is connected to an output terminal of the second trigger.

[0114] The output end of the seventh trigger is connected to the input end of the eighth trigger. The first-stage slave processing unit circuit includes a third trigger and a fourth trigger.

[0115] The output terminal of the third trigger is connected to the input terminal of the fourth trigger.

[0116] The second-stage slave processing unit circuit includes a ninth trigger, a tenth trigger, an eleventh trigger, and a twelfth trigger; an input end of the ninth trigger is connected to an output end of the fourth trigger.

[0117] The output terminal of the ninth flip-flop is connected to the input terminal of the tenth flip-flop.

[0118] An input terminal of the eleventh trigger is connected to an output terminal of the fourth trigger.

[0119] The output terminal of the eleventh flip-flop is connected to the input terminal of the twelfth flip-flop.

[0120] In this embodiment, Figure 2As shown, taking DO1 as an example, the main processing unit circuit samples the input signal Di when triggered by the rising edge of the clock signal ck1, and inputs the first output sub-signal D11. The second-level main processing unit circuit samples the first output sub-signal D11 output by the first-level main processing unit circuit when triggered by the rising edge of the clock signal ck2, and outputs D01. The other output signals D02, D03, and D04 are all the same process, and the phase of the clock corresponding to each trigger is different.

[0121] refer to Figure 3 , Figure 3 is a timing diagram proposed in an embodiment of the present application, such as Figure 3 As shown, the first-level processing unit circuit in the master / slave processing circuit separates the input signal Di according to the odd and even sequence, for example, the input signal Di is a0, b0, c0, d0, a1, b1, c1, d1, a2, b2, c2, d2, ..., the output signal D11 of the first-level master processing unit circuit is a0, c0, a1, c1, a2, c2, ..., the output signal D12 of the first-level slave processing unit circuit is b0, d0, b1, d1, b2, d2, .... The second-level processing unit circuit in the master / slave processing circuit separates the input signal D11 / D12 according to the odd and even sequence, the output signals Do1 and Do3 of the master processing unit circuit are a0, a1, a2, ..., and c0, c1, c2, ..., respectively, and the output signals Do2 and Do4 of the slave processing unit circuit are b0, b1, b2, ..., and d0, d1, d2, ..., respectively. Among them, pre is the front mark, main is the main mark, pos1 is the first rear mark, and pos2 is the second rear mark, which respectively represent the interfaces corresponding to the signals at different times. Figure 3 In the embodiment, compared with the period of the input signal Di, the periods of the first-stage processing unit circuit output signal D11 and the second-stage processing unit circuit output signal D01 are doubled.

[0122] The coefficient weighting unit circuit includes a first differential unit, a second differential unit, a third differential unit, a fourth differential unit, and a signal amplitude control resistor.

[0123] In this embodiment, reference Figure 4 , Figure 4 is a schematic diagram of a coefficient weighting unit circuit structure proposed in an embodiment of the present application, such as Figure 4As shown, the coefficient weighting unit circuit includes a first differential unit, the first differential unit consists of a first differential input port M1, a second differential input port M2, a first constant current source, a second differential unit, the second differential unit includes a third differential input port M3, a fourth differential input port M4, a second constant current source, a third differential unit, the third differential unit includes a fifth differential input port M5, a sixth differential input port M6, a third constant current source, a fourth differential unit, the fourth differential unit includes a seventh differential input port M7, an eighth differential input port M8, and a fourth constant current source. A signal amplitude control resistor, the signal amplitude control resistor is composed of two resistors R, one of which is connected to the first differential input port, the third differential input port, the fifth differential input port, and the seventh differential input port, and the other resistor is connected to the second differential input port, the fourth differential input port, the sixth differential input port, and the eighth differential input port.

[0124] In this embodiment, the differential circuit is composed of two symmetrical circuits, which together constitute a complete circuit. The parameters of the two circuits are exactly the same, so they have the same input and output levels. When the input of one circuit changes, the input of the other circuit will also change accordingly, but their outputs remain the same. Therefore, the output of the differential circuit is obtained by the difference in the inputs of the two circuits. Each differential input unit is a MOS tube, that is, a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), which is a widely used semiconductor device. The MOS tube is composed of a metal electrode, an insulating layer and a semiconductor material. It uses the conductive properties of the N-type or P-type region in the semiconductor to control the flow of current. The working principle of the MOS tube is to control the current by applying an electric field on the insulating layer of the semiconductor material to change its conductive properties. When an appropriate voltage is applied to the metal electrode, the electric field will form an electric field under the insulating layer, which will affect the conductivity of the semiconductor region. High input resistance: The input resistance of the MOS tube is very high and is suitable for use as a high impedance amplifier. Low noise: Due to the high input resistance, the MOS tube has the characteristic of low noise. Low power consumption: Since only a small current is needed to control the current flow, the MOS tube has low power consumption. Fast response: The MOS tube has a fast response speed, which can reach a frequency of several hundred megahertz. The constant current source is a wide spectrum, high-precision AC current-stabilized power supply with the advantages of fast response speed, high constant current accuracy, long-term stable operation, and suitable for various types of loads (resistive, inductive, capacitive). It is mainly used to detect thermal relays, molded case circuit breakers, small circuit breakers, and production occasions where the rated current, operating current, short-circuit protection current, etc. need to be set.

[0125] The first differential unit is used to receive a first path of sub-signals among the four paths of sub-signals.

[0126] The second differential unit is used to receive a fourth sub-signal among the four sub-signals.

[0127] The third differential unit is used to receive a third sub-signal among the four sub-signals.

[0128] The fourth differential unit is used to receive the second path sub-signal among the four paths sub-signals.

[0129] The signal amplitude control resistor is used to control the swing amplitude of the output signal.

[0130] The signal amplitude control resistor is connected to the first differential unit, the second differential unit, the third differential unit, and the fourth differential unit.

[0131] The first differential unit includes a first differential input port, a second differential input port, and a first constant current source.

[0132] The first differential input port is used to receive the positive signal of the first path signal.

[0133] The second differential input port is used to receive the negative signal of the first path signal.

[0134] In this embodiment, Figure 4 As shown, the first differential input port M1 corresponds to the positive signal Vprep of the first path signal, and the second differential input port M2 corresponds to the negative signal Vpren of the first path signal. The corresponding tap coefficient is cpre.

[0135] The first constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0136] The second differential unit includes a third differential input port, a fourth differential input port, and a second constant current source.

[0137] The third differential input port is used to receive the positive signal of the fourth path signal.

[0138] The fourth differential input port is used to receive the negative signal of the fourth path signal.

[0139] In this embodiment, Figure 4 As shown, the third differential input port M3 corresponds to the positive signal Vmainp of the first path signal, and the fourth differential input port M4 corresponds to the negative signal Vmainn of the first path signal. The corresponding tap coefficient is Cmain.

[0140] The second constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0141] The third differential unit includes a fifth differential input port, a sixth differential input port, and a third constant current source.

[0142] The fifth differential input port is used to receive the positive signal of the third path signal.

[0143] The sixth differential input port is used to receive the negative signal of the third path signal.

[0144] In this embodiment, Figure 4 As shown, the fifth differential input port M5 corresponds to the positive signal Vpos1p of the first path signal, and the sixth differential input port M6 corresponds to the negative signal Vpos1n of the first path signal. The corresponding tap coefficient is Cpos1.

[0145] The third constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0146] The fourth differential unit includes a seventh differential input port, an eighth differential input port, and a fourth constant current source.

[0147] The seventh differential input port is used to receive the positive signal of the second path signal.

[0148] The eighth differential input port is used to receive the negative signal of the second path signal.

[0149] In this embodiment, Figure 4 As shown, the seventh differential input port M7 corresponds to the positive signal Vpos2p of the first path signal, and the eighth differential input port M8 corresponds to the negative signal Vpos2n of the first path signal. The corresponding tap coefficient is Cpos2.

[0150] The fourth constant current source is used to provide a stable current for the coefficient weighting unit circuit.

[0151] In this embodiment, Figure 4 As shown, the differential input ports Vprep / Vpren, Vmainp / Vmainn, Vpos1p / Vpos1n, Vpos2p / Vpos2n respectively constitute the input signals Vpre, Vmain, Vpos1, Vpos2 corresponding to the pre-marker, main mark, first post-marker and second post-marker, and the corresponding tap coefficients are Cpre, Cmain, Cpos1 and Cpos2. The differential output port Voutp / Voutn constitutes the output signal Vout, which is equal to Vpre×cpre+Vmain×Cmain+Vpos1×Cpos1+Vpos2×Cpos2.

[0152] The polling unit circuit includes a rising edge detection unit, a counter unit, a modulo 4 unit, a base conversion unit, and a shift unit.

[0153] In this embodiment, reference Figure 5, Figure 5 1 is a schematic diagram of the circuit structure of a polling selection unit proposed in an embodiment of the present application, which includes a rising edge detection unit, a counter unit, a modulo 4 unit, a base conversion unit, and a shift unit.

[0154] The rising edge detection unit is used to detect the clock signal sent by the clock circuit.

[0155] In this embodiment, when the clock circuit sends a clock signal to the signal equalization circuit, the rising edge detection unit detects that the clock signal is at a rising edge.

[0156] When the rising edge detection unit detects that the clock circuit sends a clock signal, the rising edge detection unit sends notification information to the counter unit.

[0157] In this embodiment, when the rising edge detection unit detects that the clock circuit sends a clock signal, it sends notification information to the counter unit, where the notification information is used to notify the counter unit to increase the count of the received rising edge signal by one.

[0158] The counter unit is used to record the number of rising edge signals of the clock signal.

[0159] When receiving the notification information sent by the rising edge detection unit, the counter unit increases the number of recorded rising edge signals by one.

[0160] In this embodiment, the counter unit is used to record the number of rising edge signals of the clock signal. When the first clock signal is sent to the signal equalization circuit, the number of rising edge signals recorded is 1. When the second clock signal is sent to the signal equalization circuit, the number of rising edge signals recorded is 2. And so on. Every time the signal equalization circuit receives a clock signal, the counter unit adds one to the number of rising edge signals recorded. When recording the number of rising edge signals, the counter unit uses decimal counting. Due to the limitation of the modulo 4 unit, every time the number recorded reaches a multiple of 4, the counter unit will start counting from 0 again, that is, 0.1.2.3.0.1.2.3, and so on.

[0161] The modulo 4 unit is used to limit the polling unit circuit to receive four rising edge signals as one shift cycle.

[0162] In this embodiment, the setting of the modulo 4 unit is to limit the polling unit circuit to the reception time of four rising edge signals as a shift cycle. After each shift cycle, the corresponding interface of each path signal in the coefficient weighting unit circuit is the same as the initial state, that is, the first path signal corresponds to the first differential unit, the second path signal corresponds to the fourth differential unit, the third path signal corresponds to the third differential unit, and the fourth path signal corresponds to the second differential unit.

[0163] The base conversion unit is used for converting a decimal number into a binary number.

[0164] The base conversion unit obtains the decimal number recorded in the counter unit.

[0165] The base conversion unit converts the decimal number into a binary number.

[0166] In this embodiment, the base conversion unit acts after the counter unit updates the number of rising edge signals recorded. Each time the number of rising edge signals is updated, the base conversion unit obtains the decimal number recorded in the counter unit and converts the decimal number into a binary number. Due to the limitation of the modulo 4 unit, the decimal number can only be converted into four binary numbers: 00, 01, 10, and 11.

[0167] The shift unit is used to control the signal transmission of the four sub-signals.

[0168] The shift unit switches the four sub-signals to corresponding interfaces according to the binary number obtained by the base conversion unit.

[0169] In this embodiment, the shift unit searches the interface interconnection table corresponding to the shift circuit according to the binary number obtained by the base conversion unit, and further determines the differential unit corresponding to each path signal at each moment.

[0170] Refer to Table 1, which is an interface interconnection table corresponding to a shift circuit proposed in an embodiment of the present application.

[0171] Table 1

[0172]

[0173] As shown in Table 1, at the first moment of a shift cycle of the signal equalization circuit, at this moment, the clock circuit does not send a clock signal, and the interface corresponding to each sub-signal is in the initial state. At this time, the rising edge detection unit in the polling selection circuit does not send notification information to the counter unit. At this time, the number of rising edge signals recorded in the counter unit is 0, and the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 0. The number conversion unit converts the decimal number 0 to the binary number 00. At this time, the interface corresponding to the first sub-signal D01 is the first differential unit, and the gear corresponding to the sub-signal is the pre (pre-mark) gear. At this time, the shift unit maintains the default gear.

[0174] At the first moment of a shift cycle of the signal equalization circuit, at this moment, the clock circuit does not send a clock signal, and the interface corresponding to each sub-signal is in the initial state. At this time, the rising edge detection unit in the polling selection circuit does not send notification information to the counter unit. At this time, the number of rising edge signals recorded in the counter unit is 0, and the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 0. The number conversion unit converts the decimal number 0 to the binary number 00. At this time, the interface corresponding to the second sub-signal D02 is the fourth differential unit, and the gear corresponding to this sub-signal is the pos2 (second postscript) gear. At this time, the shift unit maintains the default gear.

[0175] At the first moment of a shift cycle of the signal equalization circuit, at this moment, the clock circuit does not send a clock signal, and the interface corresponding to each sub-signal is in the initial state. At this time, the rising edge detection unit in the polling selection circuit does not send notification information to the counter unit. At this time, the number of rising edge signals recorded in the counter unit is 0, and the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 0. The number conversion unit converts the decimal number 0 to the binary number 00. At this time, the interface corresponding to the third sub-signal D03 is the third differential unit, and the gear position corresponding to this sub-signal is the pos1 (first postscript) gear position. At this time, the shift unit maintains the default gear position.

[0176] At the first moment of a shift cycle of the signal equalization circuit, at this moment, the clock circuit does not send a clock signal, and the interface corresponding to each sub-signal is in the initial state. At this time, the rising edge detection unit in the polling selection circuit does not send notification information to the counter unit. At this time, the number of rising edge signals recorded in the counter unit is 0, and the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 0. The number conversion unit converts the decimal number 0 to the binary number 00. At this time, the interface corresponding to the fourth sub-signal D04 is the second differential unit, and the gear corresponding to this sub-signal is the main gear. At this time, the shift unit maintains the default gear.

[0177] At the first moment of a shift cycle of the signal equalization circuit, the coefficient weighting unit circuit collects the signal of the pre (pre-mark) gear of the first path signal D01, the coefficient weighting unit circuit collects the signal of the pos2 (second post-mark) gear of the second path signal D02, the coefficient weighting unit circuit collects the signal of the pos1 (first post-mark) gear of the third path signal D03, and the coefficient weighting unit circuit collects the signal of the main (main mark) gear of the fourth path signal D04. At this time, according to the tap coefficient preset by each differential unit, the weighted sum of these signals is obtained to obtain the output signal.

[0178] When the rising edge detection unit in the polling selection circuit detects the first clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 0 to 1. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 1. The number conversion unit converts the decimal number 1 into the binary number 01. At this time, the interface corresponding to the first path signal D01 is the second differential unit, and the gear position corresponding to the sub-signal is the main gear position. At this time, the shift unit adjusts the interface corresponding to the first path signal DO1 from the pre gear position to the main gear position.

[0179] When the rising edge detection unit in the polling selection circuit detects the first clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 0 to 1. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 1. The number conversion unit converts the decimal number 1 into the binary number 01. At this time, the interface corresponding to the second path signal D02 is the first differential unit, and the gear position corresponding to the sub-signal is the pre (pre-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the second path signal DO2 from the pos2 (second post-mark) gear position to the pre (pre-mark) gear position.

[0180] When the rising edge detection unit in the polling selection circuit detects the first clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 0 to 1. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 1. The number conversion unit converts the decimal number 1 into the binary number 01. At this time, the interface corresponding to the third path signal D03 is the fourth differential unit, and the gear position corresponding to this sub-signal is the pos2 (second post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the third path signal DO3 from the pos1 (first post-mark) gear position to the pos2 (second post-mark) gear position.

[0181] When the rising edge detection unit in the polling selection circuit detects the first clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 0 to 1. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 1. The number conversion unit converts the decimal number 1 into the binary number 01. At this time, the interface corresponding to the fourth path signal D04 is the third differential unit, and the gear position corresponding to the sub-signal is the pos1 (first post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the fourth path signal DO4 from the main (main mark) gear position to the pos1 (first post-mark) gear position.

[0182] At the second moment, the coefficient weighting unit circuit collects the signal of the main position of the first path signal D01, the coefficient weighting unit circuit collects the signal of the pre position of the second path signal D02, the coefficient weighting unit circuit collects the signal of the pos2 position of the third path signal D03, and the coefficient weighting unit circuit collects the signal of the pos1 position of the fourth path signal D04. At this time, according to the tap coefficients preset by each differential unit, the weighted sum of these signals is obtained to obtain the output signal.

[0183] When the rising edge detection unit in the polling selection circuit detects the second clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 1 to 2. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 2. The number conversion unit converts the decimal number 2 into the binary number 10. At this time, the interface corresponding to the first path signal D01 is the third differential unit, and the gear position corresponding to the sub-signal is the pos1 (first post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the first path signal DO1 from the main (main) gear position to the pos1 (first post-mark) gear position.

[0184] When the rising edge detection unit in the polling selection circuit detects the second clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 1 to 2. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 2. The number conversion unit converts the decimal number 2 into the binary number 10. At this time, the interface corresponding to the second path signal D02 is the second differential unit, and the gear position corresponding to the sub-signal is the main gear position. At this time, the shift unit adjusts the interface corresponding to the second path signal DO2 from the pre gear position to the main gear position.

[0185] When the rising edge detection unit in the polling selection circuit detects the second clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 1 to 2. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 2. The number conversion unit converts the decimal number 2 into the binary number 10. At this time, the interface corresponding to the third path sub-signal D03 is the first differential unit, and the gear position corresponding to this sub-signal is the pre (pre-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the third path signal DO3 from the pos2 (second post-mark) gear position to the pre (pre-mark) gear position.

[0186] When the rising edge detection unit in the polling selection circuit detects the second clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 1 to 2. The number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 2. The number conversion unit converts the decimal number 2 into the binary number 10. At this time, the interface corresponding to the fourth path signal D04 is the fourth differential unit, and the gear position corresponding to this sub-signal is the pos2 (second post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the fourth path signal DO4 from the pos1 (first post-mark) gear position to the pos2 (second post-mark) gear position.

[0187] At the third moment, the coefficient weighting unit circuit collects the signal of the pos1 (first post-mark) gear of the first path signal D01, the coefficient weighting unit circuit collects the signal of the main (main) gear of the second path signal D02, the coefficient weighting unit circuit collects the signal of the pre (pre-mark) gear of the third path signal D03, and the coefficient weighting unit circuit collects the signal of the pos2 (second post-mark) gear of the fourth path signal D04. At this time, according to the tap coefficients preset by each differential unit, the weighted sum of these signals is obtained to obtain the output signal.

[0188] When the rising edge detection unit in the polling selection circuit detects the third clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 2 to 3. Then the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 3. The number conversion unit converts the decimal number 3 into the binary number 11. At this time, the interface corresponding to the first path signal D01 is the fourth differential unit, and the gear position corresponding to this sub-signal is the pos2 (second post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the first path signal DO1 from the pos1 (first post-mark) gear position to the pos2 (second post-mark) gear position.

[0189] When the rising edge detection unit in the polling selection circuit detects the third clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 2 to 3. Then the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 3. The number conversion unit converts the decimal number 3 into the binary number 11. At this time, the interface corresponding to the second path signal D02 is the third differential unit, and the gear position corresponding to this sub-signal is the pos1 (first post-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the second path signal DO2 from the main (main) gear position to the pos1 (first post-mark) gear position.

[0190] When the rising edge detection unit in the polling selection circuit detects the third clock signal in a shifting cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 2 to 3. Then the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 3. The number conversion unit converts the decimal number 3 into the binary number 11. At this time, the interface corresponding to the third sub-signal D03 is the second differential unit, and the gear position corresponding to the sub-signal is the main gear position. At this time, the shift unit adjusts the interface corresponding to the third sub-signal DO3 from the pre gear position to the main gear position.

[0191] When the rising edge detection unit in the polling selection circuit detects the third clock signal in a shift cycle, a notification message is sent to the counter unit in the polling selection circuit. The notification message is used to notify the counter unit to record the number of rising edge signals plus one. At this time, the counter unit receives the notification message and the number of rising edge signals recorded changes from 2 to 3. Then the number conversion unit obtains that the number of rising edge signals recorded in the counter unit is 3. The number conversion unit converts the decimal number 3 into the binary number 11. At this time, the interface corresponding to the fourth path signal D04 is the fourth differential unit, and the gear position corresponding to this sub-signal is the pre (pre-mark) gear position. At this time, the shift unit adjusts the interface corresponding to the fourth path signal DO4 from the pos2 (second post-mark) gear position to the pre (pre-mark) gear position.

[0192] At the fourth moment, the coefficient weighting unit circuit collects the signal of the pos2 (second post-mark) gear of the first path signal D01, the coefficient weighting unit circuit collects the signal of the pos1 (first post-mark) gear of the second path signal D02, the coefficient weighting unit circuit collects the signal of the main (main mark) gear of the third path signal D03, and the coefficient weighting unit circuit collects the signal of the pre (pre-mark) gear of the fourth path signal D04. At this time, according to the tap coefficients preset by each differential unit, the weighted sum of these signals is obtained to obtain the output signal.

[0193] The polling unit circuit is a digital circuit running in the signal equalization circuit.

[0194] In this embodiment, the polling unit circuit is used to control the connection between the master / slave processing unit circuit and the coefficient weighting unit circuit in the signal equalization circuit. It is a pre-written program. When the signal equalization circuit receives a signal, the rising edge detection unit, the counter unit, the modulo 4 unit, the base conversion unit, and the shift unit in the polling unit circuit start to operate, and control each sub-signal in the master / slave processing unit circuit to be transmitted to the corresponding interface in the coefficient weighting unit circuit. The shift circuit realizes the transmission of signals and the weighting of coefficients according to the corresponding relationship between the gear position and the interface of each sub-signal in a shift cycle specified in Table 1.

[0195] In this embodiment, based on the half-rate structure technology, a two-level design is used in the master / slave processing circuit, and the polling technology is combined to realize high-speed NRZ FFE. The half-rate structure technology reduces the clock frequency of the traditional NRZ FFE circuit by half, reduces the design difficulty of the clock circuit and the influence of clock jitter on the data signal. The master-slave structure technology divides the single data transmission path into multiple paths, effectively reduces the interference problem between data signals, and can greatly improve the compensation effect of the circuit, thereby expanding the transmission rate and transmission line.

[0196] The signal equalization circuit in this embodiment can also be applied to a variety of interconnected scenarios, such as GPU (graphics processing), AI (Artificial Intelligence), etc. Using the signal equalization circuit in this embodiment in a GPU chip can effectively improve the speed of graphics processing and the inter-code interference between various image signals during graphics processing, thereby improving the accuracy of graphics processing. Using the signal equalization circuit in this embodiment in an AI chip can improve the speed of operation and the accuracy of AI during the training process and use of AI.

[0197] Based on the same inventive concept, another embodiment of the present application provides an interface, which includes the signal equalization circuit as described in the first aspect of the embodiment of the present application.

[0198] Based on the same inventive concept, another embodiment of the present application provides a system on chip, which includes implementing communication through an interface, and the interface in the system on chip includes the signal equalization circuit as described in the first aspect of the embodiment of the present application.

[0199] Based on the same inventive concept, another embodiment of the present application provides a server, wherein the server runs a system on a chip, and the communication interface of the system on a chip in the server includes the signal equalization circuit as described in the first aspect of the embodiment of the present application.

[0200] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0201] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0202] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0203] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0204] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0205] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0206] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0207] The signal equalization circuit provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A signal equalization circuit, characterized in that: The circuit comprises: a master / slave processing unit circuit, a coefficient weighting unit circuit, and a polling unit circuit; The master / slave processing unit circuit is used to receive an input signal, split the input signal into four sub-signals, and output the four sub-signals to the coefficient weighting unit circuit; The coefficient weighting unit circuit is used to receive the four-path sub-signals, perform weighted processing on the four-path sub-signals, and obtain an output signal; The polling unit circuit is used to control the signal transmission between the master / slave processing unit circuit and the coefficient weighting unit circuit; Wherein, each differential unit in the coefficient weighting unit circuit receives one of the four sub-signals according to the gear position corresponding to the current moment, and performs weighted processing on the four sub-signals according to the weight corresponding to each differential unit to obtain the output signal, and the gear position includes a front mark, a main mark, a first rear mark, and a second rear mark; The master / slave processing unit circuit comprises a master processing unit circuit and a slave processing unit circuit; The main processing unit circuit includes a first-level main processing unit circuit and a second-level main processing unit circuit; The first-stage main processing unit circuit is used to convert the input signal into a first output sub-signal; The second-stage main processing unit circuit is used to receive the first output sub-signal, and split the first output sub-signal into a first path sub-signal and a third path sub-signal; The slave processing unit circuit includes a first-level slave processing unit circuit and a second-level slave processing unit circuit; The first-stage slave processing unit circuit is used to convert the input signal into a second output sub-signal; The second-stage slave processing unit circuit is used for receiving the second output sub-signal, and splitting the second output sub-signal into a second path sub-signal and a fourth path sub-signal; The polling unit circuit includes a rising edge detection unit, a counter unit, a modulo 4 unit, a base conversion unit, and a shift unit; The rising edge detection unit is used to detect the clock signal sent by the clock circuit; When the rising edge detection unit detects that the clock circuit sends a clock signal, the rising edge detection unit sends notification information to the counter unit; The counter unit is used to record the number of rising edge signals of the clock signal; The counter unit increases the number of recorded rising edge signals by one when receiving the notification information sent by the rising edge detection unit; The module 4 unit is used to limit the polling unit circuit to receive four rising edge signals as one shift cycle; The base conversion unit is used to convert a decimal number into a binary number; The base conversion unit obtains the decimal number recorded in the counter unit; The base conversion unit converts the decimal number into a binary number; The shift unit is used to control the signal transmission of the four-way sub-signals; The shift unit switches the four sub-signals to corresponding interfaces according to the binary number obtained by the base conversion unit.

2. The circuit according to claim 1, characterized in that The first-stage main processing unit circuit includes a first trigger and a second trigger; The output terminal of the first trigger is connected to the input terminal of the second trigger.

3. The circuit according to claim 1, characterized in that The second-stage main processing unit circuit includes a fifth trigger, a sixth trigger, a seventh trigger, and an eighth trigger; The input terminal of the fifth trigger is connected to the output terminal of the second trigger; The output terminal of the fifth trigger is connected to the input terminal of the sixth trigger; An input terminal of the seventh trigger is connected to an output terminal of the second trigger; The output terminal of the seventh flip-flop is connected to the input terminal of the eighth flip-flop.

4. The circuit according to claim 1, characterized in that The first-stage slave processing unit circuit includes a third trigger and a fourth trigger; The output terminal of the third trigger is connected to the input terminal of the fourth trigger.

5. The circuit according to claim 1, characterized in that The second-stage slave processing unit circuit includes a ninth trigger, a tenth trigger, an eleventh trigger, and a twelfth trigger; The input end of the ninth trigger is connected to the output end of the fourth trigger; The output terminal of the ninth trigger is connected to the input terminal of the tenth trigger; The input terminal of the eleventh trigger is connected to the output terminal of the fourth trigger; The output terminal of the eleventh flip-flop is connected to the input terminal of the twelfth flip-flop.

6. The circuit according to claim 1, characterized in that The coefficient weighting unit circuit includes a first differential unit, a second differential unit, a third differential unit, a fourth differential unit, and a signal amplitude control resistor; The first differential unit is used to receive a first path of sub-signals among the four paths of sub-signals; The second differential unit is used to receive a fourth path of sub-signals among the four paths of sub-signals; The third differential unit is used to receive a third path of sub-signals among the four paths of sub-signals; The fourth differential unit is used to receive the second path sub-signal among the four paths sub-signals; The signal amplitude control resistor is used to control the swing amplitude of the output signal; The signal amplitude control resistor is connected to the first differential unit, the second differential unit, the third differential unit, and the fourth differential unit.

7. The circuit according to claim 6, characterized in that The first differential unit includes a first differential input port, a second differential input port, and a first constant current source; The first differential input port is used to receive the positive signal of the first path signal; The second differential input port is used to receive the negative signal of the first path signal; The first constant current source is used to provide a stable current for the coefficient weighting unit circuit.

8. The circuit according to claim 6, characterized in that The second differential unit includes a third differential input port, a fourth differential input port, and a second constant current source; The third differential input port is used to receive the positive signal of the fourth path signal; The fourth differential input port is used to receive the negative signal of the fourth path signal; The second constant current source is used to provide a stable current for the coefficient weighting unit circuit.

9. The circuit according to claim 6, characterized in that The third differential unit includes a fifth differential input port, a sixth differential input port, and a third constant current source; The fifth differential input port is used to receive the positive signal of the third path signal; The sixth differential input port is used to receive the negative signal of the third path signal; The third constant current source is used to provide a stable current for the coefficient weighting unit circuit.

10. The circuit according to claim 6, characterized in that The fourth differential unit includes a seventh differential input port, an eighth differential input port, and a fourth constant current source; The seventh differential input port is used to receive the positive signal of the second path signal; The eighth differential input port is used to receive the negative signal of the second path signal; The fourth constant current source is used to provide a stable current for the coefficient weighting unit circuit.

11. The circuit according to claim 1, characterized in that The polling unit circuit is a digital circuit running in the signal equalization circuit.

12. An interface, characterized in that: The interface comprises a signal equalization circuit as claimed in any one of claims 1-11.

13. A system on chip, the system on chip comprising a communication interface, characterized in that: The interface in the system on chip comprises the signal equalization circuit as claimed in any one of claims 1-11.

14. A server, wherein the server runs a system on a chip, characterized in that: The interface of the system on chip in the server includes the signal equalization circuit as described in any one of claims 1-11.

Images