A miniaturized low-insertion-loss high-rejection low-pass filter
By designing a miniaturized low-insertion loss high-suppression low-pass filter in electronic devices, using nine-layer circuit layer and low-temperature co-fired ceramic technology, the problem of difficulty in achieving low-insertion loss and high-suppression in limited space is solved, and the problem of low-insertion loss and high-suppression in limited space is realized. Efficient RF performance and stability.
Patent Information
- Application Number
- CN202410655751.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-24
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2044-05-24
AI Technical Summary
In the limited electronic equipment space, it is difficult to effectively ensure the performance of low-pass filters with low insertion loss and high rejection.
A miniaturized low insertion loss high suppression low pass filter was designed. By setting up nine-layer circuit layers in a single dielectric body, using low-temperature co-fired ceramic technology and multi-layer printed circuit board technology, combined with copper or palladium silver materials, it can achieve Low insertion loss and high suppression effect.
It realizes efficient low interpolation loss and high suppression in a very small volume, reduces signal interference in the RF system, improves process stability and applicability, and is suitable for high-integration electronic devices.
Smart Images
Figure CN118472576B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of low-pass filters, and in particular to a miniaturized low-insertion-loss and high-inhibition low-pass filter. Background Art
[0002] The current microwave systems are developing towards high integration, high performance and small size, and two or more channels are often integrated in one system. In order to reduce the system size and reduce the total power consumption of the system, in recent years, with the maturity of radio frequency technology, electronic devices such as mobile phones can reduce the noise of the received signal at the antenna port through low-pass filter technology. At this time, high-suppression low-pass filter components are needed. However, as the functions of electronic devices such as mobile phones become more and more powerful, the space for electronic devices and radio frequency devices and electronic devices has become very limited. How to ensure low insertion loss and high suppression in the limited space of electronic devices is an important issue. Summary of the invention
[0003] In view of the above-mentioned deficiencies in the prior art, a miniaturized low-insertion-loss and high-rejection low-pass filter provided by the present invention solves the problem that low insertion loss and high rejection cannot be effectively guaranteed in the limited space of existing electronic equipment.
[0004] In order to achieve the above-mentioned purpose of the invention, the technical solution adopted by the present invention is: a miniaturized low-insertion-loss and high-suppression low-pass filter, comprising a low-pass filter housing and a dielectric body, the dielectric body is located inside the low-pass filter housing, a circuit layer is arranged inside the dielectric body, and an input port, an output port, a first ground port, a second ground port, a first empty port and a second empty port connected to the line of the circuit layer are arranged at the bottom of the low-pass filter housing, the input port and the first empty port are symmetrically arranged, the output port and the second empty port are symmetrically arranged, and the first ground port and the second ground port are symmetrically arranged.
[0005] The beneficial effect of the above scheme is: the present invention provides a miniaturized low-insertion-loss and high-inhibition low-pass filter, which is built into a single dielectric body and can be processed into a patch component based on lamination technology, thereby achieving a low-insertion-loss and high-inhibition low-pass filter effect in an extremely small volume, solving the problem that low insertion loss and high inhibition cannot be effectively guaranteed in the limited space of existing electronic equipment.
[0006] Further, the circuit layer includes, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer and a ninth circuit layer;
[0007] The first circuit layer is connected to the second circuit layer and the sixth circuit layer respectively, the second circuit layer is connected to the third circuit layer, the third circuit layer is connected to the fourth circuit layer, the fourth circuit layer is connected to the fifth circuit layer, the fifth circuit layer is connected to the eighth circuit layer, the seventh circuit layer is connected to the ninth circuit layer, the eighth circuit layer is connected to the input port, the output port, the first empty port and the second empty port respectively, and the ninth circuit layer is connected to the first ground port and the second ground port respectively.
[0008] The beneficial effect of the above further scheme is: the low-pass filter designed by the present invention includes nine circuit layers, and the nine circuit layers are built into a single dielectric body, realizing a low-insertion-loss and high-suppression low-pass filter in an extremely small volume. On the premise of ensuring that its electrical performance is not affected, the tolerance of the processing technology is maximized, and higher process stability and consistency are achieved. It is also easy to be integrated with other circuit modules and has high applicability.
[0009] Further, the first circuit layer includes a first electrode plate, a first via hole, a second via hole and a third via hole;
[0010] The second circuit layer includes a second electrode plate, a third electrode plate, a third via hole, a fourth via hole and a fifth via hole;
[0011] The third circuit layer includes a fourth electrode plate, a fifth electrode plate, a third via hole, a sixth via hole and a seventh via hole;
[0012] The fourth circuit layer includes a sixth electrode plate, a seventh electrode plate, a third via hole, an eighth via hole and a ninth via hole;
[0013] The fifth circuit layer includes an eighth electrode plate, a ninth electrode plate, a third via hole, an eighth via hole and a ninth via hole;
[0014] The sixth circuit layer includes a tenth electrode plate, an eighth via hole and a ninth via hole;
[0015] The seventh circuit layer includes an eleventh electrode plate, an eighth via hole, a ninth via hole, a tenth via hole and an eleventh via hole;
[0016] The eighth circuit layer includes a twelfth electrode plate, a thirteenth electrode plate, a fourteenth electrode plate, an eighth via hole, a ninth via hole, a tenth via hole, an eleventh via hole, a twelfth via hole and a thirteenth via hole;
[0017] The ninth circuit layer includes a fifteenth electrode plate, an eighth via hole, a ninth via hole, an eleventh via hole, a twelfth via hole, a thirteenth via hole and a fourteenth via hole;
[0018] The first electrode plate is connected to the second electrode plate through a first via hole, the first electrode plate is connected to the third electrode plate through a second via hole, the first electrode plate is connected to the tenth electrode plate through a third via hole; the second electrode plate is connected to the fourth electrode plate through a fourth via hole; the third electrode plate is connected to the fifth electrode plate through a fifth via hole; the fourth electrode plate is connected to the sixth electrode plate through a sixth via hole; the fifth electrode plate is connected to the seventh electrode plate through a seventh via hole; the sixth electrode plate, the eighth electrode plate and the twelfth electrode plate are connected through an eighth via hole, and the seventh electrode plate, the ninth electrode plate and the twelfth electrode plate are connected through an eighth via hole. The electrode plate is connected to the thirteenth electrode plate through the ninth via hole; the eleventh electrode plate is connected to the fifteenth electrode plate through the tenth via hole and the eleventh via hole, the twelfth electrode plate is connected to the input port through the eighth via hole, the thirteenth electrode plate is connected to the output port through the ninth via hole, the fourteenth electrode plate is connected to the first vacant port through the twelfth via hole, the fourteenth electrode plate is connected to the second vacant port through the thirteenth via hole, the fifteenth electrode plate is connected to the second ground port through the eleventh via hole, and the fifteenth electrode plate is connected to the first ground port through the fourteenth via hole.
[0019] The beneficial effect of the above further scheme is: through the above technical scheme, a specific structure of each circuit layer is provided, and by adopting low-temperature co-fired ceramic technology, the structure is built into the low-pass filter dielectric body. The low-pass filter has a small size, a low profile, and high suppression, which is beneficial to reducing interference from surrounding radio frequency devices. It has excellent performance such as high Q value, small size, low insertion loss, and high suppression, which further reduces signal interference of the radio frequency system.
[0020] Furthermore, the first circuit layer, the second circuit layer, the third circuit layer and the fourth circuit layer constitute an inductance region unit, and the fifth circuit layer, the sixth circuit layer, the seventh circuit layer, the eighth circuit layer and the ninth circuit layer constitute a capacitance region unit.
[0021] Further, the first electrode plate, the second electrode plate, the fourth electrode plate, the first via hole and the fourth via hole constitute a first equivalent inductance L1;
[0022] The first electrode plate, the third electrode plate, the fifth electrode plate, the second via hole and the fifth via hole constitute a second equivalent inductance L2;
[0023] The eleventh electrode plate and the twelfth electrode plate constitute a first equivalent capacitor C1;
[0024] The eighth electrode plate and the tenth electrode plate constitute a second equivalent capacitor C2;
[0025] The tenth electrode plate and the eleventh electrode plate constitute a third equivalent capacitor C3;
[0026] The ninth electrode plate and the tenth electrode plate constitute a fourth equivalent capacitor C4;
[0027] The eleventh electrode plate and the thirteenth electrode plate constitute a fifth equivalent capacitor C5;
[0028] One end of the second equivalent capacitor C2 is respectively connected to one end of the first equivalent capacitor C1, the input port and one end of the first equivalent inductor L1, and the other end is respectively connected to the other end of the first equivalent inductor L1, one end of the third equivalent capacitor C3, one end of the second equivalent inductor L2 and one end of the fourth equivalent capacitor C4. The other end of the fourth equivalent capacitor C4 is respectively connected to the other end of the second equivalent inductor L2, one end of the fifth equivalent capacitor C5 and the output port, and the other end of the first equivalent capacitor C1, the other end of the third equivalent capacitor C3 and the other end of the fifth equivalent capacitor C5 are all grounded.
[0029] The beneficial effect of the above further scheme is: the low-pass filter designed by the present invention reduces the interference of surrounding RF devices through modularization, optimized performance, integrated inductance, enhanced suppression and filtering effects, etc., and has excellent performance such as high Q value, small size, low insertion loss, and high suppression, further improving the working efficiency of the RF system.
[0030] Furthermore, the dielectric body is a single dielectric body, and the single dielectric body is manufactured based on a multi-layer printed circuit board process or a low-temperature co-fired ceramic technology.
[0031] The beneficial effect of the above further solution is that the present invention can manufacture a single dielectric body through a multi-layer printed circuit board process or a low-temperature co-fired ceramic technology.
[0032] Furthermore, the material of the low-pass filter is copper or palladium silver.
[0033] The beneficial effect of the above further solution is that the present invention uses a metal material with high electrical conductivity, such as copper or palladium silver, to make a low-pass filter. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 It is a schematic diagram of the appearance of the low-pass filter of the present invention.
[0035] Figure 2 It is a schematic diagram of the internal structure of the low-pass filter of the present invention.
[0036] Figure 3 It is a schematic diagram of the first layer circuit of the low-pass filter of the present invention.
[0037] Figure 4 It is a schematic diagram of the second layer circuit of the low-pass filter of the present invention.
[0038] Figure 5 It is a schematic diagram of the third layer circuit of the low-pass filter of the present invention.
[0039] Figure 6 It is a schematic diagram of the fourth circuit of the low-pass filter of the present invention.
[0040] Figure 7 It is a schematic diagram of the fifth circuit of the low-pass filter of the present invention.
[0041] Figure 8 This is a schematic diagram of the sixth circuit of the low-pass filter of the present invention.
[0042] Fig. 9 This is a schematic diagram of the seventh circuit of the low-pass filter of the present invention.
[0043] Fig.10 This is a schematic diagram of the eighth circuit of the low-pass filter of the present invention.
[0044] Fig.11 It is a ninth circuit diagram of the low-pass filter of the present invention.
[0045] Fig.12 It is an equivalent principle diagram of the low-pass filter of the present invention.
[0046] Fig.13 It is a suppression response curve diagram of the low-pass filter of the present invention.
[0047] Fig.14 It is an insertion loss response curve diagram of the low-pass filter of the present invention.
[0048] Wherein: 01, low-pass filter housing; 02, input port; 03, output port; 04, first ground port; 05, second ground port; 06, first empty port; 07, second empty port; 1, first electrode plate; 2, second electrode plate; 3, third electrode plate; 4, fourth electrode plate; 5, fifth electrode plate; 6, sixth electrode plate; 7, seventh electrode plate; 8, eighth electrode plate; 9, ninth electrode plate; 10, tenth electrode plate; 11, eleventh electrode plate electrode plate; 12, twelfth electrode plate; 13, thirteenth electrode plate; 14, fourteenth electrode plate; 15, fifteenth electrode plate; 16, first via hole; 17, second via hole; 18, third via hole; 19, fourth via hole; 20, fifth via hole; 21, sixth via hole; 22, seventh via hole; 23, eighth via hole; 24, ninth via hole; 25, tenth via hole; 26, eleventh via hole; 27, twelfth via hole; 28, thirteenth via hole; 29, fourteenth via hole. DETAILED DESCRIPTION
[0049] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.
[0050] like Figure 1As shown, a miniaturized low-insertion-loss high-suppression low-pass filter comprises a low-pass filter housing 01 and a dielectric body, wherein the dielectric body is located inside the low-pass filter housing 01, a circuit layer is arranged inside the dielectric body, an input port 02, an output port 03, a first grounding port 04, a second grounding port 05, a first empty port 06 and a second empty port 07 connected to the circuit layer are arranged at the bottom of the low-pass filter housing, the input port 02 and the first empty port 06 are symmetrically arranged, the output port 03 and the second empty port 07 are symmetrically arranged, and the first grounding port 04 and the second grounding port 05 are symmetrically arranged.
[0051] like Figure 2 As shown, the circuit layers include, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer and a ninth circuit layer;
[0052] The first circuit layer is connected to the second circuit layer and the sixth circuit layer respectively, the second circuit layer is connected to the third circuit layer, the third circuit layer is connected to the fourth circuit layer, the fourth circuit layer is connected to the fifth circuit layer, the fifth circuit layer is connected to the eighth circuit layer, the seventh circuit layer is connected to the ninth circuit layer, the eighth circuit layer is connected to the input port 02, the output port 03, the first empty port 06 and the second empty port 07 respectively, and the ninth circuit layer is connected to the first ground port 04 and the second ground port 05 respectively.
[0053] like Figure 3 As shown, the first circuit layer includes a first electrode plate 1, a first via hole 16, a second via hole 17 and a third via hole 18;
[0054] like Figure 4 As shown, the second circuit layer includes a second electrode plate 2, a third electrode plate 3, a third via hole 18, a fourth via hole 19 and a fifth via hole 20;
[0055] like Figure 5 As shown, the third circuit layer includes a fourth electrode plate 4, a fifth electrode plate 5, a third via hole 18, a sixth via hole 21 and a seventh via hole 22;
[0056] like Figure 6 As shown, the fourth circuit layer includes a sixth electrode plate 6, a seventh electrode plate 7, a third via hole 18, an eighth via hole 23 and a ninth via hole 24;
[0057] like Figure 7 As shown, the fifth circuit layer includes an eighth electrode plate 8, a ninth electrode plate 9, a third via hole 18, an eighth via hole 23 and a ninth via hole 24;
[0058] like Figure 8As shown, the sixth circuit layer includes a tenth electrode plate 10, an eighth via hole 23 and a ninth via hole 24;
[0059] like Fig. 9 As shown, the seventh circuit layer includes an eleventh electrode plate 11, an eighth via hole 23, a ninth via hole 24, a tenth via hole 25 and an eleventh via hole 26;
[0060] like Fig.10 As shown, the eighth circuit layer includes a twelfth electrode plate 12, a thirteenth electrode plate 13, a fourteenth electrode plate 14, an eighth via hole 23, a ninth via hole 24, a tenth via hole 25, an eleventh via hole 26, a twelfth via hole 27 and a thirteenth via hole 28;
[0061] like Fig.11 As shown, the ninth circuit layer includes a fifteenth electrode plate 15, an eighth via hole 23, a ninth via hole 24, an eleventh via hole 26, a twelfth via hole 27, a thirteenth via hole 28 and a fourteenth via hole 29;
[0062] The first electrode plate 1 is connected to the second electrode plate 2 through a first via 16, the first electrode plate 1 is connected to the third electrode plate 3 through a second via 17, the first electrode plate 1 is connected to the tenth electrode plate 10 through a third via 18; the second electrode plate 2 is connected to the fourth electrode plate 4 through a fourth via 19; the third electrode plate 3 is connected to the fifth electrode plate 5 through a fifth via 20; the fourth electrode plate 4 is connected to the sixth electrode plate 6 through a sixth via 21; the fifth electrode plate 5 is connected to the seventh electrode plate 7 through a seventh via 22; the sixth electrode plate 6, the eighth electrode plate 8 are connected to the twelfth electrode plate 12 through an eighth via 23, the seventh electrode plate 7, the ninth electrode plate 9 are connected to the twelfth electrode plate 13 through an eighth via 24, The thirteenth electrode plate 13 is connected through the ninth via hole 24; the eleventh electrode plate 11 and the fifteenth electrode plate 15 are connected through the tenth via hole 25 and the eleventh via hole 26, the twelfth electrode plate 12 is connected to the input port 02 through the eighth via hole 23, the thirteenth electrode plate 13 is connected to the output port 03 through the ninth via hole 24, the fourteenth electrode plate 14 is connected to the first empty port 06 through the twelfth via hole 27, the fourteenth electrode plate 14 is connected to the second empty port 07 through the thirteenth via hole 28, the fifteenth electrode plate 15 is connected to the second ground port 05 through the eleventh via hole 26, and the fifteenth electrode plate 15 is connected to the first ground port 04 through the fourteenth via hole 29.
[0063] The first circuit layer, the second circuit layer, the third circuit layer and the fourth circuit layer constitute an inductor area unit, and the fifth circuit layer, the sixth circuit layer, the seventh circuit layer, the eighth circuit layer and the ninth circuit layer constitute a capacitor area unit. The capacitor unit and the inductor unit constitute a low insertion loss high suppression low pass filter.
[0064] like Fig.12 As shown, the first electrode plate 1, the second electrode plate 2, the fourth electrode plate 4, the first via hole 16 and the fourth via hole 19 constitute a first equivalent inductance L1;
[0065] The first electrode plate 1, the third electrode plate 3, the fifth electrode plate 5, the second via hole 17 and the fifth via hole 20 constitute a second equivalent inductance L2;
[0066] The eleventh electrode plate 11 and the twelfth electrode plate 12 form a first equivalent capacitor C1;
[0067] The eighth electrode plate 8 and the tenth electrode plate 10 constitute a second equivalent capacitor C2;
[0068] The tenth electrode plate 10 and the eleventh electrode plate 11 constitute a third equivalent capacitor C3;
[0069] The ninth electrode plate 9 and the tenth electrode plate 10 constitute a fourth equivalent capacitor C4;
[0070] The eleventh electrode plate 11 and the thirteenth electrode plate 13 form a fifth equivalent capacitor C5.
[0071] One end of the second equivalent capacitor C2 is respectively connected to one end of the first equivalent capacitor C1, the input port 02 and one end of the first equivalent inductor L1, and the other end is respectively connected to the other end of the first equivalent inductor L1, one end of the third equivalent capacitor C3, one end of the second equivalent inductor L2 and one end of the fourth equivalent capacitor C4. The other end of the fourth equivalent capacitor C4 is respectively connected to the other end of the second equivalent inductor L2, one end of the fifth equivalent capacitor C5 and the output port 03. The other end of the first equivalent capacitor C1, the other end of the third equivalent capacitor C3 and the other end of the fifth equivalent capacitor C5 are all grounded.
[0072] The dielectric body is a single dielectric body, and the single dielectric body is manufactured based on a multi-layer printed circuit board process or a low-temperature co-fired ceramic technology.
[0073] The material of the low-pass filter is copper or palladium silver.
[0074] In one embodiment of the present invention, the thickness from the first circuit layer to the top of the low-pass filter housing is 50 μm;
[0075] The thickness from the second circuit layer to the first circuit layer is 30 μm;
[0076] The thickness from the third circuit layer to the second circuit layer is 30 μm;
[0077] The thickness from the fourth circuit layer to the third circuit layer is 30 μm;
[0078] The thickness from the fifth circuit layer to the fourth circuit layer is 30 μm;
[0079] The thickness of the sixth circuit layer to the fifth circuit layer is 30 μm;
[0080] The thickness from the seventh circuit layer to the sixth circuit layer is 30 μm;
[0081] The thickness of the eighth circuit layer to the seventh circuit layer is 30 μm;
[0082] The thickness of the ninth circuit layer to the eighth circuit layer is 30 μm;
[0083] The thickness from the bottom circuit layer to the ninth circuit layer is 30 μm;
[0084] There is a marking 47 symbol on the top of the low-pass filter housing to identify the position of each port.
[0085] In this embodiment, a ceramic dielectric body is made by low temperature co-fired ceramic technology, and its volume is 1.0mm×0.5mm×0.4mm. The low-pass filter module is placed in the ceramic dielectric body and sintered at a temperature of 890℃±20℃, which can realize the miniaturization, low insertion loss and high suppression of the low-pass filter on the three-dimensional circuit substrate. Palladium silver is used as the embedded metal material and placed in nine circuit layers, which is conducive to improving the quality factor of the circuit system, and no oxidation will occur during the sintering process, and no electroplating protection is required.
[0086] The dielectric constant of the dielectric material used in the low-insertion-loss, high-suppression low-pass filter circuit can vary within a wide range. The physical size of the equivalent component is inversely proportional to the square root of the dielectric constant of the material, that is, the larger the dielectric constant, the smaller the required component size. Therefore, in this embodiment, a dielectric material with a dielectric constant of 32 and a dielectric loss tangent of 0.006 is used.
[0087] like Fig.13 and 14 As shown, based on the equivalent circuit of the low-insertion-loss and high-suppression low-pass filter, the low-pass filter of this embodiment has an insertion loss of less than 0.48 dB in the operating frequency band of 1695 to 2180 MHz, and a triple frequency suppression of more than 48 dB, which reflects the stability of the transmission characteristics of the low-pass filter.
[0088] The present invention includes nine layers of circuits and is built into a single dielectric material. The volume of the low-pass filter is only 1.0mm×0.5mm×0.4mm. It can be processed into a patch component based on the lamination technology, and achieves a low-insertion-loss and high-inhibition low-pass filter effect in a very small volume. The low-pass filter is small in size and low in profile, which is conducive to reducing the interference of surrounding RF devices. It has excellent performance such as high Q value, small volume, low insertion loss, and high inhibition, and further improves the working efficiency of the RF system. On the premise of ensuring that its electrical performance is not affected, the tolerance of the processing technology is maximized, achieving higher process stability and consistency, and it is easy to integrate with other circuit modules, with high applicability.
[0089] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the invention.
Claims
1. A miniaturized low-insertion-loss high-rejection low-pass filter, characterized in that: The invention comprises a low-pass filter housing (01) and a dielectric body, wherein the dielectric body is located inside the low-pass filter housing (01), a circuit layer is arranged inside the dielectric body, and an input port (02), an output port (03), a first grounding port (04), a second grounding port (05), a first empty port (06) and a second empty port (07) connected to the circuit of the circuit layer are arranged at the bottom of the low-pass filter housing, the input port (02) and the first empty port (06) are arranged symmetrically, the output port (03) and the second empty port (07) are arranged symmetrically, and the first grounding port (04) and the second grounding port (05) are arranged symmetrically; The circuit layers include, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer and a ninth circuit layer; The first circuit layer is connected to the second circuit layer and the sixth circuit layer respectively, the second circuit layer is connected to the third circuit layer, the third circuit layer is connected to the fourth circuit layer, the fourth circuit layer is connected to the fifth circuit layer, the fifth circuit layer is connected to the eighth circuit layer, the seventh circuit layer is connected to the ninth circuit layer, the eighth circuit layer is connected to the input port (02), the output port (03), the first idle port (06) and the second idle port (07) respectively, and the ninth circuit layer is connected to the first ground port (04) and the second ground port (05) respectively; The first circuit layer comprises a first electrode plate (1), a first via hole (16), a second via hole (17) and a third via hole (18); The second circuit layer comprises a second electrode plate (2), a third electrode plate (3), a third via hole (18), a fourth via hole (19) and a fifth via hole (20); The third circuit layer comprises a fourth electrode plate (4), a fifth electrode plate (5), a third via hole (18), a sixth via hole (21) and a seventh via hole (22); The fourth circuit layer comprises a sixth electrode plate (6), a seventh electrode plate (7), a third via hole (18), an eighth via hole (23) and a ninth via hole (24); The fifth circuit layer comprises an eighth electrode plate (8), a ninth electrode plate (9), a third via hole (18), an eighth via hole (23) and a ninth via hole (24); The sixth circuit layer comprises a tenth electrode plate (10), an eighth via hole (23) and a ninth via hole (24); The seventh circuit layer comprises an eleventh electrode plate (11), an eighth via hole (23), a ninth via hole (24), a tenth via hole (25) and an eleventh via hole (26); The eighth circuit layer comprises a twelfth electrode plate (12), a thirteenth electrode plate (13), a fourteenth electrode plate (14), an eighth via hole (23), a ninth via hole (24), a tenth via hole (25), an eleventh via hole (26), a twelfth via hole (27) and a thirteenth via hole (28); The ninth circuit layer comprises a fifteenth electrode plate (15), an eighth via hole (23), a ninth via hole (24), an eleventh via hole (26), a twelfth via hole (27), a thirteenth via hole (28) and a fourteenth via hole (29); The first electrode plate (1) is connected to the second electrode plate (2) through a first via hole (16), the first electrode plate (1) is connected to the third electrode plate (3) through a second via hole (17), the first electrode plate (1) is connected to the tenth electrode plate (10) through a third via hole (18); the second electrode plate (2) is connected to the fourth electrode plate (4) through a fourth via hole (19); the third electrode plate (3) is connected to the fifth electrode plate (5) through a fifth via hole (20); the fourth electrode plate (4) is connected to the sixth electrode plate (6) through a sixth via hole (21); the fifth electrode plate (5) is connected to the seventh electrode plate (7) through a seventh via hole (22); the sixth electrode plate (6), the eighth electrode plate (8) and the twelfth electrode plate (12) are connected through an eighth via hole (23), the seventh electrode plate (7), the ninth electrode plate (9) are connected to the twelfth electrode plate (12) through an eighth via hole (24); ) is connected to the thirteenth electrode plate (13) through the ninth via hole (24); the eleventh electrode plate (11) is connected to the fifteenth electrode plate (15) through the tenth via hole (25) and the eleventh via hole (26); the twelfth electrode plate (12) is connected to the input port (02) through the eighth via hole (23); the thirteenth electrode plate (13) is connected to the output port (03) through the ninth via hole (24); the fourteenth electrode plate (14) is connected to the first vacant port (06) through the twelfth via hole (27); the fourteenth electrode plate (14) is connected to the second vacant port (07) through the thirteenth via hole (28); the fifteenth electrode plate (15) is connected to the second ground port (05) through the eleventh via hole (26); and the fifteenth electrode plate (15) is connected to the first ground port (04) through the fourteenth via hole (29).
2. The miniaturized low insertion loss high rejection low pass filter according to claim 1, characterized in that: The first circuit layer, the second circuit layer, the third circuit layer and the fourth circuit layer constitute an inductance area unit, and the fifth circuit layer, the sixth circuit layer, the seventh circuit layer, the eighth circuit layer and the ninth circuit layer constitute a capacitance area unit.
3. The miniaturized low insertion loss high rejection low pass filter according to claim 1, characterized in that: The first electrode plate (1), the second electrode plate (2), the fourth electrode plate (4), the first via hole (16) and the fourth via hole (19) constitute a first equivalent inductance L1; The first electrode plate (1), the third electrode plate (3), the fifth electrode plate (5), the second via hole (17) and the fifth via hole (20) constitute a second equivalent inductance L2; The eleventh electrode plate (11) and the twelfth electrode plate (12) form a first equivalent capacitor C1; The eighth electrode plate (8) and the tenth electrode plate (10) form a second equivalent capacitor C2; The tenth electrode plate (10) and the eleventh electrode plate (11) form a third equivalent capacitor C3; The ninth electrode plate (9) and the tenth electrode plate (10) form a fourth equivalent capacitor C4; The eleventh electrode plate (11) and the thirteenth electrode plate (13) form a fifth equivalent capacitor C5; One end of the second equivalent capacitor C2 is respectively connected to one end of the first equivalent capacitor C1, the input port (02) and one end of the first equivalent inductor L1, and the other end is respectively connected to the other end of the first equivalent inductor L1, one end of the third equivalent capacitor C3, one end of the second equivalent inductor L2 and one end of the fourth equivalent capacitor C4. The other end of the fourth equivalent capacitor C4 is respectively connected to the other end of the second equivalent inductor L2, one end of the fifth equivalent capacitor C5 and the output port (03). The other end of the first equivalent capacitor C1, the other end of the third equivalent capacitor C3 and the other end of the fifth equivalent capacitor C5 are all grounded.
4. The miniaturized low insertion loss high rejection low pass filter according to claim 1, characterized in that: The dielectric body is a single dielectric body, and the single dielectric body is manufactured based on a multi-layer printed circuit board process or a low-temperature co-fired ceramic technology.
5. The miniaturized low insertion loss high rejection low pass filter according to claim 1, characterized in that: The material of the low-pass filter is copper or palladium silver.