A bridge rectifier module packaging structure and processing method using board-level packaging

Abstract

The present invention relates to a bridge rectifier module packaging structure using board-level packaging, including a carrier board and a plurality of chips, the two side surfaces of the carrier board are provided with a pad layer, a plastic sealing layer, an interconnection layer and an external electrode layer in sequence from the inside to the outside, the plastic sealing layer seals and wraps the plurality of chips, and the plastic sealing layer is provided with an internal through hole, and the pad layer, the chip, the plastic sealing layer, the interconnection layer and the external electrode layer are all symmetrically distributed about the center of the carrier board. The bridge rectifier module of the present invention adopts the process of board-level packaging, and the overall structure is a symmetrical stacked structure, the overall structure is stable and the stress is small; compared with the traditional frame structure; the side plate side through hole design can effectively improve the tin creeping effect, and the weldability is significantly enhanced, and the plate side through hole can increase the heat dissipation channel of the product, the heat dissipation area becomes larger, and the heat dissipation capacity of the structure is improved; the design of a plurality of internal through holes increases the heat dissipation channel inside the board-level packaging structure, so that the heat of the chip is easier to dissipate when working, and the tolerance of the internal chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a packaging structure and a processing method of a bridge stack rectifier module using board-level packaging. Background Art

[0002] In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developing towards miniaturization, intelligence, high performance and high reliability. Packaging technology not only affects the performance of products, but also restricts the miniaturization of products. With the continuous miniaturization and integration of chips, the number of chip pins is increasing, the size is getting smaller and smaller, and the requirements for packaging technology in the field of integrated circuits are getting higher and higher. Traditional packaging uses lead frames, patches, wire bonding (wire donding), etc. This traditional packaging process has the disadvantages of low efficiency and high cost, so board-level packaging came into being. Board-level packaging is to replace the traditional wire bonding process through the process flow of printed circuit boards PCB or packaging substrates to improve the overall power density, current tolerance, etc.

[0003] In the current bridge rectifier module, the main structure used is the frame structure, which is formed by cross-welding two copper frames. The product has low structural strength and large dimensions. At the same time, it has low compatibility with chips of different sizes and high processing costs. So how to apply board-level packaging technology to bridge rectifier modules to improve the structural strength and dimensions of bridge rectifier modules has become a technical problem that needs to be solved in the industry. Summary of the invention

[0004] In order to overcome the shortcomings of the existing bridge rectifier module adopting a frame structure, such as low structural strength and large external dimensions, the present invention provides a bridge rectifier module packaging structure and a processing method using board-level packaging.

[0005] The technical solution of the present invention is as follows:

[0006] A bridge rectifier module packaging structure using board-level packaging, characterized in that it includes a carrier board and a plurality of chips, the two side surfaces of the carrier board are provided with a pad layer, a plastic sealing layer, an interconnection layer and an external electrode layer in sequence from the inside to the outside, the plurality of chips are arranged on the pad layer, the plastic sealing layer seals and wraps the chip, the plastic sealing layer is provided with inner through holes corresponding to the pad layer and the chip, a part of the interconnection layer is connected to the pad layer through the corresponding inner through hole to connect to the bottom of the chip, and another part of the interconnection layer is connected to the top of the chip through the corresponding inner through hole;

[0007] The pad layers, chips, plastic packaging layers, interconnection layers and external electrode layers on the two side surfaces of the carrier board are all symmetrically distributed about the center of the carrier board.

[0008] Furthermore, the board edge of the carrier board is provided with a board side through hole, and the board side through hole connects the external electrode layer on the two side boards, the interconnection layer connected to the top of the chip, and the pad layer.

[0009] As a preferred solution of the present invention, the Tg value of the carrier plate is greater than 150° C., and the material of the carrier plate is epoxy resin.

[0010] As a preferred solution of the present invention, the pad layer extends from the bottom of the chip to the edge of the carrier board and is connected to the board-side through-holes at the edge of the board.

[0011] As a preferred solution of the present invention, the chip is soldered to the pad layer by solder paste, or is connected to the pad layer by conductive glue.

[0012] Furthermore, the chip can be soldered to the pad layer in a face-down manner or in a flip-down manner.

[0013] Furthermore, the number of chips on the two side surfaces of the carrier board may be the same or different; and the number of chips may be 1, 2 or more than 2.

[0014] As a preferred solution of the present invention, the material of the plastic sealing layer is epoxy resin.

[0015] As a preferred solution of the present invention, the interconnection layer includes a first interconnection layer and a second interconnection layer, the inner through hole includes a first inner through hole and a second inner through hole, the first inner through hole passes through the plastic packaging layer, and the first inner through hole connects the first interconnection layer and the pad layer; the second inner through hole penetrates the plastic packaging layer to the top of the chip, and the second inner through hole connects the second interconnection layer and the top of the chip.

[0016] Furthermore, the inner through hole is in a truncated cone shape, and the diameter of the outer side of the inner through hole is larger than the diameter of the inner side.

[0017] By adopting the above technical solution, the inner through hole is used as the internal heat dissipation hole of the packaging structure. The small diameter close to the heat source can make the heat flow in the designed direction and transfer from the high temperature area to the low temperature area along the truncated cone-shaped channel, which conforms to the principles of natural convection and heat conduction; the large diameter side is away from the heat source, which can provide a larger heat dissipation surface and more complete contact with the low temperature environment outside, which helps to improve the heat transfer efficiency.

[0018] Optionally, the inner through hole is cylindrical, conical or polygonal.

[0019] Furthermore, the inner through hole is a metallized hole, which is made by chemical copper deposition and then pattern electroplating.

[0020] Optionally, the second inner through hole away from the chip is filled with a copper block or other metal block.

[0021] As a preferred solution of the present invention, the first interconnection layer is arranged at one end of the plastic encapsulation layer corresponding to the pad layer, and the second interconnection layer is arranged at the other end of the plastic encapsulation layer corresponding to the chip.

[0022] As a preferred solution of the present invention, a solder resist area is provided in the middle of the external electrode layer, and the solder resist area isolates a plurality of device electrode areas.

[0023] Furthermore, the material of the solder resist area is resin.

[0024] As a preferred solution of the present invention, a semi-cured layer is provided between the external electrode layer and the interconnection layer.

[0025] Furthermore, the external electrode layer is made of copper, and can be made of copper foil, copper sheet or copper block.

[0026] The present invention also provides a method for processing a bridge stack rectifier module using board-level packaging, which is used to process and form the above-mentioned bridge stack rectifier module packaging structure using board-level packaging, take a carrier board as a carrier, weld chips on both sides of the carrier board, perform plastic sealing to seal the chips and keep the board surface flat, drill holes in the plastic sealing layer and electroplate copper in the holes to achieve interconnection, press-fit to make a metal conductive layer, drill holes on the side of the board and electroplate copper in the holes to interconnect the chips on both sides of the carrier board, etch patterns on the metal conductive layer and electroplate it to obtain the device electrode area; and complete the board-level packaging process.

[0027] As a preferred solution of the present invention, the chip welding on both sides of the carrier board includes the following steps: making pad layers at central symmetrical positions on both sides of the carrier board; and welding the chips to the pad layers on both sides of the carrier board respectively.

[0028] As a preferred solution of the present invention, the plastic encapsulation process to seal and wrap the chip includes the following steps: coating the surface of the plastic encapsulation material carrier board to cover the chip, the pad layer and the partially exposed carrier board; and forming a plastic encapsulation layer after curing to completely wrap the chip.

[0029] By adopting the above technical solution, the plastic encapsulation layer can protect the chip soldered on the carrier board. By completely wrapping the chip in the plastic encapsulation layer, a sealed environment is formed to prevent moisture and pollutants in the air from affecting the chip, thereby improving the reliability and life of the chip. The plastic encapsulation layer also plays a role in electrical insulation to prevent short circuits or accidental contact.

[0030] As a preferred solution of the present invention, the plastic encapsulation layer is drilled and copper is electroplated in the holes to achieve interconnection, including the following steps: drilling holes at positions of the plastic encapsulation layer corresponding to the pad layer, and drilling holes at positions of the plastic encapsulation layer corresponding to the chip; copper is electroplated at the drilled positions to obtain a first inner through hole connecting the pad layer and a second inner through hole connecting the top of the chip; a first interconnection layer is formed on the plastic encapsulation layer by pattern electroplating to connect a plurality of first inner through holes, and a second interconnection layer is formed to connect a plurality of second inner through holes.

[0031] By adopting the above technical solution, the inner through holes of the plastic packaging layer are formed by chemical copper deposition and pattern electroplating to form an interconnection layer on the plastic packaging layer, which can increase more connection points and improve integration without increasing the thickness of the board-level packaging.

[0032] Furthermore, the shapes of the first inner through hole and the second inner through hole are designed to be truncated cones, the side with a smaller diameter of the first inner through hole is connected to the pad layer, and the side with a larger diameter is connected to the first interconnection layer; the side with a smaller diameter of the second inner through hole is connected to the top of the chip, and the side with a larger diameter is connected to the second interconnection layer.

[0033] As a preferred solution of the present invention, the lamination process for producing the metal conductive layer comprises the following steps: laminating a prepreg on the outermost layer of the board; and laminating a copper foil layer on the outer side of the prepreg.

[0034] The present invention according to the above scheme has the following beneficial effects:

[0035] 1. The bridge rectifier module of the present invention adopts the board-level packaging process, and the overall structure is a symmetrical stacked structure, the overall structure is stable, the stress is small, and it is not easy to deform;

[0036] 2. The board-level packaging structure prepared by the present invention has a smaller packaging size, and can package larger chips in the same volume, making it easier to achieve product miniaturization, which is beneficial to terminal applications;

[0037] 3. Compared with the traditional frame structure, the bridge rectifier module of the board-level packaging structure of the present invention has high processing efficiency, a large number of one-time molding, and a more cost-effective; and because the method of designing a separate frame is abandoned, the matching is more flexible, and the chip packaging of different specifications can be realized;

[0038] 4. The through-hole design on the side of the board can effectively improve the tin creeping effect, significantly enhance the solderability, and the through-hole on the side of the board can increase the heat dissipation channels of the product, increase the heat dissipation area, and improve the heat dissipation capacity of the structure;

[0039] 5. The design of several internal through holes increases the heat dissipation channel inside the board-level packaging structure, making it easier to dissipate the heat of the chip when it is working, and improving the tolerance of the internal chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of the present invention;

[0041] Figure 2 It is a structural schematic diagram of the bearing plate of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of the packaging board after the chip is welded;

[0043] Figure 4 This is a schematic diagram of the structure of the package board after plastic sealing;

[0044] Figure 5 This is a schematic diagram of the structure of the packaging board after drilling holes in the plastic sealing layer;

[0045] Figure 6 This is a schematic diagram of the structure of the package board after drilling and copper electroplating;

[0046] Figure 7 This is a schematic diagram of the structure of the package board after the copper layer is pressed;

[0047] Figure 8 This is a schematic diagram of the structure after the side drilling of the package board is completed;

[0048] Fig. 9 This is a schematic diagram of the structure of the package board after the etching pattern is completed.

[0049] In the figure,

[0050] 1. Carrier board; 2. Pad layer; 3. Chip; 4. Plastic packaging layer; 51. First inner through hole; 52. Second inner through hole; 61. First interconnection layer; 62. Second interconnection layer; 7. Semi-cured layer; 8. External electrode layer; 81. Solder resist area; 82. Device electrode area; 9. Board side through hole. DETAILED DESCRIPTION

[0051] In order to better understand the purpose, technical scheme and technical effect of the present invention, the present invention is further explained in conjunction with the accompanying drawings and embodiments. It should be noted that similar numbers and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, it is stated that the embodiments described below are only used to explain the present invention and are not used to limit the present invention.

[0052] It should be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may also be a central element, and when an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time.

[0053] The indicated orientation or position relationship is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the product of the application is usually placed when used, or the orientation or position relationship commonly understood by technical personnel in this field, or the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0054] The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.

[0055] like Figure 1 As shown, a method for processing a bridge rectifier module using board-level packaging includes the following steps:

[0056] Step 1, providing a carrier plate 1;

[0057] like Figure 2 As shown, a carrier board 1 is provided as a basic carrier of the board-level packaging structure, and the packaging process is carried out on the basic carrier. The board surfaces on both sides of the carrier board 1 are covered with copper layers, and the copper layers are used for the subsequent production of pads and interconnection lines. Among them, the carrier board 1 is made of non-metallic materials with high strength, high Tg value and low thermal expansion coefficient. The high-strength carrier board 1 can provide better mechanical support and resist various mechanical stresses that may occur during assembly and use, thereby improving the stability and durability of the overall packaging structure; the carrier board 1 with a high Tg value can still maintain its physical properties unchanged at higher temperatures; when experiencing repeated thermal cycles or temperature changes, the low thermal expansion coefficient helps to reduce material fatigue and structural deformation caused by thermal stress, thereby improving the product life.

[0058] Among them, Tg (Glass Transition Temperature) is an important parameter to measure the heat resistance of the board. Boards with high Tg values ​​have stronger heat resistance and mechanical strength.

[0059] In an optional embodiment, the Tg value of the carrier plate 1 is greater than 150°C.

[0060] In an optional embodiment, the material of the carrying plate 1 is epoxy resin.

[0061] Step 2: welding a plurality of chips 3 on the carrier board 1, specifically comprising the following steps:

[0062] Step 201, making pad layer 2;

[0063] A layer of photosensitive film is attached to the copper layer surface on both sides of the carrier board 1. After exposure and development, at least one group of pads is made on the surface of the copper layer, and the pad group has at least two pads; at the same time, interconnection lines are also made; this step realizes the formation of a pad layer 2 on the carrier board 1, and the pad layer 2 includes pads for chip connection and interconnection lines.

[0064] Step 202: chip welding;

[0065] like Figure 3 As shown, the chip 3 is soldered to the pads on both sides of the carrier board 1, and the soldering material is solder paste or conductive glue with conductive ability. The chip 3 is accurately placed on the pad position of the carrier board 1, and the electrode of the chip 3 must be accurately aligned with the pad on the carrier board 1. If solder paste is used, it is necessary to solder by reflow soldering. The carrier board 1 and the chip 3 pass through the soldering furnace. The solder paste melts at a specific temperature and wets the electrode of the chip 3 and the pad of the carrier board 1. After cooling, it solidifies to form a solder joint. If conductive glue is used, it is directly solidified at room temperature, or the conductive glue is quickly solidified by ultraviolet light irradiation to fix the chip 3 on the carrier board 1.

[0066] Step 3: Plastic encapsulation is performed on both sides of the carrier board 1 to seal a number of chips;

[0067] like Figure 4 As shown, both the front and back sides of the carrier board 1 are plastic-sealed, so that a plastic-sealing layer 4 is formed on both sides of the carrier board 1. The plastic-sealing layer 4 covers the pad layer 2, the chip 3 and the partially exposed carrier board 1, and completely wraps the chip 3, so that the chip 3 is sealed in the plastic-sealing layer 4.

[0068] Among them, the plastic sealing process includes the following steps:

[0069] Step 301, coating;

[0070] The plastic encapsulation material is a liquid epoxy resin or polymer, which is evenly coated on the surface of the carrier board 1 to cover the chip 3 and the pad layer 2; the plastic encapsulation material can also be a powdery structural material or a film layer structural material;

[0071] Step 302, curing;

[0072] Put the carrier plate 1 coated with the plastic sealing material into an oven or use other methods to cure it to form a hard plastic sealing layer 4;

[0073] Step 303: trimming;

[0074] After curing, the plastic encapsulation layer 4 is subjected to correction work such as grinding, cutting or polishing to remove excess material and ensure the flatness and thickness consistency of the plastic encapsulation layer 4. This step is not necessary.

[0075] The plastic encapsulation layer 4 can protect the chip 3 welded on the carrier board 1. By completely wrapping the chip 3 in the plastic encapsulation layer 4, a sealed environment is formed to prevent moisture and pollutants in the air from affecting the chip, thereby improving the reliability and life of the chip. The plastic encapsulation layer 4 also plays a role in electrical insulation to prevent short circuits or accidental contact.

[0076] Step 4, drilling interconnection holes in the plastic sealing layer, and forming an interconnection layer on the outer surface of the plastic sealing layer;

[0077] like Figure 5 As shown, laser drilling is used to drill interconnect holes at the position of the plastic encapsulation layer 4 corresponding to the chip and at the position of the plastic encapsulation layer 4 corresponding to the pad layer 2, and copper plating is performed to metalize the holes to form conductive metallized holes; circuits are formed above the metallized holes by graphic electroplating, and an interconnection layer is formed on the outer surface of the plastic encapsulation layer 4.

[0078] Specifically, an interconnection hole is drilled at a position of the plastic encapsulation layer 4 corresponding to the pad layer 2, where the interconnection hole penetrates the plastic encapsulation layer 4 from the outside to the inside to expose the pad layer 2 at the bottom of the plastic encapsulation layer 4; the interconnection hole is metallized in the hole by copper plating, that is, a copper film is deposited on the hole wall to form a first inner through hole 51; on the first inner through hole 51 formed by copper plating, a desired circuit pattern is formed by graphic plating, that is, a first interconnection layer 61 located on the outer surface of the plastic encapsulation layer 4 corresponding to the pad layer 2 is formed. The first interconnection layer 61 interconnects multiple first inner through holes 51 and is connected to the pad layer 2, thereby connecting to the bottom of the chip 3 through the pad layer 2.

[0079] like Figure 6 As shown, an interconnection hole is drilled at a position of the plastic encapsulation layer 4 corresponding to the chip 3, and the interconnection hole here penetrates part of the plastic encapsulation layer 4 to the top of the chip 3 to expose the top of the chip 3; the interconnection hole is metalized by copper plating to form a second inner through hole 52; on the second inner through hole 52, a desired circuit pattern is formed by pattern plating to form a second interconnection layer 62 located on the outer surface of the plastic encapsulation layer 4 corresponding to the chip 3. The second interconnection layer 62 interconnects multiple second inner through holes 52 and is connected to the top of the chip 3.

[0080] The inner through holes of the plastic packaging layer 4 are formed by chemical copper deposition and pattern electroplating to form an interconnection layer on the plastic packaging layer 4, which can add more connection points and improve the integration without increasing the thickness of the board-level package.

[0081] In a specific embodiment, the shape of the inner through hole can be truncated cone, that is, the cross section of the inner through hole is truncated cone, and the diameter of the outer side of the inner through hole is larger than the diameter of the inner side, that is, the side with a smaller diameter of the first inner through hole 51 is connected to the pad layer 2, and the side with a larger diameter is connected to the first interconnection layer 61; the side with a smaller diameter of the second inner through hole 52 is connected to the top of the chip 3, and the side with a larger diameter is connected to the second interconnection layer 62. The inner through hole is used as an internal heat dissipation hole of the package board. The small diameter close to the heat source can make the heat flow in the designed direction and transfer from the high temperature area to the low temperature area along the truncated cone hole, which conforms to the principles of natural convection and heat conduction; the large diameter side is far away from the heat source, which can provide a larger heat dissipation surface and more fully contact with the low temperature environment outside, which helps to improve the heat transfer efficiency.

[0082] Step 5: Pressing the copper layer to form an external electrode layer;

[0083] like Figure 7 As shown, the semi-cured sheet and copper foil are sequentially pressed on the outermost side of the board to form an external electrode layer 8. During pressing, the semi-cured sheet is placed on the outer side of the board to form a semi-cured layer 7, which is combined with the carrier board 1 through a lamination process; and then the copper foil is pressed on the semi-cured layer 7 to form an external electrode layer 8 as a metal conductive layer on the outer side of the board. Among them, the semi-cured sheet is also called a PP sheet or prepreg, which is a material pre-impregnated with partially cured resin, usually used in combination with glass fiber or other reinforcing materials. It can be seen that the material of the external electrode layer 8 is copper. In addition to copper foil, copper sheets or copper blocks can also be used.

[0084] Step 6: Drill holes on the side of the carrier board 1 and perform copper electroplating to form through holes on the side of the board;

[0085] like Figure 8 As shown, a mechanical drill is used to drill a through hole 9 on the side of the carrier board 1, and the through hole 9 on the side of the board is metalized by copper plating, so that the through hole 9 on the side of the board is connected to the external electrode layer 8 on the two side surfaces, the interconnection layer connected to the top of the chip, and the pad layer 2, so as to connect the chips 3 on the front and back sides of the carrier board 1.

[0086] The drilling steps include: step 601, positioning; accurately positioning on the side of the carrier plate 1 to determine the exact position of the plate side through hole 9; step 602, drilling; using a mechanical drill to drill the required plate side through hole 9 at the positioning position.

[0087] Among them, the steps of copper plating include: step 603, hole cleaning; cleaning the hole wall to remove debris and dust generated during the drilling process; step 604, copper plating; depositing a layer of copper film on the hole wall through a chemical copper plating process as a seed layer for subsequent electroplating to ensure that the metal can be evenly attached to the hole wall during the electroplating process; step 605, electroplating; on the basis of copper plating, electroplating is performed to increase the thickness of the copper layer in the hole.

[0088] Step 7: Etching and electroplating to make external electrodes of the device and solder resist processing;

[0089] like Fig. 9 As shown, a pattern is etched on the external electrode layer 8 according to the circuit design drawing, and then the pattern is electroplated to form the required device electrode area 82; the device electrode area 82 is electrically connected to the internal chip through the board side through hole 9 to form a circuit structure. The external electrode layer 8 is then solder-resisted, and the non-device electrode area is covered with resin to form a solder-resist area 81, which isolates the device electrode areas 82 from each other.

[0090] In this step, the unnecessary copper layer is removed by etching the pattern, thereby leaving the designed circuit pattern. Step 7 includes the following steps:

[0091] Step 701, anti-corrosion layer application: Cover the copper foil with a layer of anti-corrosion material, such as dry film or photoresist.

[0092] Step 702: Exposure: Exposure is performed through a mask so that the resist layer in certain areas becomes soluble.

[0093] Step 703, development; washing away the soluble resist layer to expose the copper layer underneath.

[0094] Step 704, etching: using a chemical solution (etching solution) to remove the copper layer not protected by the anti-corrosion layer.

[0095] Step 705, remove the resist layer; after the etching is completed, remove the remaining resist layer to leave the required circuit pattern.

[0096] Step 706: Electroplating is performed in the remaining area to increase the thickness of the copper layer.

[0097] Step 707, the solder resist is evenly coated on the non-welding area of ​​the external electrode layer 8 by screen printing, spraying or dipping. The area outside the solder resist area 81, that is, the device electrode area 82 will not be covered by the solder resist to facilitate subsequent welding and connection. The solder resist area 81 effectively isolates each device electrode area 82 to prevent the solder from bridging the adjacent pad area during welding to avoid short circuit.

[0098] like Figure 1As shown, the present invention also provides a packaging structure of a bridge rectifier module using board-level packaging, and a packaging board made by the above-mentioned processing method of a bridge rectifier module using board-level packaging. The packaging board includes a carrier board 1 and a plurality of chips 3. The two side surfaces of the carrier board 1 are provided with a pad layer 2, a plastic sealing layer 4, an interconnection layer and an external electrode layer 8 in sequence from the inside to the outside. The plurality of chips 3 are arranged on the pad layer 2, and the plastic sealing layer 4 seals and wraps the chip 3. The plastic sealing layer 4 is provided with internal through holes corresponding to the pad layer 2 and the corresponding chip 3. A part of the interconnection layer is connected to the pad layer 2 through the corresponding internal through holes to connect to the bottom of the chip, and the other part of the interconnection layer is connected to the top of the chip through the corresponding internal through holes; the pad layer 2, the chip 3, the plastic sealing layer 4, the interconnection layer and the external electrode layer 8 on the two side surfaces of the carrier board 1 are symmetrically distributed about the center of the carrier board 1.

[0099] The bridge rectifier module of the present invention adopts the board-level packaging process, and the overall structure is a symmetrical stacked structure. The overall structure is stable, the stress is small, and it is not easy to deform. The existing bridge rectifier module is a traditional frame structure, the product strength is low, and it is easy to be damaged. The board-level packaging structure prepared by the present invention has a smaller packaging size, and can package larger chips in the same volume, which makes it easier to achieve product miniaturization and is beneficial to terminal applications. Compared with the traditional frame structure, the bridge rectifier module of the board-level packaging structure has high processing efficiency, a large number of one-time molding, and more cost advantages. Moreover, since the present invention abandons the method of designing a separate frame, the matching is more flexible, and the chip packaging of different specifications can be achieved.

[0100] In the present invention, the board side through holes 9 are provided on the board edge of the carrier board 1, and the board side through holes 9 connect the external electrode layer 8 on the board surface on both sides, the interconnection layer connected to the top of the chip, and the pad layer 2. The design of the board side through holes 9 on the side can effectively improve the tin creeping effect, significantly enhance the solderability, and the board side through holes 9 can increase the heat dissipation channels of the product, increase the heat dissipation area, and improve the heat dissipation capacity of the structure, thereby making the overall flow capacity of the product stronger.

[0101] In a specific embodiment, the Tg value of the carrier board 1 is greater than 150°C, and the carrier board 1 with a high Tg value can still maintain its physical properties at a higher temperature. The material of the carrier board 1 is epoxy resin, which has a higher Tg value, better thermal stability, and a lower thermal expansion coefficient, so that the package board has high cost-effectiveness, good electrical insulation performance, and high mechanical strength.

[0102] In a specific embodiment, the pad layer 2 extends from the bottom of the chip 3 to the edge of the carrier board 1 and is connected to the board side through hole 9 at the edge of the board, so that the bottom of the chip 3 is led out through the pad layer 2 and connected to the board side through hole 9, thereby realizing the interconnection of the chips on both sides of the board.

[0103] In the present invention, solder is applied to the corresponding position of the pad area on the pad layer 2 to mount and weld the chip 3. The solder can be solder paste or conductive glue or other materials with conductive ability. The chip mounting method can be a positive mounting method or a flip-chip mounting method. The number of chips 3 can be 1, 2 or more than 2, and the number of chips 3 on the two sides of the carrier board 1 can be the same or different.

[0104] The two side surfaces of the carrier board 1 are sealed with plastic encapsulation material to form a plastic encapsulation layer 4. The plastic encapsulation material is epoxy resin, which can be a liquid structure, a powder structure, or a film structure. The plastic encapsulation layer 4 is provided with an inner through hole. The specific hole forming process is as described above and will not be repeated here. The inner through hole of the plastic encapsulation layer 4 is formed on the plastic encapsulation layer 4 by chemical copper plating and pattern electroplating. More connection points can be added without increasing the thickness of the board-level package. Among them, the interconnection layer includes a first interconnection layer 61 and a second interconnection layer 62. The first interconnection layer 61 is arranged at one end of the corresponding pad layer 2 of the plastic encapsulation layer 4, and the second interconnection layer 62 is arranged at the other end of the corresponding chip 3 of the plastic encapsulation layer 4. The inner through hole includes a first inner through hole 51 and a second inner through hole 52. The first inner through hole 51 penetrates the plastic encapsulation layer 4, and the first inner through hole 51 connects the first interconnection layer 61 and the pad layer 2; the second inner through hole 52 penetrates the plastic encapsulation layer 4 to the top of the chip, and the second inner through hole 52 connects the second interconnection layer 62 and the top of the chip.

[0105] In this embodiment, the inner through hole is truncated cone-shaped, and the diameter of the outer side of the inner through hole is larger than the diameter of the inner side. The side with a smaller diameter of the first inner through hole 51 is connected to the pad layer 2, and the side with a larger diameter is connected to the first interconnection layer 61; the side with a smaller diameter of the second inner through hole 52 is connected to the top of the chip, and the side with a larger diameter is connected to the second interconnection layer 62. The inner through hole serves as an internal heat dissipation hole of the packaging board. The small diameter close to the heat source can make the heat flow in the designed direction and transfer from the high temperature zone to the low temperature zone along the truncated cone-shaped channel, which conforms to the principles of natural convection and heat conduction; the large diameter side is far away from the heat source, which can provide a larger heat dissipation surface and more fully contact with the low temperature environment outside, which helps to improve the heat transfer efficiency. In other optional embodiments, the inner through hole is cylindrical, conical or polygonal.

[0106] In addition to using copper plating technology, the through holes without chip positions can be replaced with copper blocks or other metals with high thermal conductivity to ensure heat dissipation. Specifically, the second inner through hole 52 away from the chip 3 is filled with copper blocks or other metal blocks.

[0107] The internal through holes of the present invention include a first internal through hole 51 and a second internal through hole 52, which are respectively connected to the bottom and the top of the chip 3, not only realizing electrical connection, but also becoming a heat dissipation channel for the chip 3. The internal through holes increase the heat dissipation channel inside the board-level packaging structure of the bridge stack rectifier module, making it easier to dissipate heat when the chip 3 is working, thereby improving the tolerance of the chip 3.

[0108] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A bridge rectifier module packaging structure using board-level packaging, It is characterized in that It comprises a carrier board and a plurality of chips, wherein the two side surfaces of the carrier board are provided with a pad layer, a plastic sealing layer, an interconnection layer and an external electrode layer in order from the inside to the outside, the plurality of chips are provided on the pad layer, the plastic sealing layer seals and wraps the chips, the plastic sealing layer is provided with inner through holes corresponding to the pad layer and the chips, a part of the interconnection layer is connected to the pad layer through the corresponding inner through holes to connect to the bottom of the chip, and another part of the interconnection layer is connected to the top of the chip through the corresponding inner through holes; The pad layers, chips, plastic packaging layers, interconnection layers and external electrode layers on both side surfaces of the carrier board are symmetrically distributed about the center of the carrier board; The board edge of the carrier board is provided with a board side through hole, and the board side through hole connects the external electrode layer on the two side board surfaces, the interconnection layer connected to the top of the chip, and the pad layer.

2. According to the board-level packaging structure of the bridge rectifier module of claim 1, It is characterized in that The pad layer extends from the bottom of the chip to the board edge of the carrier board and is connected to the board side through holes at the board edge.

3. According to the board-level packaging structure of the bridge rectifier module of claim 1, It is characterized in that The interconnection layer includes a first interconnection layer and a second interconnection layer, and the inner through hole includes a first inner through hole and a second inner through hole, the first inner through hole passes through the plastic packaging layer, and the first inner through hole connects the first interconnection layer and the pad layer; the second inner through hole penetrates the plastic packaging layer to the top of the chip, and the second inner through hole connects the second interconnection layer and the top of the chip.

4. According to the board-level packaging structure of the bridge rectifier module of claim 3, It is characterized in that The first interconnection layer is arranged at one end of the plastic encapsulation layer corresponding to the pad layer, and the second interconnection layer is arranged at the other end of the plastic encapsulation layer corresponding to the chip.

5. The bridge rectifier module packaging structure using board-level packaging according to claim 1, It is characterized in that A solder resist area is provided in the middle of the external electrode layer, and the solder resist area divides the external electrode layer into a plurality of device electrode areas isolated from each other.

6. A method for processing a bridge rectifier module using board-level packaging, used for processing and forming a packaging structure of a bridge rectifier module using board-level packaging as claimed in any one of claims 1 to 5, It is characterized in that Take a carrier board as a carrier, weld the chips on both sides of the carrier board, plastic encapsulate the chips to seal and keep the board surface flat, drill holes in the plastic encapsulation layer and electroplate copper in the holes to achieve interconnection, press together to make a metal conductive layer, drill holes on the side of the board and electroplate copper in the holes to interconnect the chips on both sides of the carrier board, etch the metal conductive layer and electroplate it to obtain the device electrode area; complete the board-level packaging process.

7. The method for processing a bridge rectifier module using board-level packaging according to claim 6, It is characterized in that The method of welding chips on the two side surfaces of the carrier board comprises the following steps: making pad layers at the central symmetrical positions of the two side surfaces of the carrier board; and welding the chips to the pad layers on the two side surfaces of the carrier board respectively.

8. The method for processing a bridge rectifier module using board-level packaging according to claim 6, It is characterized in that The plastic encapsulation process is used to seal and wrap the chip, including the following steps: coating the surface of the plastic encapsulation material carrier board to cover the chip, the pad layer and the partially exposed carrier board; and forming a plastic encapsulation layer after curing to completely wrap the chip.

9. The method for processing a bridge rectifier module using board-level packaging according to claim 6, It is characterized in that The plastic sealing layer is drilled and copper is electroplated in the holes to achieve interconnection, including the following steps: Holes are drilled at positions of the plastic encapsulation layer corresponding to the pad layer, and holes are drilled at positions of the plastic encapsulation layer corresponding to the chip; copper is plated at the drilling positions to obtain a first inner through hole connecting the pad layer and a second inner through hole connecting the top of the chip; a first interconnection layer is formed on the plastic encapsulation layer by pattern electroplating to connect several first inner through holes, and a second interconnection layer is formed to connect several second inner through holes.

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