A simulated AI computing architecture

Abstract

The present invention provides an analog AI computing architecture, which relates to the field of circuit design technology. The architecture includes a signal acquisition module for sampling analog signals to obtain signal sample data; a filtering module for bandpass filtering the signal sample data using an AI signal transmission mechanism to obtain filtered data; and a computing module for performing analog AI computing on the filtered data using an operator and an external control switch to obtain a processed analog signal. The present invention simplifies the processing flow of traditional digital signals, improves the computing speed, and reduces the power consumption and system complexity required for computing.

Description

Technical Field

[0001] This specification relates to the field of circuit design technology, and in particular to an analog AI computing architecture. Background Art

[0002] In traditional digital signal processing, analog signals need to go through a series of conversion steps before they can be processed by digital circuits. These steps require the use of A / D converters for analog signal acquisition; FIR filters for digital signal filtering; FPGAs for some preprocessing, such as removing noise, amplifying or reducing signals, etc.; ARM processors or specialized DSP chips for more complex analysis and processing. The specific process is as follows: Figure 1 As shown, the final result is output after a series of processing.

[0003] Although this method can achieve efficient processing of analog signals, it also has some disadvantages and limitations. First, digital signal processing requires a large number of device support, which leads to a large number of devices required for the entire system, increasing the complexity and cost of the system, and the optimization and debugging of the algorithm also takes a lot of time.

[0004] Secondly, since the conversion process between analog and digital domains may introduce errors, there may be a loss of precision during the processing. Furthermore, since the analog signal needs to be converted into a digital signal and then the processing result is converted back to an analog signal output, this process may introduce additional processing delays, affecting the real-time performance and response speed of the system. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides an analog AI computing architecture which simplifies the processing flow of traditional digital signals, improves the computing speed, and reduces the power consumption and system complexity required for computing.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a simulated AI computing architecture, comprising:

[0007] A signal acquisition module is used to sample the analog signal to obtain signal sample data;

[0008] A filtering module, used to perform bandpass filtering on the signal sample data using an AI signal transmission mechanism to obtain filtered data;

[0009] The calculation module is used to use the operator and the external control switch to calculate the filtered data to obtain a processed analog signal.

[0010] Furthermore, the signal acquisition module includes a sampling and holding circuit composed of a fully differential operational amplifier and a sampling capacitor:

[0011] The fully differential operational amplifier is used to sample the input analog signal and store the obtained sampled charge in the sampling capacitor;

[0012] The sampling capacitor is used to convert the sampled charge into a form to obtain signal sample data.

[0013] Furthermore, the expression of the sampled charge is:

[0014] q S1 (φ1)=C S ·V in1 (φ1);

[0015] q S2 (φ1)=C S ·V in2 (φ1);

[0016] Among them, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, q S2 Represents the second sample charge, V in2 Represents the input second analog signal.

[0017] Furthermore, the expression of the signal sample data is:

[0018]

[0019]

[0020] Among them, V S1 represents the first signal sample data, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, t represents the sampling period, V S2 represents the second signal sample data, q S2 Represents the second sample charge, V in2 Represents the input second analog signal.

[0021] Furthermore, the filtering module includes a bandpass filter composed of a transconductance amplifier and a capacitor:

[0022] Used to perform bandpass filtering processing on the signal sample data in the continuous time domain using a bandpass filter to obtain filtered data:

[0023]

[0024]

[0025] Among them, V out1 Represents the first filtered data, G m represents the amplification factor of the transconductance amplifier, C represents the capacitance value in the bandpass filter, V S1 represents the first signal sample data, τ represents the current time, t represents the sampling period, V out2 Represents the second filtering data, V S2 Represents the second signal sample data.

[0026] Furthermore, the computing module includes an operator and a control switch array:

[0027] The control switch array is used to analyze the filtered data and input the filtered data into the corresponding operational amplifier for operation by using an external control switch;

[0028] The operator is used to calculate the filtered data to obtain a processed analog signal.

[0029] The beneficial effects of the present invention are as follows: the analog AI computing architecture is composed of a signal acquisition module, a filtering module and a computing module, and the processed analog signal is obtained by sampling, filtering and analog AI computing processing of the analog signal. Through highly parallel and analog processing, the more complex processing process in the field of digital signal processing can be transformed into the result of direct processing in a simpler analog domain, reducing the distortion and delay that may occur in the signal conversion process, and improving the real-time performance and response speed of the system; by omitting the digital signal processor and other related digital circuits, referring to the high-energy-efficiency process of neurons transmitting signals through synapses in the human brain, it simplifies the system architecture and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] This specification will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same number represents the same structure, wherein:

[0031] Figure 1 is a schematic diagram of a module for simulating an AI computing architecture according to some embodiments of this specification;

[0032] Figure 2 This is an exemplary schematic diagram of an analog AI computing architecture working circuit shown in some embodiments of this specification. DETAILED DESCRIPTION

[0033] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0034] Example

[0035] Figure 1 It is a module diagram of a simulated AI computing architecture according to some embodiments of this specification.

[0036] In some embodiments, the simulated AI computing architecture may include a signal acquisition module, a filtering module, and a computing module.

[0037] The signal acquisition module is used to sample the analog signal to obtain signal sample data.

[0038] The analog signal is a signal that reflects the continuous change of current and voltage over time. For example, the analog signal may include a first analog signal and a second analog signal, which reflect the current signal and voltage signal input into the circuit.

[0039] The first analog signal is an analog signal obtained by the first input terminal.

[0040] The second analog signal is an analog signal obtained from the second input terminal.

[0041] The signal sample data is the target frequency interval signal at each time point divided by time period.

[0042] In some embodiments, the signal acquisition module may include a sample-and-hold circuit composed of a fully differential operational amplifier and a sampling capacitor, which is used to sample the analog signal to obtain signal sample data.

[0043] A fully differential operational amplifier is used to sample the input analog signal and store the obtained sampled charge in a sampling capacitor.

[0044] The sampled charge is a charge-form data reflecting the voltage value of the signal at each time point. For example, the sampled charge may include a first sampled charge and a second sampled charge.

[0045] The first sampled charge is charge data obtained by sampling the first analog signal.

[0046] The second sampled charge is charge data obtained by sampling the second analog signal.

[0047] In some embodiments, the expression of the sampled charge may be:

[0048] q S1 (φ1)=C S ·V in1 (φ1);

[0049] q S2 (φ1)=C S ·V in2 (φ1);

[0050] Among them, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, q S2 Represents the second sample charge, V in2 Represents the input second analog signal.

[0051] The sampling capacitor is used to convert the sampled charge into a form to obtain signal sample data.

[0052] In some embodiments, the expression of the signal sample data may be:

[0053]

[0054]

[0055] Among them, V S1 represents the first signal sample data, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, t represents the sampling period, V S2 represents the second signal sample data, q S2 Represents the second sample charge, V in2 Represents the input second analog signal.

[0056] The first signal sample data is voltage-form data converted from the first sampled charge.

[0057] The second signal sample data is voltage-form data after the second sampled charge is converted.

[0058] In some embodiments, the signal acquisition module can use a capacitor flip-type sampling and holding circuit to sample the input analog signal to obtain a sampled charge. In the holding stage, the sampled charge q S1 and q S2The charge value remains unchanged, and is converted back to voltage form through the sampling capacitor CS for the next filtering process until the next sampling cycle. In the holding process, the signal type is still an analog voltage signal, but its value is the voltage at the sampling moment and does not change with time.

[0059] In some embodiments, the signal acquisition module may include an integral sampling and holding circuit that operates within a wider frequency range; a switching capacitor sampling and holding circuit that uses switching capacitor technology to switch capacitors through external control signals to achieve sampling and holding functions; a time-interleaved sampling and holding circuit that samples multiple signals through time-interleaved technology and is suitable for a multi-channel data acquisition system; and structures such as low-pass, high-pass, band-pass and band-stop filters that are used to filter out unnecessary frequency components in the signal.

[0060] The filtering module is used to perform bandpass filtering on the signal sample data by using the AI ​​signal transmission mechanism to obtain filtered data.

[0061] The filtered data is the signal sample data of the target frequency interval that reflects the essential characteristics of the original signal after the noise is removed.

[0062] In some embodiments, the target frequency range can be calculated according to actual circuit requirements.

[0063] In some embodiments, the filtering module may include a bandpass filter composed of a transconductance amplifier and a capacitor, and is used to perform bandpass filtering processing on the signal sample data in the continuous time domain using the bandpass filter to obtain filtered data.

[0064] In some embodiments, the expression of the filtered data may be:

[0065]

[0066]

[0067] Among them, V out1 Represents the first filtered data, G m represents the amplification factor of the transconductance amplifier, C represents the capacitance value in the bandpass filter, V S1 represents the first signal sample data, τ represents the current time, t represents the sampling period, V out2 Represents the second filtering data, V S2 Represents the second signal sample data.

[0068] The first filtered data is analog signal data obtained by filtering the first signal sample data.

[0069] The second filtered data is analog signal data obtained by filtering the second signal sample data.

[0070] In some embodiments, the signal acquisition module may include a capacitor flip-over sampling and holding circuit composed of a switch, a fully differential operational amplifier, and a sampling capacitor, and the filtering module may include a Gm-C filter; wherein the switch is controlled by a clock Control and high level sampling switch.

[0071] In some embodiments, Figure 2 As shown, the first analog signal V in1 and the second analog signal V in2 By controlling the clock The controlled switch and sampling capacitor C S1 , C S2 One end a and b are connected, and the clock is controlled The controlled switch is connected to the positive output and negative output of the fully differential operational amplifier, and the sampling capacitor C S1 The other end X is connected to the sampling capacitor C S2 Connected to the negative terminal of the fully differential operational amplifier input, where the sampling capacitor C S1 and sampling capacitor C S2 By controlling the clock The two switches controlled by the controller are connected, and the node C between the two switches is connected to the mode voltage V cm , sampling capacitor C S2 The other end Y is connected to the positive input terminal of the fully differential operational amplifier. The positive and negative output terminals of the fully differential operational amplifier are controlled by the clock The controlled switch is connected, and the positive output terminal and the negative output terminal of the fully differential operational amplifier are connected to the Gm-C filter.

[0072] In some embodiments, Figure 2 As shown, the Gm-C filter may include a Gm1-C filter and a Gm2-C filter, wherein the positive input terminal of the Gm1-C filter is connected to the positive output terminal of the fully differential operational amplifier, the negative input terminal is grounded, and the output terminal is connected to a calculation module having four addition, subtraction, multiplication and division operators whose switches are controlled by external signals to be closed or opened; the positive input terminal of the Gm2-C filter is connected to the negative output terminal of the fully differential operational amplifier, the negative input terminal is grounded, and the output terminal is connected to a calculation module having four addition, subtraction, multiplication and division operators whose switches are controlled by external signals to be closed or opened.

[0073] Circuit working principle: When the clock signal and is high level, When it is low, the circuit works in sampling mode. At this time, the charge Q x The charge Q at node Y y They are:

[0074] Q x =(V cm -V in1 )C s1 ;

[0075] Q y =(V cm -V in2 )C s2 ;

[0076] When the clock signal and is low level, When it is high level, the circuit works in the hold mode. At this time, the sampling capacitor C S1 and C S2 Directly connected between the input and output, the charge Q between node X and node Y x With Q y They are:

[0077] Q x =(V x -V out1 )C s ;

[0078] Q y =(V y -V out2 )C s ;

[0079] Among them, V out1 and V out2 They represent the voltage values ​​at the positive output terminal and the negative output terminal of the fully differential operational amplifier respectively;

[0080] Assuming the op amp is an ideal op amp, the voltage V at node X is x The voltage V at node Y y Equal, according to the law of conservation of charge we can get:

[0081] V out1 -V out2 =V in1 -V in2 ;

[0082] It can be seen that the embodiment of this scheme refers to the signal receiving process of the neuron dendrites, that is, the dendrites in the neurons receive signals from other neurons and convert them into potential changes. Within one clock cycle, the capacitor flip sampling and holding circuit is used to complete the sampling and holding function of the input signal; refer to the signal filtering and integration mechanism of neurons in the brain, that is, in the brain, neurons integrate signals from multiple sources through synapses, and filter according to the intensity and timing of the signals to produce appropriate responses. After the analog signal to be input is sampled and held, it enters the Gm-C filter. The Gm-C filter uses a transconductance amplifier (Gm) and a capacitor (C) to realize the filtering function and processes the input signal in the continuous time domain.

[0083] The calculation module is used to use an operator and an external control switch to perform analog AI calculations on the filtered data to obtain a processed analog signal.

[0084] An operator is a circuit operation structure used to calculate analog signals to obtain analog signals. For example, an operator may include an adder, a subtractor, a multiplier, and a divider.

[0085] The external control switch is a switch used to control the connection relationship between the filter module and the operator.

[0086] The processed analog signal is an analog signal that meets the requirements of subsequent circuit identification.

[0087] In some embodiments, the processed analog signal can be used to input other circuits for subsequent identification and processing.

[0088] In some embodiments, the calculation module may include an operator and a control switch array, which are used to perform operations on the filtered data to obtain a processed analog signal.

[0089] The control switch array is used to analyze the filtered data and input the filtered data into the corresponding operational amplifier for operation by using an external control switch.

[0090] In some embodiments, the computing module may utilize a control switch array to input analog signals into an operator for computing.

[0091] The operator is used to calculate the filtered data to obtain a processed analog signal.

[0092] In some embodiments, the operator of the computing module may also include a function generator, an integrator, a differentiator, a logarithmic and exponential operator, and other structures for generating specific function waveforms, such as analog signals of sine waves, exponential waveforms, etc.

[0093] In some embodiments, Figure 2As shown, the external control switch S of the computing module 31 , S 41 , S 51 and S 61 One end can be connected to the output of the Gm1-C filter to calculate the external control switch S of the module. 32 , S 42 , S 52 and S 62 One end can be connected to the output of the Gm2-C filter, and the external control switch S 31 , S 32 Connected to the adder, external control switch S 41 , S 42 Connected to the subtractor, external control switch S 51 , S 52 Connect to the multiplier, external control switch S 61 , S 62 Connected to the divider.

[0094] Working principle of the circuit: The filtered signal will enter the corresponding analog calculation unit according to the control of the control switch array, such as the adder connected to S31 and S32 whose switches are controlled by external signals, or the subtractor connected to S41 and S42 whose switches are controlled by external signals, or the multiplier connected to S51 and S52 whose switches are controlled by external signals, or the divider connected to S61 and S62 whose switches are controlled by external signals to perform corresponding operations:

[0095] V sum (t) = V out1 (t)+V out2 (t);

[0096] V diff (t) = V out1 (t)-V out2 (t);

[0097] V prod (t) = V out1 (t)×V out2 (t);

[0098]

[0099] Among them, V sum Represents the output analog signal of the addition operation, V diff Represents the output analog signal of the subtraction operation, V prod Represents the output analog signal of the multiplication operation, V quotient An output analog signal representing a division operation;

[0100] The analog divider may include an inverting proportional operational amplifier, and the output analog signal of the division operation may be expressed as:

[0101]

[0102] Among them, R f Represents the feedback resistor, R in Represents the input resistance, the output analog signal of the division operation V quotient It is the negative ratio of the product of the two input signals.

[0103] In some embodiments of this specification, the analog AI computing architecture is composed of a signal acquisition module, a filtering module and a computing module, and the processed analog signal is obtained by sampling, filtering and analog AI computing processing of the analog signal. Through highly parallel and analog processing, the more complex processing process in the field of digital signal processing can be transformed into the result of direct processing in a simpler analog domain, reducing the distortion and delay that may occur in the conversion process of the analog signal, and improving the real-time performance and response speed of the system; by omitting the digital signal processor and other related digital circuits, referring to the high-energy-efficiency process of neurons transmitting signals through synapses in the human brain, it simplifies the system architecture and reduces power consumption.

Claims

1. A simulated AI computing architecture, characterized in that: include: A signal acquisition module is used to sample the analog signal to obtain signal sample data; wherein the signal acquisition module includes a sampling and holding circuit composed of a fully differential operational amplifier and a sampling capacitor: The fully differential operational amplifier is used to sample the input analog signal and store the obtained sampled charge in the sampling capacitor; the expression of the sampled charge is: q S1 (φ1)=C S ·V in1 (φ1); q S2 (φ1)=C S ·V in2 (φ1); Among them, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, q S2 Represents the second sample charge, V in2 a second analog signal representing an input; The sampling capacitor is used to convert the sampled charge into a form to obtain signal sample data; the expression of the signal sample data is: Among them, V S1 represents the first signal sample data, q S1 represents the first sample charge, C S represents the sampling capacitor, V in1 represents the first analog signal input, φ1 represents the control clock, t represents the sampling period, V S2 represents the second signal sample data, q S2 Represents the second sample charge, V in2 a second analog signal representing an input; A filtering module is used to perform bandpass filtering on the signal sample data by using the AI ​​signal transmission mechanism to obtain filtered data; the filtering module includes a bandpass filter composed of a transconductance amplifier and a capacitor: It is used to receive signals from other neurons in the dendrites of neurons and convert them into potential changes. Within one clock cycle, capacitance flip sampling is performed, and the signal sample data is subjected to continuous time domain bandpass filtering by using a bandpass filter to obtain filtered data: Among them, V out1 Represents the first filtered data, G m represents the amplification factor of the transconductance amplifier, C represents the capacitance value in the bandpass filter, V S1 represents the first signal sample data, τ represents the current time, t represents the sampling period, V out2 Represents the second filtering data, V S2 represents second signal sample data; The calculation module is used to use the operator and the external control switch to calculate the filtered data to obtain a processed analog signal.

2. The simulated AI computing architecture according to claim 1, wherein: The computing module includes an operator and a control switch array: The control switch array is used to analyze the filtered data and input the filtered data into the corresponding operational amplifier for operation by using an external control switch; The operator is used to calculate the filtered data to obtain a processed analog signal.

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