A hybrid analog-digital self-refreshing in-memory computing cluster and analog-assisted digital in-memory computing circuit

Abstract

The present invention discloses an analog-digital hybrid self-refreshing in-memory computing cluster and an analog-assisted digital in-memory computing circuit, which belong to the field of integrated circuit design. The present invention embeds digital computing, analog computing and refresh functions into the same in-memory computing cluster, and through low-precision analog pre-computation, the required high-precision digital computing operations can be greatly reduced, thereby improving the energy efficiency and area efficiency of digital in-memory computing. In addition, data between analog computing and digital computing can be reused, and no additional data transfer is required, so the energy efficiency and area efficiency are further improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a novel analog-digital hybrid self-refreshing in-memory computing cluster and an analog-assisted digital in-memory computing circuit. Background Art

[0002] In recent years, artificial intelligence (AI) technology has developed rapidly and has had a profound impact on human society. In order to achieve better performance on various tasks, high-performance AI algorithm models have also evolved from convolutional neural network (CNN) models to transformer models. In CNN, each convolutional layer of the model extracts local features through convolution kernels, and then further simplifies the data through pooling layers. The receptive field of CNN is expanded layer by layer, and finally forms a global feature map. Due to its local operation and weight sharing characteristics, this local receptive field design has advantages in computational efficiency. In contrast, transformers usually achieve global receptive fields through multi-head self-attention. This global perception ability enables transformer models to flexibly adjust their focus and capture long-range features and global patterns in images. Therefore, transformers show greater flexibility and the ability to understand complex relationships in image processing tasks. However, the global attention mechanism of transformers may consume more computing resources when processing high-resolution images. In addition, in natural language processing, the attention mechanism of the transformer gives it a global receptive field, which can flexibly adjust the focus in the sequence. This is especially important in natural language processing because the context and semantics of the language may involve long-distance relationships. The large language model (LLM), which currently has very outstanding performance, was developed based on the transformer architecture. The large language model obtains stronger understanding and generation capabilities by expanding the model size, increasing the amount of training data, and fine-tuning after pre-training. In general, the attention mechanism of the transformer enables it to show extremely outstanding performance in various fields, but the huge amount of computation it brings also puts higher requirements on computing resources and hardware performance.

[0003] In terms of hardware, the energy efficiency of processors for general application scenarios is limited when running AI algorithms due to incomplete adaptation of hardware and computing requirements. In order to improve the computing energy efficiency of hardware so that AI models can be widely deployed, people have begun to design domain-specific accelerators and optimize the design of computing cores for specific applications through algorithm and hardware collaborative optimization. When designing hardware, researchers found that the calculations in AI models are mainly dominated by large-dimensional matrix-vector multiplication operations. When performing a large number of matrix-vector multiplications using the traditional storage-computation separation computing architecture, a lot of power is often consumed in data transfer. In order to solve the problem of data transfer power consumption, researchers proposed a new computing core: the in-memory computing core. The in-memory computing core embeds the computing function into the memory unit, and no longer needs to read the data before calculation. When the in-memory computing core performs matrix-vector multiplication, the two-dimensional weight matrix can be stored in the two-dimensional in-memory computing array very adaptably. At the same time, the input vector can be fed into the in-memory computing array through multiple word lines, and each value in the input vector is shared by multiple in-memory computing units through the word line, and multiplication is completed with the weight. Next, the inputs of multiple in-memory computing units connected to the same bit line are multiplied by the weights to complete the accumulation. Such a high degree of parallelism makes the in-memory computing core have extremely high energy efficiency and throughput. At present, according to the specific implementation method of the computing part of the circuit, the in-memory computing core can be divided into digital in-memory computing core and analog in-memory computing core. Digital in-memory computing uses digital logic to complete multiplication and accumulation, so there is no loss of precision, which is suitable for high-precision calculation. However, the addition tree circuit that completes the digital domain accumulation has a large area and power consumption overhead, resulting in low energy efficiency of the digital in-memory computing core. In contrast, the analog in-memory computing core has higher energy efficiency. However, since the performance of the analog domain computing circuit is easily affected by process, voltage and temperature offsets and transistor mismatch, its calculation accuracy is limited.

[0004] At present, at the algorithm level, researchers are exploring the sparsity of the self-attention mechanism to reduce its complexity. At the circuit level, researchers are trying to use digital in-memory computing cores to accelerate the transformer. However, due to the energy efficiency bottleneck of digital in-memory computing itself, the energy efficiency of the current transformer accelerator based on digital in-memory computing cores is not high. Directly using analog in-memory computing cores for acceleration faces accuracy issues. Therefore, there is a need for an in-memory computing core design that can fully utilize the sparsity of the self-attention mechanism and combine the advantages of analog high energy efficiency with the advantages of digital high precision to further improve the computational energy efficiency of the self-attention mechanism, so that high-performance transformer models can be widely deployed. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention proposes a novel analog-digital hybrid self-refreshing in-memory computing cluster and an analog-assisted digital in-memory computing circuit.

[0006] The technical solution provided by the present invention is as follows:

[0007] A computing cluster in an analog-to-digital hybrid self-refresh memory, characterized in that it includes 1 sign bit unit, Z analog-to-digital hybrid units and Z+1 digital units, where Z is a natural number. All units in the computing cluster in the analog-to-digital hybrid memory are connected to a read word line RWL via a write word line WWL, wherein the Z analog-to-digital hybrid units are connected to an analog line AL via a computing line CL, wherein the analog line AL is connected to an analog line AL of the sign bit unit. The number of write word lines WWL, read word lines RWL, analog lines AL, computing lines CL, input lines IL and input line anti-ILB in the computing cluster is all 1, and the number of write bit lines WBL and read bit lines RBL is all 2x(Z+1). The computing cluster in the analog-to-digital hybrid self-refresh memory stores a 2x(Z+1)-bit "sign-amplitude" encoded data, the sign bit unit stores the sign bit, the analog-to-digital hybrid unit stores the high Z bit in the data amplitude bit, and the digital unit stores the low Z+1 bit in the data amplitude bit. The working modes of the computing cluster in the analog-to-digital hybrid self-refresh memory are analog mode and digital mode. In the analog mode, the sign bit unit and the analog-to-digital hybrid unit of the computing cluster in the analog-to-digital hybrid self-refresh memory are enabled to perform analog domain calculations, while the digital unit is not enabled; in the digital mode, all units of the computing cluster in the analog-to-digital hybrid self-refresh memory are enabled, and the data are read out to complete the digital and calculations.

[0008] The digital unit is composed of four transistors. Among the four transistors, two of them are N-type transistors and P-type transistors respectively. Their gate ends are connected together as a storage node, the source end of the P-type transistor and the drain end of the N-type transistor are connected together as a storage node, and the drain end of the P-type transistor and the source end of the N-type transistor are connected to the power supply and the ground respectively. The other two transistors of the four transistors are the write transistor and the read transistor. The write transistor is an N-type transistor, and its source and drain ends are respectively connected to the write bitline (WBL) and the storage node, and the gate end is connected to the write wordline (WWL). The read transistor is an N-type transistor, and its source and drain ends are respectively connected to the read bitline (RBL) and the storage node, and the gate end is connected to the read wordline (RWL).

[0009] The analog-to-digital hybrid unit is composed of four transistors and a computing capacitor. The size of the capacitor in the analog-to-digital hybrid unit is binary weighted. Among the four transistors, two of them are N-type transistors and P-type transistors respectively. Their gate ends are connected together as a storage node, the source end of the P-type transistor and the drain end of the N-type transistor are connected together as a storage node, and the drain end of the P-type transistor and the source end of the N-type transistor are connected to the power supply and the analog line (AL) respectively. The other two transistors of the four transistors are the write tube and the read tube. The write tube is an N-type transistor, and its source and drain ends are respectively connected to the write bitline (WBL) and the storage node, and the gate end is connected to the write wordline (WWL). The read tube is an N-type transistor, and its source and drain ends are respectively connected to the read bitline (RBL) and the storage node, and the gate end is connected to the read wordline (RWL). One end of the computing capacitor is connected to the storage node, and the other end is connected to the compute line (compute line).

[0010] The sign bit unit is composed of six transistors. Among the six transistors, four of them are connected in the same way as the digital unit. The extra two transistors are N-type transistors, whose gate terminals are connected to the storage node and the storage node bar, respectively, and whose source terminals are connected to the input line (IL) and the input line bar (ILB), respectively. The drain terminals of the two transistors are connected together as an analog line (AL).

[0011] The present invention further provides an analog-assisted digital in-memory computing circuit, which first includes an in-memory computing group, which includes (32xM)x(4xN) in-memory computing clusters, where M and N are natural numbers. There are 4xN in-memory computing clusters in the same row of the in-memory computing group connected by write bit lines WBL, read bit lines RBL, input lines IL and input line anti-ILB. There are 32xM in-memory computing clusters in the same column of the in-memory computing group connected by write word lines WWL and read word lines RWL. In addition, the computing lines CL of all in-memory computing clusters in the in-memory computing group are connected. The number of write bit lines WBL and read bit lines RBL in the in-memory computing group is 32xMx2x(Z+1), the number of input lines IL and input line anti-ILB is 32xM, the number of write word lines WWL and read word lines RWL is 4xN, and the number of computing lines CL is 1;

[0012] Next, an in-memory computing sub-array is formed by 4xG in-memory computing groups, 32xMx2x(Z+1) refresh and global read bit line driver units, a multi-input comparator and a word line driver, where G is a natural number. The 4xG in-memory computing groups are connected through write bit lines WBL, read bit lines RBL, input lines IL and input line anti-ILB. The refresh and global read bit line driver unit is connected to the sign bit unit, analog-digital mixed unit or digital unit in the same row of the in-memory computing cluster through the read bit lines and write bit lines. The number of write bit lines WBL and read bit lines RBL in the in-memory computing subarray is 32xMx2x(Z+1), the number of input lines IL and input line anti-ILB is 32xM, the number of write word lines WWL and read word lines RWL is 4xNx4xG, and the number of computing lines CL is 4xG. The 4xG in-memory computing groups are connected to the multi-input comparator through G computing lines CL, and are connected to the word line driver through 4xNx4xG write word lines WWL and 4xNx4xG read word lines RWL. The output of the multi-input comparator is connected to the input of the word line driver through the index line.

[0013] Finally, the analog auxiliary digital in-memory computing circuit includes an in-memory computing array composed of S in-memory computing sub-arrays, an input data register, a digital-to-analog converter, and a digital multiplication and accumulation module, where S is a natural number. The S in-memory computing sub-arrays are connected through input lines IL, input line inversions ILB, global write bit lines GWBL, and global read bit lines GRBL. The number of global write bit lines GWBL and global read bit lines GRBL in the in-memory computing array is 32xMx2x(Z+1), and the number of input lines IL and input line inversions ILB is 32xM.

[0014] The calculation method of the analog-assisted digital in-memory calculation circuit is as follows: each in-memory calculation cluster stores a 2x(Z+1)-bit "sign-amplitude" encoded data, the sign bit unit stores the sign bit, the analog-digital mixing unit stores the high Z bit in the data amplitude bit, and the digital unit stores the low Z+1 bit in the data amplitude bit. In the first step of analog domain calculation, the high Z+1 bit of all data in the in-memory calculation array is enabled (that is, the sign bit unit and the analog-digital mixing unit in all in-memory calculation clusters are enabled, while the digital unit is not enabled), and each column of data in each in-memory calculation group and the input data vector complete the Z+1-bit multiplication and accumulation operation in the analog domain, and the result is averaged in the analog domain and output to the multi-input comparator. Then, the multi-input comparator in each in-memory calculation sub-array will compare the calculation results from the 4xG in-memory calculation groups, find the maximum value and generate the index of the corresponding in-memory calculation sub-array position, and output the index to the word line driver. In the second step of digital domain calculation, all bits of the enabled data in the in-memory calculation array are read out: the word line driver will only enable the in-memory calculation group with the largest analog calculation result in each in-memory calculation sub-array according to the index, and read out the data in the in-memory calculation group in turn to complete the 2x(Z+1)-bit multiplication and accumulation operation with the input data vector in the digital multiplication and accumulation module.

[0015] Therefore, the analog auxiliary digital in-memory calculation circuit of the present invention is used, and in the low-precision analog pre-calculation operation: in the first step of analog domain calculation, the sign bit unit and the analog-digital mixing unit in all in-memory calculation clusters are enabled. The digital-to-analog converter will convert the input data into the voltage change on the input line and the opposite of the input line according to the different input data values ​​in the input data register. The sign bit unit in the in-memory calculation cluster will select the voltage on the input line or the opposite of the input line to transmit to the analog line according to the sign bit data, thereby driving the digital-to-analog mixing unit. According to the different data in the digital-to-analog mixing unit, the analog line will generate different voltage changes on the calculation line through the capacitor in the digital-to-analog mixing unit, and the voltage change is the product of the input data and the high Z+1 bit data in the in-memory calculation cluster. The 32xM in-memory calculation clusters connected to the same calculation line simultaneously complete the product of the input data and the high Z+1 bit data in the in-memory calculation cluster, and the total voltage change generated on the calculation line is the result of the multiplication and accumulation of the input data vector and the high Z+1 bit data in the 32xM in-memory calculation clusters. At the same time, since the 4xN calculation lines in the same in-memory calculation group are connected together, their voltage changes are averaged. Then, the multi-input comparator in each in-memory calculation sub-array will compare the calculation results from the 4xG in-memory calculation groups, find the maximum value and generate the index of the corresponding in-memory calculation sub-array position, and output the index to the word line driver.

[0016] In high-precision sparse digital domain computing operations: In the second step of digital domain computing, the sign bit unit, analog-digital hybrid unit, and digital unit in the selected in-memory computing cluster are all enabled. Each word line driver will enable the in-memory computing group with the largest analog computing result among the 4xG in-memory computing groups in each in-memory computing subarray according to the index, and enable each read word line in the in-memory computing group in turn, read the in-memory computing group data to the read bit line and the global read bit line, and complete the 2x(Z+1)-bit multiplication and accumulation operation with the input data vector in the digital multiplication and accumulation module.

[0017] Advantages of the present invention:

[0018] Compared with the traditional digital in-memory computing circuit, the analog-assisted digital in-memory computing circuit of the present invention greatly reduces the number of high-precision digital computing operations required through low-precision analog pre-computation, thereby improving the energy efficiency and area efficiency of digital in-memory computing. In addition, since the digital computing and analog computing and refresh functions are embedded in the same in-memory computing cluster, and the data between analog computing and digital computing can be reused, no additional data transfer is required, so the energy efficiency and area efficiency are further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the digital unit of the present invention.

[0020] Figure 2 It is a schematic diagram of the analog-digital mixing unit of the present invention.

[0021] Figure 3 It is a schematic diagram of the sign bit unit of the present invention.

[0022] Figure 4 The schematic diagram of the computing cluster in the analog-digital hybrid self-refresh memory of the present invention.

[0023] Figure 5 Schematic diagram of two working modes of the computing cluster in the analog-digital hybrid self-refresh memory of the present invention.

[0024] Figure 6 A schematic diagram of the in-memory computing group of the present invention.

[0025] Figure 7 It is a schematic diagram of the in-memory computing subarray of the present invention.

[0026] Figure 8 It is a self-refresh principle diagram and timing diagram of the in-memory computing subarray of the present invention.

[0027] Fig. 9 A schematic diagram of the in-memory computing array of the present invention.

[0028] Fig.10 The figure is a flow chart of analog-assisted digital calculation of the in-memory calculation array of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings.

[0030] The computing cluster in the analog-digital hybrid self-refresh memory of the present invention comprises 1 sign bit unit, Z analog-digital hybrid units and Z+1 digital units. Figure 1 As shown, the digital unit is composed of four transistors. Among the four transistors, transistor 1 and transistor 2 are respectively a P-type transistor and an N-type transistor, their gate terminals are connected together as a storage node, the source terminal of transistor 1 and the drain terminal of transistor 2 are connected together as a storage node, and the drain terminal of transistor 1 and the source terminal of transistor 2 are connected to the power supply and the ground respectively. The other two transistors of the four transistors are a write transistor and a read transistor. Among them, transistor 3 is a write transistor, and its source and drain terminals are respectively connected to the write bit line (write bitline, WBL) and the storage node, and the gate terminal is connected to the write word line. Transistor 4 is a read transistor, and its source and drain terminals are respectively connected to the read bit line and the storage node, and the gate terminal is connected to the read word line.

[0031] like Figure 2 As shown, the analog-to-digital hybrid unit is composed of four transistors and a calculation capacitor. Among the four transistors, transistor 1 and transistor 2 are respectively a P-type transistor and an N-type transistor, their gate terminals are connected together as a storage node, the source terminal of transistor 1 and the drain terminal of transistor 2 are connected together as a storage node, and the drain terminal of transistor 1 and the source terminal of transistor 2 are respectively connected to the power supply and the analog line (analog line, AL). The other two transistors of the four transistors are a write transistor and a read transistor. Among them, transistor 3 is a write transistor, and its source and drain terminals are respectively connected to the write bit line (write bitline, WBL) and the storage node, and the gate terminal is connected to the write word line. Transistor 4 is a read transistor, and its source and drain terminals are respectively connected to the read bit line and the storage node, and the gate terminal is connected to the read word line. One end of the calculation capacitor is connected to the storage node, and the other end is connected to the calculation line.

[0032] like Figure 3 As shown, the sign bit unit is composed of six transistors. Among the six transistors, the connection method of four transistors is the same as that of the digital unit (eDRAM). The two extra transistors, transistor 5 and transistor 6, are both N-type transistors, whose gate terminals are respectively connected to the storage node and the opposite of the storage node, and whose source terminals are respectively connected to the input line and the opposite of the input line, and the drain terminals of the two transistors are connected together as an analog line.

[0033] Figure 4 It is a structural block diagram of an embodiment of the in-memory computing cluster with analog-digital hybrid self-refresh proposed by the present invention.

[0034] like Figure 4 As shown, in this embodiment, Z=3, and the calculation cluster in the analog-digital hybrid self-refresh memory of this embodiment is composed of 1 sign bit unit, 3 analog-digital hybrid units, and 4 digital units (eDRAM units). The capacitance size in the 3 analog-digital hybrid units is binary weighted. All eDRAM units in the calculation cluster in the analog-digital hybrid memory are connected to the read word line RWL through the write word line WWL, and the 3 analog-digital hybrid units are connected to the analog line AL through the calculation line CL, and the analog line AL is connected to the analog line AL of the sign bit unit. The number of write word lines WWL, read word lines RWL, analog lines AL, calculation lines CL, input lines IL, and input line anti-ILB in the calculation cluster in the analog-digital hybrid self-refresh memory is 1, and the number of write bit lines WBL and read bit lines RBL is 8.

[0035] Figure 5 Schematic diagram of two working modes of the computing cluster in the analog-digital hybrid self-refresh memory of the present invention.

[0036] In analog mode, one sign bit unit and three analog-digital hybrid units in the in-memory computing cluster are enabled to perform analog domain calculations, while the digital units are not enabled. In digital mode, one sign bit unit, three analog-digital hybrid units, and four digital units in the in-memory computing cluster are enabled, and the data in the units are read out to complete digital domain calculations.

[0037] Figure 6 It is a structural block diagram of an embodiment of the in-memory computing group proposed by the present invention.

[0038] like Figure 6 As shown, in this embodiment, M=N=1, and the in-memory computing group includes 32x4 digital-analog mixed in-memory computing clusters. There are 4 in-memory computing clusters in the same row of the in-memory computing group connected by write bit line WBL, read bit line RBL, input line IL and input line anti-ILB. There are 32 in-memory computing clusters in the same column of the in-memory computing group connected by write word line WWL and read word line RWL. In addition, all in-memory computing clusters in the in-memory computing group are connected by computing line CL. The number of write bit lines WBL and read bit lines RBL in the in-memory computing group is 32x8, the number of input lines IL and input line anti-ILB is 32, the number of write word lines WWL and read word lines RWL is 4, and the number of computing line CL is 1.

[0039] Figure 7 It is a structural block diagram of an embodiment of the in-memory computing subarray proposed by the present invention.

[0040] like Figure 7As shown, in this embodiment, G=1, the in-memory calculation subarray includes 4 in-memory calculation groups, 256 refresh and global read bit line driver units, a multi-input comparator and a word line driver. The 4 in-memory calculation groups are connected through the write bit line WBL, the read bit line RBL, the input line IL and the input line anti-ILB, and are connected to the 256 refresh and global read bit line driver units through the write bit line WBL and the read bit line RBL. The number of the write bit line WBL and the read bit line RBL in the in-memory calculation subarray is 32x8, the number of the input line IL and the input line anti-ILB is 32, the number of the write word line WWL and the read word line RWL is 4x4, and the number of the calculation lines CL is 4; the 4 in-memory calculation groups are connected to the multi-input comparator through the 4 calculation lines CL, and are connected to the word line driver through the 16 write word lines WWL and the 16 read word lines RWL. The output of the multi-input comparator is connected to the input of the word line driver through the index line.

[0041] like Figure 8 As shown, in this embodiment, in the in-memory computing subarray, the refresh and global read bit line driver unit is connected to the in-memory computing cluster unit in the same row through the read bit line and the write bit line. This unit can be a sign bit unit, a mixed analog-digital unit, or a digital unit. The refresh and global read bit line driver unit consists of two tri-state gates. The input of one of the tri-state gates is connected to the read bit line, the output is connected to the write bit line, and the control signal is connected to the read and write enable. The input of the other tri-state gate is connected to the read bit line, the output is connected to the global read bit line, and the control signal is connected to the read enable. When performing a self-refresh operation: the read word line is first set high, and the value of the storage node in the opened in-memory computing cluster is transferred to the read bit line; then the read and write enable is set high, the value of the read bit line is restored and transferred to the write bit line; finally, the write word line is set high, and the value of the write bit line is transferred to the storage node to complete the refresh.

[0042] Fig. 9 It is a whole structural block diagram of an embodiment of the analog auxiliary digital in-memory computing circuit proposed by the present invention.

[0043] like Fig. 9As shown, in this embodiment, S=16, the in-memory calculation array includes 16 in-memory calculation sub-arrays, 32 input data registers, 32 digital-to-analog converters and 1 digital multiplication and accumulation module. The 16 in-memory calculation sub-arrays are connected through input lines IL, input line anti-ILB, global write bit lines GWBL and global read bit lines GRBL. The number of global write bit lines GWBL and global read bit lines GRBL in the in-memory calculation array is 32x8, and the number of input lines IL and input line anti-ILB is 32. The 32 input data registers are respectively connected to the 32 digital-to-analog converters, and the 32 digital-to-analog converters are connected to the 16 in-memory calculation sub-arrays through 32 input lines IL and input line anti-ILB, and the digital multiplication and accumulation module is connected through 256 global read bit lines GRBL.

[0044] Fig.10 The figure is a flow chart of analog-assisted digital calculation of the in-memory calculation array of the present invention.

[0045] During low-precision analog pre-calculation: During the first step of analog domain calculation, the sign bit unit and analog-to-digital mixing unit in all in-memory computing clusters are enabled. The digital-to-analog converter will convert the input data into voltage changes on the input line and the opposite of the input line according to the different input data values ​​in the input data register. The sign bit unit in the in-memory computing cluster will select the voltage on the input line or the opposite of the input line to transmit to the analog line according to the sign bit data, thereby driving the digital-to-analog mixing unit. According to the different data in the digital-to-analog mixing unit, the analog line will generate different voltage changes on the computing line through the capacitor in the digital-to-analog mixing unit. The voltage change is the product of the input data and the high Z+1 bit data in the in-memory computing cluster. The 32xM in-memory computing clusters connected to the same computing line simultaneously complete the product of the input data and the high Z+1 bit data in the in-memory computing cluster. The total voltage change generated on the computing line is the result of the multiplication and accumulation of the input data vector and the high Z+1 bit data in the 32xM in-memory computing clusters. At the same time, since the 4xN computing lines in the same in-memory computing group are connected together, their voltage changes are averaged. Next, the multi-input comparator in each in-memory calculation subarray compares the calculation results from the 4xG in-memory calculation groups, finds the maximum value and generates an index of the corresponding in-memory calculation subarray position, and outputs the index to the word line driver.

[0046] High-precision sparse digital domain calculation: In the second step of digital domain calculation, the sign bit unit, analog-digital hybrid unit, and digital unit in the selected in-memory calculation cluster are all enabled. Each word line driver will enable the in-memory calculation group with the largest analog calculation result among the 4xG in-memory calculation groups in each in-memory calculation subarray according to the index, and enable each read word line in the in-memory calculation group in turn, read the in-memory calculation group data to the read bit line and the global read bit line, and complete the 2x(Z+1)-bit multiplication and accumulation operation with the input data vector in the digital multiplication and accumulation module.

[0047] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A hybrid analog-digital self-refresh in-memory computing cluster, characterized in that: The invention comprises a sign bit unit, Z analog-digital mixing units and Z+1 digital units, wherein Z is a natural number, and the digital unit is composed of four transistors, including an N-type transistor, a P-type transistor, a write tube and a read tube. The gate ends of the N-type transistor and the P-type transistor are connected together as a storage node, the source end of the P-type transistor and the drain end of the N-type transistor are connected together as a storage node, the drain end of the P-type transistor and the source end of the N-type transistor are connected to a power supply and a ground respectively, the write tube is an N-type transistor, the source end and the drain end of the write tube are connected to a write bit line WBL and a storage node respectively, the gate end of the write tube is connected to a write word line WWL, and the read tube is an N-type transistor. , the source and drain of the readout tube are respectively connected to the read bit line RBL and the storage node, and the gate of the readout tube is connected to the read word line RWL; the analog-digital hybrid unit includes four transistors and a calculation capacitor, wherein the four transistors are respectively an N-type transistor, a P-type transistor, a write tube and a readout tube, wherein the gate of the N-type transistor and the gate of the P-type transistor are connected together as a storage node, the source of the P-type transistor and the drain of the N-type transistor are connected together as a storage node, the drain of the P-type transistor and the source of the N-type transistor are respectively connected to the power supply and the analog line AL, the write tube is an N-type transistor, and the source and drain of the write tube are respectively connected to the write bit line WBL The gate end of the write tube is connected to the write word line WWL, the read tube is an N-type transistor, the source and drain ends of the read tube are respectively connected to the read bit line RBL and the storage node, the gate end of the read tube is connected to the read word line RWL, the calculated capacitance is binary weighted, one end of the calculated capacitance is connected to the storage node, and the other end is connected to the calculation line CL; the sign bit unit is composed of six transistors, four of which are an N-type transistor, a P-type transistor, a write tube and a read tube, the gate ends of the N-type transistor and the P-type transistor are connected together as a storage node, the source end of the P-type transistor and the drain end of the N-type transistor are connected together as a storage node, and the P-type transistor The drain end of the body tube and the source end of the N-type transistor are connected to the power supply and the ground respectively. The write tube is an N-type transistor. The source end and the drain end of the write tube are connected to the write bit line WBL and the storage node respectively. The gate end of the write tube is connected to the write word line WWL. The read tube is an N-type transistor. The source end and the drain end of the read tube are connected to the read bit line RBL and the storage node respectively. The gate end of the read tube is connected to the read word line RWL. In addition to the above four transistors, the other two transistors are N-type transistors. The gate ends of these two transistors are connected to the storage node and the storage node respectively. The source ends are connected to the input line IL and the input line ILB respectively. The drain ends of these two transistors are connected together to form an analog line AL.The in-memory computing cluster stores a 2x(Z+1)-bit "sign-amplitude" encoded data, the sign bit unit stores the sign bit, the analog-digital mixing unit stores the high Z bit in the data amplitude bit, and the digital unit stores the low Z+1 bit in the data amplitude bit. All the above units are connected to the read word line RWL through the write word line WWL, wherein the Z analog-digital mixing units are connected to the analog line AL through the calculation line CL, the number of the write word line WWL, the read word line RWL, the analog line AL, the calculation line CL, the input line IL and the input line anti-ILB are all 1, the number of the write bit line WBL and the read bit line RBL is 2x(Z+1), the analog line AL of the analog-digital mixing unit is connected to the analog line AL of the sign bit unit, and the working modes of the in-memory computing cluster are respectively analog mode and digital mode. In the analog mode, the sign bit unit and the analog-digital mixing unit are enabled to perform analog domain calculation, while the digital unit is not enabled; in the digital mode, all units are enabled, and the data are read out to complete the digital and calculation. ; 2. An analog-assisted digital in-memory computing circuit constructed using the analog-digital hybrid self-refresh in-memory computing cluster of claim 1, characterized in that: First, an in-memory computing group is formed by (32xM)x(4xN) in-memory computing clusters, where M and N are natural numbers. The same row in the in-memory computing group has 4xN in-memory computing clusters connected through a write bit line WBL, a read bit line RBL, an input line IL, and an input line anti-ILB. The same column in the in-memory computing group has 32xM in-memory computing clusters connected through a write word line WWL and a read word line RWL. The computing lines CL of all in-memory computing clusters in the in-memory computing group are connected. Then, an in-memory computing sub-array is formed by 4xG in-memory computing groups, 32xMx2x(Z+1) refresh and global read bit line driver units, a multi-input comparator and a word line driver, G is a natural number, the 4xG in-memory computing groups are connected through write bit lines WBL, read bit lines RBL, input lines IL and input line inversion ILB, the refresh and global read bit line driver units are connected to the sign bit units, analog-digital hybrid units or digital units in the in-memory computing cluster of the same row through read bit lines and write bit lines, the 4xG in-memory computing groups are connected to the multi-input comparator through G computing lines CL, connected to the word line driver through write word lines WWL and read word lines RWL, and the output of the multi-input comparator is connected to the input of the word line driver through index lines; Finally, the analog auxiliary digital in-memory computing circuit includes an in-memory computing array composed of S in-memory computing sub-arrays, an input data register, a digital-to-analog converter and a digital multiplication and accumulation module, S is a natural number, and the S in-memory computing sub-arrays are connected through an input line IL, an input line inverse ILB, a global write bit line GWBL and a global read bit line GRBL.

3. The analog-assisted digital in-memory computing circuit according to claim 2, characterized in that: In the in-memory computing subarray, the refresh and global read bit line driver unit is composed of two tri-state gates, wherein the input of one tri-state gate is connected to the read bit line, the output is connected to the write bit line, and the control signal is connected to the read and write enable; the input of the other tri-state gate is connected to the read bit line, the output is connected to the global read bit line, and the control signal is connected to the read enable; If the read word line is set high, the value of the storage node in the opened in-memory computing cluster is transferred to the read bit line; then the read and write enable is set high, and the value of the read bit line is restored and transferred to the write bit line; Finally, the write word line is set high and the value of the write bit line is transferred to the storage node.

4. An operating method of the analog-assisted digital in-memory computing circuit as claimed in claim 2, characterized in that: The specific steps include: 1) In the first step of analog domain calculation, the sign bit units and analog-to-digital mixed units in all in-memory computing clusters are enabled. The digital-to-analog converter will convert the input data into voltage changes on the input line and the opposite of the input line according to the different input data values ​​in the input data register. The sign bit unit in the in-memory computing cluster will select the voltage on the input line or the opposite of the input line to transmit to the analog line according to the sign bit data, thereby driving the digital-to-analog mixed unit. According to the different data in the digital-to-analog mixed unit, the analog line will generate different voltage changes on the computing line through the capacitor in the digital-to-analog mixed unit. The voltage change is the difference between the input data and the high Z+1 bit in the in-memory computing cluster. The 32xM in-memory computing clusters connected to the same computing line simultaneously complete the product of the input data and the high Z+1 bit data in the in-memory computing cluster, and the total voltage change generated on the computing line is the result of the multiplication and accumulation of the input data vector and the high Z+1 bit data in the 32xM in-memory computing clusters. At the same time, since the 4xN computing lines in the same in-memory computing group are connected together, their voltage changes are averaged; then, the multi-input comparator in each in-memory computing sub-array will compare the calculation results from the 4xG in-memory computing groups, find the maximum value and generate the index of the corresponding in-memory computing sub-array position, and output the index to the word line driver; 2) During the second step of digital domain calculation, the sign bit unit, analog-digital mixed unit, and digital unit in the selected in-memory calculation cluster are all enabled, and each word line driver will enable the in-memory calculation group with the largest analog calculation result among the 4xG in-memory calculation groups in each in-memory calculation subarray according to the index, and enable each read word line in the in-memory calculation group in turn, read the in-memory calculation group data to the read bit line and the global read bit line, and complete the 2x(Z+1)-bit multiplication and accumulation operation with the input data vector in the digital multiplication and accumulation module.

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