LLC resonant converter synchronous rectification control device

Abstract

The present invention provides a synchronous rectification control device for an LLC resonant converter. It is applied to the field of power supply control. The method comprises: a processor, which outputs a secondary synchronous rectification MOS tube control signal SR_PWM and a comparator start signal Dsp_start_pwm according to the output power Pout; a comparison unit, which is used to determine the direction of the output current of the secondary synchronous rectification MOS tube, and outputs a current comparison trigger signal Ien according to the direction of the output current of the secondary synchronous rectification MOS tube under the triggering of the comparator start signal Dsp_start_pwm; an inverter, which is used to perform an inversion operation on the drain-source voltage signal Uds of the secondary synchronous rectification MOS tube and output a signal; a first logic AND unit, which is used to receive the current comparison trigger signal Ien and the signal, perform a signal level state logic AND operation, and output a signal Uen; a second logic AND unit, which is used to receive the signal Uen and the secondary synchronous rectification MOS tube control signal SR_PWM. The present invention realizes precise control of the opening and closing of the synchronous rectification MOS tube, and improves the power conversion efficiency of the LLC resonant converter.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply control, and in particular to a synchronous rectification control device of an LLC resonant converter. Background Art

[0002] With the large-scale construction of 5G, higher requirements are placed on the high efficiency of AC-DC switching power supplies. LLC converters are increasingly used in switching power supplies because they can achieve zero voltage switching (ZVS) or zero current switching (ZCS) and have the characteristics of high efficiency and high power density. Since most of the current base station switching power supplies are 48V, they belong to low-voltage and high-current occasions. The LLC converter uses synchronous rectification technology to greatly reduce the loss of the rectifier tube, so turning on the output synchronous rectification switch is particularly important to improve the efficiency of the LLC converter.

[0003] LLC synchronous rectification drive is much more complicated than other topologies. Its synchronous rectification drive is not only related to the primary side drive, but also to the resonant current. The most important thing about synchronous rectification is its drive timing. Its main idea is to control the synchronous conduction of the switch tube when the body diode is turned on, reduce the on-resistance Rd of the secondary side switch tube, and improve the conversion efficiency. When the LLC resonant converter works in the state of continuous or critically continuous secondary current of the transformer, the primary LLC resonant converter drive signal is synchronized with the secondary current, which meets the requirements of synchronous rectification drive; however, when the LLC resonant converter works in the state of discontinuous secondary current of the transformer, that is, the switching frequency of the converter is less than the resonant frequency, the secondary current drops to zero. Since the primary MOS tube drive signal still exists, the secondary SR is still turned on. Therefore, during the period of discontinuous current, if the drive of the synchronous rectification SR cannot be turned off in time, energy will flow back from the secondary side to the primary side, which will eventually increase the converter loss and reduce the gain.

[0004] At present, some schemes judge the driving signal according to the synchronous rectifier SR drain-source voltage. When the synchronous rectifier drain-source voltage is lower than the conduction threshold, it means that current flows through the body diode at this time, and the detection chip outputs a driving signal to turn it on. When shutting down, the synchronous rectifier is controlled to shut down by judging the size of the drain-source voltage. However, there are parasitic parameters in the circuit, which leads to deviations in the detection of the SR drain-source voltage. Therefore, the SR may be shut down by mistake, affecting the effect of synchronous rectification. Some other schemes adopt current detection control, that is, the synchronous rectifier driving signal is provided by detecting the output load current of the secondary diode, but the signal value of the diode current is small when it is close to zero, which is easy to give the synchronous rectifier MOS tube frequent switching or wrong driving signal. In short, the power conversion efficiency of the LLC resonant converter of the above scheme is low. Summary of the invention

[0005] In view of this, the present invention provides an LLC resonant converter synchronous rectification control device, comprising:

[0006] The processor calculates the output power Pout of the LLC resonant converter according to the output voltage signal Uo and the output current signal Io of the LLC resonant converter, and outputs the secondary side synchronous rectification MOS tube control signal SR_PWM and the comparator start signal Dsp_start_pwm according to the output power Pout;

[0007] A comparison unit, used for judging the direction of the output current of the secondary-side synchronous rectification MOS tube, and outputting a current comparison trigger signal Ien according to the direction of the output current of the secondary-side synchronous rectification MOS tube under the triggering of the comparator start signal Dsp_start_pwm, wherein when the output current of the secondary-side synchronous rectification MOS tube is a forward current, the current comparison trigger signal Ien is in a high level state, and when the output current of the secondary-side synchronous rectification MOS tube is a reverse current, the current comparison trigger signal Ien is in a low level state, the LLC resonant converter includes a primary side and a secondary side synchronous rectification network of the LLC resonant converter, the secondary side synchronous rectification network includes a secondary side synchronous rectification MOS tube, the forward current indicates that the current flows from the primary side of the LLC resonant converter to the secondary side synchronous rectification network, and the reverse current indicates that the current flows from the secondary side synchronous rectification network to the primary side of the LLC resonant converter;

[0008] The inverter is used to invert the drain-source voltage signal Uds of the secondary synchronous rectifier MOS tube and output the signal ;

[0009] The first logic AND unit is used to receive the current comparison trigger signal Ien and the signal , perform signal level state logic AND operation, and output signal Uen, wherein, when the current comparison trigger signal Ien and the signal When both are in high level state, the signal Uen is in high level state. When any one of them is in a low level state, the signal Uen is in a low level state;

[0010] A second logic AND unit is used to receive the signal Uen and the secondary synchronous rectification MOS tube control signal SR_PWM, wherein when the signal Uen is in a high level state, the signal Uen and the secondary synchronous rectification MOS tube control signal SR_PWM are subjected to a signal level state logic AND operation, and a control signal SR_COL_PWM is output to the secondary synchronous rectification MOS tube to drive and turn on the secondary synchronous rectification network; when the signal Uen is in a low level state, the secondary synchronous rectification MOS tube control signal SR_PWM is turned off and no longer outputs the control signal SR_COL_PWM;

[0011] After the second logic AND unit drives and turns on the secondary-side synchronous rectification MOS tube, the comparison unit detects the output current of the secondary-side synchronous rectification MOS tube. When the output current of the secondary-side synchronous rectification MOS tube becomes 0, the output end of the second logic gate circuit unit turns off the control signal SR_COL_PWM to turn off the secondary-side synchronous rectification network.

[0012] Optionally, after the second logic and unit drives and turns on the secondary-side synchronous rectification network, it further includes:

[0013] When the second logic AND unit stops receiving the secondary synchronous rectification MOS tube control signal SR_PWM, the output end of the second logic AND unit stops outputting the control signal SR_COL_PWM to the secondary synchronous rectification MOS tube to shut down the secondary synchronous rectification network.

[0014] Optionally, the processor includes an AD sampling unit for filtering the output voltage signal Uo and the output current signal Io of the LLC resonant converter.

[0015] Optionally, the processor outputs a secondary-side synchronous rectification MOS tube control signal SR_PWM and a comparator start signal Dsp_start_pwm according to the output power Pout, including:

[0016] The processor compares the output power Pout with a maximum power limit value Pup and a minimum power limit value Pdown, wherein Pup>Pdown, and a difference between the maximum power limit value Pup and the minimum power limit value Pdown is greater than a preset difference;

[0017] If Pout<Pdown, the processor turns off the output of the secondary-side synchronous rectification MOS tube control signal SR_PWM;

[0018] If Pout>Pup, the processor determines the magnitude of the switching frequency fs and the resonant frequency fr of the LLC resonant converter;

[0019] If fs≥fr, the processor outputs a signal for lowering the bus voltage of the LLC resonant converter so that fs<fr;

[0020] If fs<fr, the processor slowly outputs the secondary-side synchronous rectification MOS tube control signal SR_PWM from the minimum duty cycle until the maximum duty cycle is reached. Compared with the primary-side MOS tube control signal, the secondary-side synchronous rectification MOS tube control signal SR_PWM has the timing logic characteristics of being turned on at the same time and turned off a period of time earlier than the primary-side MOS tube. The processor outputs the comparator start signal Dsp_start_pwm according to the timing logic of the secondary-side synchronous rectification MOS tube control signal SR_PWM. The effective level of the comparator start signal Dsp_start_pwm is used to turn on the second comparator output and release the threshold voltage generated after the second comparator output is flipped from a high level to a low level.

[0021] Optionally, the comparison unit includes: a second comparator, the second comparator includes a positive input terminal, a negative input terminal, and a second comparator output terminal, the positive input terminal is used to receive the comparator start signal Dsp_start_pwm on the first differential circuit and the current signal GND of the secondary synchronous rectification MOS tube, and after the positive input terminal receives the comparator start signal Dsp_start_pwm, it ensures that the second comparator is turned on at the same time when the primary MOS tube is turned on;

[0022] The negative input terminal is used to receive the current signal GND1 of the secondary synchronous rectification MOS tube on the second differential circuit and the feedback signal output by the second comparator. After the output of the second comparator jumps from a high level to a low level, the feedback signal will generate a threshold voltage for latching the output of the second comparator;

[0023] When triggered by the comparator start signal Dsp_start_pwm, the second comparator cancels the influence of the threshold voltage of the negative input terminal for latching the output of the second comparator, so that the second comparator outputs a current comparison trigger signal Ien at the output terminal of the second comparator according to the current size of the current signal GND input at the positive input terminal and the current signal GND1 input at the negative input terminal.

[0024] Optionally, the first differential circuit includes: a sixth inverter, an eighth resistor, a second diode, and a second resistor. The comparator start signal Dsp_start_pwm passes through the sixth inverter, the eighth resistor, the second diode and merges with the current signal GND passing through the second resistor to be input into the positive input terminal of the second comparator.

[0025] Optionally, the second differential circuit includes: a fourth resistor, a first diode, a seventh resistor, and a seventh inverter. The current signal GND1 passes through the fourth resistor and merges with the low-level current comparison trigger signal Ien passing through the seventh inverter, the seventh resistor, and the first diode to be input into the positive input terminal of the second comparator.

[0026] Optionally, the resistance of the seventh resistor is greater than the resistance of the eighth resistor.

[0027] Optionally, a capacitor is connected between the first differential circuit and the second differential circuit, and the capacitor is used to maintain the voltage difference between the first differential circuit and the second differential circuit to ensure that the control signal SR_COL_PWM of the secondary side synchronous rectification MOS tube is in a valid state within a period of time.

[0028] Optionally, the first differential circuit further includes a first pull-up resistor, and the second differential circuit further includes a fifth pull-up resistor, wherein the first pull-up resistor and the fifth pull-up resistor have the same resistance and are used to balance the voltage of the first differential circuit and the second differential circuit.

[0029] The present invention obtains the output load power Pout of the LLC resonant converter by collecting and calculating, and then determines whether to turn on or off the secondary synchronous rectification MOS tube control signal SR_PWM according to the power Pout. The drain-source voltage signal Uds of the secondary synchronous rectification MOS tube is detected and obtained, and after logical inversion, the comparison unit output current comparison trigger signal Ien for judging the output current direction of the secondary synchronous rectification MOS tube is logically ANDed, and then the comparison unit is logically ANDed with the secondary synchronous rectification MOS tube control signal SR_PWM issued by the DSP processor, and finally an accurate synchronous rectification drive control signal SR_COL_PWM is obtained. The comparison unit has a low-level output latch function, and the DSP processor sends a pulse start (comparator start signal Dsp_start_pwm) at the beginning of each LLC switching cycle, avoiding the problem of repeated flipping of the comparison unit due to a small signal when the secondary output current is close to zero. At the same time, when the secondary current is reversed, the circuit can timely block the synchronous rectification control signal SR_PWM, thereby reducing the LLC resonant converter loss. Through the wave generation logic of the DSP software and the combination with hardware detection, an accurate and reliable synchronous rectification control signal SR_COL_PWM can be generated, which can accurately control the opening and closing of the synchronous rectification MOS tube, thereby improving the power conversion efficiency and system performance of the LLC resonant converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 is a circuit diagram of an LLC resonant converter in an embodiment of the present invention;

[0032] Figure 2 is a circuit diagram of a synchronous rectification control device for an LLC resonant converter in an embodiment of the present invention;

[0033] Figure 3 It is a flow chart of the DSP processor processing data in an embodiment of the present invention;

[0034] Figure 4 A comparison diagram of LLC_PWM waveform and SR_PWM waveform of the primary LLC drive in an embodiment of the present invention;

[0035] Figure 5 It is a schematic diagram of the LLC resonant converter in the embodiment of the present invention working in three regions. DETAILED DESCRIPTION

[0036] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0038] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] Figure 1 The circuit diagram of the LLC resonant converter includes a PFC module 1, an LLC resonant converter primary 2, a resonant network 3, and a secondary synchronous rectification network 4. The PFC module 1 and the LLC resonant converter primary 2 are connected through a bus VBUS. The LLC resonant converter primary 2, the resonant network 3, and the secondary synchronous rectification network 4 are connected to each other in sequence to form a closed-loop circuit. The LLC resonant converter primary 2 includes a bus voltage sampling unit 5, a primary MOS tube Q1, a primary MOS tube Q2, a primary MOS tube Q3, a primary MOS tube Q4, and diodes connected in parallel with the four primary MOS tubes, respectively. The bus voltage sampling unit 5 is used to collect the voltage Ubus; the secondary synchronous rectification network includes a secondary synchronous rectification MOS tube DS1, a secondary synchronous rectification MOS tube DS2, a secondary synchronous rectification MOS tube DS3, a secondary synchronous rectification MOS tube DS4, diodes connected in parallel with the four secondary synchronous rectification MOS tubes, a drain-source voltage sampling unit 6, a voltage sampling unit 7, a current sampling unit 8, and a synchronous rectification current sampling terminal 9. When the secondary-side synchronous rectification MOS tube is turned on, the diode connected in parallel with it is usually not turned on, because the MOS tube provides a lower conduction voltage drop and higher efficiency. Therefore, when the MOS tube of the primary LLC is turned on, the diode is usually in the off state when the MOS tube is working; the drain-source voltage sampling unit 6 is used to collect the drain-source voltage signal Uds of the secondary-side synchronous rectification MOS tube, the voltage sampling unit 7 is used to collect the output voltage signal Uo of the LLC resonant converter; the current sampling unit 8 is used to collect the output current of the LLC resonant converter, and the signal Io is obtained after circuit transformation. The synchronous rectification current sampling terminal 9 is used to transmit the current signal GND and the current signal GND1 of the secondary-side synchronous rectification MOS tube on both sides of the resistor Rs.

[0041] When the LLC resonant converter is working, the current on the primary side flows to the resonant network and is used to achieve energy conversion and transmission through the LLC resonant converter. On the secondary side, the synchronous rectifier controls the current to flow to the output load.

[0042] Aiming at the phenomenon that the detection of drain-source voltage (Uds) and output current (Io) of LLC resonant converter is not accurate in judging the secondary synchronous rectification drive due to parasitic parameters and other reasons, the present invention adopts a combination of DSP processor software wave generation and hardware detection signal to generate accurate control synchronous rectification drive signal. LLC converter and synchronous rectification both adopt full-bridge structure, such as Figure 1 As shown, the primary MOS tubes Q1, Q2, Q3 and Q4 form a full-bridge LLC converter (LLC resonant converter primary side), Lr1, Cr1 and transformer T1 form a resonant network, and the secondary synchronous rectification MOS tubes DS1, DS2, DS3 and DS4 form a full-bridge secondary synchronous rectification network.

[0043] like Figure 2 As shown, an embodiment of the present invention provides an LLC resonant converter synchronous rectification control device, specifically comprising:

[0044] The Dsp processor 10 calculates the output power Pout of the LLC resonant converter according to the output voltage signal Uo and the output current signal Io of the LLC resonant converter, and outputs the secondary synchronous rectification MOS tube control signal SR_PWM and the comparator start signal Dsp_start_pwm according to the output power Pout. The output secondary synchronous rectification MOS tube control signal SR_PWM and the start signal Dsp_start_pwm of the second comparator U2 can be determined according to the calculated output power Pout.

[0045] The comparison unit 11 is used to determine the direction of the output current of the secondary synchronous rectifier MOS tube. When triggered by the comparator start signal Dsp_start_pwm, the current comparison trigger signal Ien is output according to the direction of the output current of the secondary synchronous rectifier MOS tube. When the output current of the secondary synchronous rectifier MOS tube is a forward current, the current comparison trigger signal Ien is in a high level state. When the output current of the secondary synchronous rectifier MOS tube is a reverse current, the current comparison trigger signal Ien is in a low level state. Figure 1 It can be seen that the forward current indicates that the current flows from the primary side of the LLC resonant converter to the secondary side synchronous rectification network, and the reverse current indicates that the current flows from the secondary side synchronous rectification network to the primary side of the LLC resonant converter. The output current direction of the secondary side synchronous rectification MOS tube also indicates the current direction of the diode connected in parallel with it.

[0046] Inverter U1 is used to invert the drain-source voltage signal Uds of the secondary synchronous rectifier MOS tube and output the signal The drain-source voltage signal Uds is a level signal between 0-3.3V. When the diode connected in parallel with the secondary synchronous rectifier MOS tube is not conducting (the secondary synchronous rectifier MOS tube is conducting), the drain-source voltage Uds value is 3.3V, which is a high level. When the diode connected in parallel with the secondary synchronous rectifier MOS tube is conducting (the secondary synchronous rectifier MOS tube is not conducting), the drain-source voltage Uds value is about 0.7V, which is a low level. Inverter U1 will invert the level state of the drain-source voltage signal Uds and obtain the signal .

[0047] The first logic AND unit U3 is used to receive the current comparison trigger signal Ien and the signal , perform signal level state logic AND operation, and output signal Uen, where when the current comparison trigger signal Ien and signal When both are in high level state, signal Uen is in high level state. When any one of them is in low level state, the signal Uen is in low level state.

[0048] The second logic AND unit U4 is used to receive the signal Uen and the secondary-side synchronous rectification MOS tube control signal SR_PWM. When the signal Uen is in a high-level state, the signal Uen and the secondary-side synchronous rectification MOS tube control signal SR_PWM are subjected to a signal level state logic AND operation, and a control signal SR_COL_PWM is output to the secondary-side synchronous rectification MOS tube to drive and turn on the secondary-side synchronous rectification network. When the signal Uen is in a low-level state, the secondary-side synchronous rectification MOS tube control signal SR_PWM is turned off and the control signal SR_COL_PWM is no longer output.

[0049] After the second logic AND unit U4 drives to turn on the secondary synchronous rectification MOS tube, the comparison unit detects the output current of the secondary synchronous rectification MOS tube. When the output current of the secondary synchronous rectification MOS tube becomes 0, the output end of the second logic gate circuit unit U4 turns off the control signal SR_COL_PWM to turn off the secondary synchronous rectification network. When the output current of the secondary synchronous rectification MOS tube becomes 0, the current comparison trigger signal Ien output by the comparison unit will deflect from high to low, and the signal Uen level state will also deflect, and then the output of the first logic AND unit U3 and the second logic AND unit U4 becomes low, blocking the output of the secondary synchronous rectification MOS tube control signal SR_PWM, and then the output end of the second logic gate circuit unit U4 turns off the control signal SR_COL_PWM, so that the secondary synchronous rectification network can be turned off.

[0050] When the secondary-side synchronous rectification network receives the control signal SR_COL_PWM, the four secondary-side synchronous rectification MOS tubes DS1, DS2, DS3 and DS4 are turned off at the same time. At this time, the diode in parallel with the MOS tube will allow current to pass. In particular, when reverse current appears in the secondary-side synchronous rectification network, the diode can prevent the reverse current from damaging the turned-off MOS tube.

[0051] In this embodiment, the output load power Pout of the LLC resonant converter is obtained by acquisition and calculation, and then the control signal SR_PWM of the secondary synchronous rectifier MOS tube is determined according to the power Pout. The drain-source voltage signal Uds of the secondary synchronous rectifier MOS tube is detected and obtained, and after logical inversion, the comparison unit output current comparison trigger signal Ien for judging the output current direction of the secondary synchronous rectifier MOS tube is logically ANDed, and then the comparison unit output current comparison trigger signal Ien is logically ANDed with the secondary synchronous rectifier MOS tube control signal SR_PWM issued by the DSP processor, and finally the precise synchronous rectifier drive control signal SR_COL_PWM is obtained. The comparison unit has a low-level output latch function, and the DSP processor sends a pulse start (comparator start signal Dsp_start_pwm) at the beginning of each LLC switching cycle, which avoids the problem of repeated flipping of the comparison unit due to a small signal when the secondary output current is close to zero. At the same time, when the secondary current is reversed, the circuit can timely block the synchronous rectification control signal SR_PWM, thereby reducing the loss of the LLC resonant converter. Through the wave generation logic of the DSP software and the combination with hardware detection, an accurate and reliable synchronous rectification control signal SR_COL_PWM can be generated, which can accurately control the opening and closing of the synchronous rectification MOS tube, thereby improving the power conversion efficiency and system performance of the LLC resonant converter.

[0052] In one embodiment, after the second logic AND unit U4 drives and turns on the secondary synchronous rectification network, it also includes:

[0053] When the second logic AND unit U4 turns off receiving the secondary synchronous rectification MOS tube control signal SR_PWM, the output end of the second logic AND unit U4 turns off the output control signal SR_COL_PWM to the secondary synchronous rectification MOS tube to turn off the secondary synchronous rectification network. In this LLC switching cycle, after the secondary synchronous rectification MOS tube is turned on, if the second logic AND unit U4 subsequently turns off receiving the secondary synchronous rectification MOS tube control signal SR_PWM, it will no longer output the control signal SR_COL_PWM to the secondary synchronous rectification MOS tube to achieve timely closing of the secondary synchronous rectification MOS tube.

[0054] In one embodiment, the Dsp processor 10 includes an AD sampling unit 12 for filtering the output voltage signal Uo and the output current signal Io of the LLC resonant converter. The AD sampling unit performs filtering processing on the sampled output voltage signal Uo and the output current signal Io to remove possible high-frequency noise or interference and retain valid information in the signal to improve the quality and accuracy of the signal.

[0055] like Figure 3 As shown, the steps of the Dsp processor outputting the secondary synchronous rectification MOS tube control signal SR_PWM and the comparator start signal Dsp_start_pwm according to the output power Pout specifically include:

[0056] S1, compare the output power Pout with the maximum power limit Pup and the minimum power limit Pdown, and determine whether the output power Pout is greater than the maximum power limit Pup, wherein Pup>Pdown, and the difference between the maximum power limit Pup and the minimum power limit Pdown is greater than the preset difference. If Pout<Pdown, execute step S2; if Pdown≤Pout≤Pup, the output load of the LLC resonant converter is normal; if Pout>Pup, execute step S3.

[0057] Among them, the maximum power limit Pup and the minimum power limit Pdown are related to the gain characteristics of the LLC resonant converter and the rated output power Pe. The maximum power limit Pup is generally between 0.05Pe and 0.15Pe, and the minimum power limit Pdown is the maximum power limit Pup minus the preset difference. In order to avoid frequent switching of the synchronous rectification MOS tube, the hysteresis value is not less than 100W.

[0058] S2, the DSP processor turns off the output of the secondary-side synchronous rectification MOS tube control signal SR_PWM, causing the signal SR_PWM to become a low level.

[0059] S3, the Dsp processor determines whether the switching frequency fs of the LLC resonant converter is less than the resonant frequency fr. In this way, it is determined whether the LLC resonant converter is in an under-resonant state. If fs≥fr, it means that the LLC resonant converter is in an over-resonant state or a quasi-resonant state, and then step S4 is executed; if fs<fr, it means that the LLC resonant converter is in an under-resonant state, and then step S5 is executed.

[0060] S4, the DSP processor outputs a signal to lower the bus voltage of the LLC resonant converter so that fs < fr. The DSP processor 10 also communicates with the PFC module 1 of the LLC resonant converter. When it is determined that the LLC resonant converter is in an over-resonant state or a quasi-resonant state, within the adjustable range of the PFC bus voltage Ubus, the DSP processor communicates with the CPU of the preceding PFC module to slowly reduce the output value of the PFC bus voltage, so that the switching frequency fs of the LLC resonant converter is gradually reduced until it is reduced to below the resonant frequency fr, and is in an under-resonant state, and then executes step S5.

[0061] S5, the Dsp processor slowly starts to output the secondary synchronous rectification MOS tube control signal SR_PWM from the minimum duty cycle until the maximum duty cycle is reached. Compared with the primary MOS tube control signal, the secondary synchronous rectification MOS tube control signal SR_PWM has the timing logic characteristics of simultaneous opening and closing a period of time earlier than the primary MOS tube. The Dsp processor outputs the comparator start signal Dsp_start_pwm according to the timing logic of the secondary synchronous rectification MOS tube control signal SR_PWM. The effective level of the comparator start signal Dsp_start_pwm is used to turn on the second comparator output and release the threshold voltage generated after the second comparator U2 output flips from a high level to a low level. The threshold voltage can be set to 0.5V, which can avoid frequent flipping of the output level of the second comparator U2 when the current is small, and ensure the safety and reliability of the secondary MOS tube synchronous rectification signal.

[0062] The DSP processor outputs the comparator start signal Dsp_start_pwm according to the timing logic of the secondary side synchronous rectification MOS tube control signal SR_PWM, that is, when the primary side MOS tube control is turned on, the secondary side synchronous rectification MOS tube control signal SR_PWM is output, and after controlling the primary side MOS tube and the secondary side MOS tube to be turned on, the output secondary side synchronous rectification MOS tube control signal SR_PWM is turned off 150ns in advance.

[0063] In the under-resonance state, the DSP processor will issue a secondary synchronous rectification network driver SR_PWM that switches on and off simultaneously with the LLC resonant converter primary driver LLC_PWM, such as Figure 4 The LLC_PWM waveform and SR_PWM waveform of the primary LLC drive in the figure show that the primary LLC drive SR_PWM is turned on at the same time as LLC_PWM but is turned off in advance. To avoid output oscillation when the secondary synchronous rectification network drive is turned on, the DSP processor sends the control signal SR_PWM in a slow start manner. The DSP processor slowly expands the SR_PWM wave until the maximum duty cycle is reached, and at the same time sends the start signal Dsp_start_pwm of the second comparator U2 that is turned on at the same time as the primary LLC drive LLC_PWM.

[0064] Specifically, the LLC resonant converter has two resonant frequencies. One is determined by the resonant components Lr and Cr, and the other is determined by Lm, Cr, and the load conditions. These two resonant frequencies are respectively:

[0065] ,

[0066] ,

[0067] where fr > fm. The inductive reactance of the inductive load increases with the increase of the switching frequency, and is used to adjust the output voltage. Therefore, the LLC needs to operate in the inductive region. According to the DC gain characteristics of the LLC resonant converter, it can be divided into three working regions. As Figure 5 shown, on the right side of the vertical line of fs / fr = 1, the switching frequency of the LLC resonant converter is greater than the resonant frequency fr. This working region is Region 1, which is a ZVS region and an inductive load region, but at this time the secondary output current is in a continuous state and ZCS cannot be achieved. In Region 3, it is a capacitive working interval and a ZCS region. Region 2 is both a ZVS and a ZCS region. Usually, the LLC resonant converter is designed to operate in Region 1 or Region 2. To improve efficiency, the switching frequency in Region 1 is relatively high and only enters when the load is light or no-load. When loaded, it mostly operates near the resonant frequency fr in Region 2.

[0068] Therefore, in step S3, the Dsp processor judges the magnitudes of the switching frequency fs and the resonant frequency fr of the LLC resonant converter, and can judge whether the LLC resonant converter is in an under-resonant state according to the magnitude relationships of the switching frequency fs, the resonant frequency fr, and fm corresponding to the following three working states:

[0069] When fs > fr, it is in an over-resonant state, and the output current of the secondary synchronous rectification network is continuous, and there is a reverse recovery loss of the diode. At this time, ZCS cannot be achieved;

[0070] When fs = fr, it is in a quasi-resonant state, and the gain is 1 at this time, and the efficiency is the highest. However, in the working process, it is very difficult to fix the switching frequency at this point;

[0071] When fm < fs < fr, it is in an under-resonant state. At this time, the gain is greater than 1, and the output current of the secondary synchronous rectification network is in a discontinuous state, and both ZVS and ZCS can be achieved. However, in the under-resonant state, if the output synchronous rectification drive is later than the turn-off of the primary LLC drive, there will be a phenomenon of energy backflow from the secondary to the primary, resulting in a decrease in efficiency or even a fault of LLC converter damage.

[0072] In this embodiment, the Dsp processor compares the output power Pout with the maximum power limit Pup and the minimum power limit Pdown to ensure that the LLC resonant converter does not exceed its power limit range to avoid overload and damage. If the output power Pout is lower than the minimum power limit Pdown, the processor will turn off the secondary synchronous rectification MOS tube control signal SR_PWM output to avoid unnecessary loss of the secondary synchronous rectification MOS tube in the low power state. If the output power Pout is higher than the maximum power limit Pup, the processor will determine the size of the switching frequency fs and the resonant frequency fr, and output a signal according to the result to adjust the bus voltage, thereby adjusting the switching frequency to ensure that the LLC resonant converter operates in the best working state. In the under-resonant working state, the Dsp processor will output the secondary synchronous rectification MOS tube control signal SR_PWM, and the start signal Dsp_start_pwm of the second comparator U2 to drive the secondary synchronous rectification MOS tube and the primary MOS tube to turn on at the same time and the secondary synchronous rectification MOS tube is turned off earlier than the primary MOS tube, ensuring the working efficiency and stability of the entire LLC resonant converter system.

[0073] like Figure 2 As shown, the comparison unit 11 includes: a second comparator U2, the second comparator U2 includes a positive input terminal, a negative input terminal, and a second comparator U2 output terminal, the positive input terminal is used to receive the comparator start signal Dsp_start_pwm on the first differential circuit and the current signal GND of the secondary synchronous rectification MOS tube, and after the positive input terminal receives the comparator start signal Dsp_start_pwm, it ensures that the second comparator U2 is turned on at the same time when the primary MOS tube is turned on;

[0074] The negative input terminal is used to receive the current signal GND1 of the secondary side synchronous rectification MOS tube on the second differential circuit and the feedback signal output by the second comparator U2. After the output of the second comparator U2 jumps from a high level to a low level, the feedback signal will generate a threshold voltage (0.5V) for latching the output of the second comparator U2. The threshold voltage can ensure that the second comparator U2 is not affected by the interference current, and avoid the second comparator U2 being mistakenly turned on, resulting in the synchronous rectification MOS tube outputting an erroneous signal. The second comparator U2 is triggered by the comparator start signal Dsp_start_pwm. The comparator start signal Dsp_start_pwm is issued by the DSP processor according to the control signal timing logic of the secondary side synchronous rectification MOS tube. When it is issued, it will ensure that the output current of the synchronous rectification MOS tube is a forward current. After the Dsp_start_pwm signal is generated, it can cancel the influence of the threshold voltage of the negative input terminal for latching the output of the second comparator U2, so that the second comparator U2 outputs the current comparison trigger signal Ien at the output terminal of the second comparator according to the current size of the current signal GND input at the positive input terminal and the current signal GND1 input at the negative input terminal.

[0075] Furthermore, the first differential circuit includes: a sixth inverter U6, an eighth resistor R8, a second diode D2, and a second resistor R2. The comparator start signal Dsp_start_pwm passes through the sixth inverter U6, the eighth resistor R8, the second diode D2 and merges with the current signal GND passing through the second resistor R2 to be input into the positive input terminal of the second comparator U2.

[0076] The second differential circuit includes: a fourth resistor R4, a first diode D1, a seventh resistor R7, and a seventh inverter U7. The current signal GND1 passes through the fourth resistor R4 and merges with the low-level current comparison trigger signal Ien passing through the seventh inverter U7, the seventh resistor R7, and the first diode D1 to be input into the positive input terminal of the second comparator U2.

[0077] Specifically, the second comparator U2 is used to determine the direction of the output current of the secondary synchronous rectification MOS tube and the parallel diode, and then output the current comparison trigger signal Ien. The current signal GND and the current signal GND1 are respectively sent to the positive input and negative input of the second comparator U2 from the two differential circuits drawn from the two sides of the secondary synchronous rectification current sampling resistor Rs. The value of the first resistor R2 of the first differential circuit is equal to the value of the fourth resistor R4 of the second differential circuit. The output signal Ien of the second comparator U2 is sent to the negative input of the second comparator U2 after passing through the seventh inverter U7, the seventh resistor R7 and the diode D1. The comparator start signal Dsp_start_pwm sent by the DSP processor is sent to the positive input of the second comparator U2 after passing through the sixth inverter U6, the eighth resistor R8 and the second diode D2. The diodes D1 and D2 are of the same model, and the value of R7 is much larger than R8.

[0078] At the beginning of each LLC switching cycle, the DSP processor sends a small low-level pulse (comparator start signal Dsp_start_pwm). When the signal Dsp_start_pwm is low, the second inverter U2 outputs a high level. After passing through the eighth resistor R8 and the second diode D2, the positive input of the second comparator U2 will be raised by one level. Since the value of the eighth resistor R8 is much smaller than the seventh resistor R7, the voltage raised at the positive electrode is greater than Vth, and the comparator start signal Dsp_start_pwm input at the positive electrode will open the latched second comparator U2. Then the second comparator U2 will perform voltage comparison based on the input current signal GND and the current signal GND1. If the voltage of the signal GND is less than the voltage of the signal GND1, it means that the secondary synchronous rectification MOS tube is a forward current, and the second comparator U2 outputs a current comparison trigger signal Ien of a high level; if the voltage of the signal GND is greater than the voltage of the signal GND1, it means that the secondary synchronous rectification MOS tube is a reverse current, and the second comparator U2 outputs a current comparison trigger signal Ien of a low level.

[0079] When the second comparator U2 outputs the current comparison trigger signal Ien at a low level, the second comparator U2 outputs the current comparison trigger signal Ien and generates a voltage drop voltage as a threshold voltage (0.5V) for latching the second comparator U2 through the seventh inverter U7, and then sends the voltage to the negative input of the second comparator U2 after passing through the seventh resistor R7 and the diode D1, which can ensure that the current comparison trigger signal Ien turns off the receiving secondary-side synchronous rectification MOS tube control signal SR_PWM when performing a logic AND operation, and turns off the output control signal SR_COL_PWM to the secondary-side synchronous rectification MOS tube, thereby achieving precise control to turn off the secondary-side synchronous rectification network and prevent the secondary-side current from backflowing.

[0080] Furthermore, a capacitor is connected between the first differential circuit and the second differential circuit, and the capacitor c2 is used to maintain the voltage difference between the first differential circuit and the second differential circuit, so as to ensure that the effective pulse of the comparator start signal Dsp_start_pwm issued by the DSP processor is maintained for a period of time, and ensure that the output of the second comparator U2 is maintained at a high level for a period of time, that is, to ensure that the control signal SR_COL_PWM of the secondary synchronous rectification MOS tube is in a valid state within a period of time.

[0081] Specifically, the DSP processor sends a small low-level pulse (comparator start signal Dsp_start_pwm), and its low level only takes a short time. Since there is a capacitor C2 between the positive and negative electrodes of the second comparator U2, the positive electrode can be maintained higher than the negative electrode for a period of time, ensuring that the second comparator U2 is turned on when the primary MOS tube of the LLC resonant converter is turned on, ensuring that the control signal SR_COL_PWM of the secondary synchronous rectification MOS tube is in a valid state within a period of time.

[0082] In one embodiment, the first differential circuit further includes a first pull-up resistor R1, and the second differential circuit further includes a fifth pull-up resistor R5, wherein the first pull-up resistor R1 and the pull-up resistor R5 have the same resistance, and are used to balance the voltage of the first differential circuit and the second differential circuit. Inputting the first pull-up resistor R1 and the fifth pull-up resistor R5 can ensure that the positive and negative inputs of the second comparator U2 remain in a stable level state when there is no input signal. This can prevent drift caused by the input signal not being connected, and ensure the accuracy of the comparison.

[0083] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0084] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0085] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0087] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A synchronous rectification control device for an LLC resonant converter, characterized in that: include: The processor calculates the output power Pout of the LLC resonant converter according to the output voltage signal Uo and the output current signal Io of the LLC resonant converter, and outputs the secondary side synchronous rectification MOS tube control signal SR_PWM and the comparator start signal Dsp_start_pwm according to the output power Pout; A comparison unit, used for judging the direction of the output current of the secondary-side synchronous rectification MOS tube, and outputting a current comparison trigger signal Ien according to the direction of the output current of the secondary-side synchronous rectification MOS tube under the triggering of the comparator start signal Dsp_start_pwm, wherein when the output current of the secondary-side synchronous rectification MOS tube is a forward current, the current comparison trigger signal Ien is in a high level state, and when the output current of the secondary-side synchronous rectification MOS tube is a reverse current, the current comparison trigger signal Ien is in a low level state, the LLC resonant converter includes a primary side and a secondary side synchronous rectification network of the LLC resonant converter, the secondary side synchronous rectification network includes a secondary side synchronous rectification MOS tube, the forward current indicates that the current flows from the primary side of the LLC resonant converter to the secondary side synchronous rectification network, and the reverse current indicates that the current flows from the secondary side synchronous rectification network to the primary side of the LLC resonant converter; The inverter is used to invert the drain-source voltage signal Uds of the secondary synchronous rectifier MOS tube and output the signal ; The first logic AND unit is used to receive the current comparison trigger signal Ien and the signal , perform signal level state logic AND operation, and output signal Uen, wherein, when the current comparison trigger signal Ien and the signal When both are in high level state, the signal Uen is in high level state. When any one of them is in a low level state, the signal Uen is in a low level state; A second logic AND unit is used to receive the signal Uen and the secondary synchronous rectification MOS tube control signal SR_PWM, wherein when the signal Uen is in a high level state, the signal Uen and the secondary synchronous rectification MOS tube control signal SR_PWM are subjected to a signal level state logic AND operation, and a control signal SR_COL_PWM is output to the secondary synchronous rectification MOS tube to drive and turn on the secondary synchronous rectification network; when the signal Uen is in a low level state, the secondary synchronous rectification MOS tube control signal SR_PWM is turned off and no longer outputs the control signal SR_COL_PWM; After the second logic AND unit drives and turns on the secondary-side synchronous rectification MOS tube, the comparison unit detects the output current of the secondary-side synchronous rectification MOS tube. When the output current of the secondary-side synchronous rectification MOS tube becomes 0, the output end of the second logic gate circuit unit turns off the control signal SR_COL_PWM to turn off the secondary-side synchronous rectification network.

2. The control device according to claim 1, characterized in that: After the second logic and unit drives and turns on the secondary synchronous rectification network, it also includes: When the second logic AND unit stops receiving the secondary synchronous rectification MOS tube control signal SR_PWM, the output end of the second logic AND unit stops outputting the control signal SR_COL_PWM to the secondary synchronous rectification MOS tube to shut down the secondary synchronous rectification network.

3. The control device according to claim 1, characterized in that: The processor includes an AD sampling unit for filtering the output voltage signal Uo and the output current signal Io of the LLC resonant converter.

4. The control device according to claim 1, characterized in that: The processor outputs a secondary-side synchronous rectification MOS tube control signal SR_PWM and a comparator start signal Dsp_start_pwm according to the output power Pout, including: The processor compares the output power Pout with a maximum power limit value Pup and a minimum power limit value Pdown, wherein Pup>Pdown, and a difference between the maximum power limit value Pup and the minimum power limit value Pdown is greater than a preset difference; If Pout<Pdown, the processor turns off the output of the secondary-side synchronous rectification MOS tube control signal SR_PWM; If Pout>Pup, the processor determines the magnitude of the switching frequency fs and the resonant frequency fr of the LLC resonant converter; If fs≥fr, the processor outputs a signal for lowering the bus voltage of the LLC resonant converter so that fs<fr; If fs<fr, the processor slowly outputs the secondary-side synchronous rectification MOS tube control signal SR_PWM from the minimum duty cycle until the maximum duty cycle is reached. Compared with the primary-side MOS tube control signal, the secondary-side synchronous rectification MOS tube control signal SR_PWM has the timing logic characteristics of being turned on at the same time and turned off a period of time earlier than the primary-side MOS tube. The processor outputs the comparator start signal Dsp_start_pwm according to the timing logic of the secondary-side synchronous rectification MOS tube control signal SR_PWM. The effective level of the comparator start signal Dsp_start_pwm is used to turn on the second comparator output and release the threshold voltage generated after the second comparator output is flipped from a high level to a low level.

5. The control device according to claim 1, characterized in that: The comparison unit includes: a second comparator, the second comparator includes a positive input terminal, a negative input terminal, and a second comparator output terminal, the positive input terminal is used to receive the comparator start signal Dsp_start_pwm on the first differential circuit and the current signal GND of the secondary synchronous rectification MOS tube, and after the positive input terminal receives the comparator start signal Dsp_start_pwm, it ensures that the second comparator is turned on at the same time when the primary MOS tube is turned on; The negative input terminal is used to receive the current signal GND1 of the secondary synchronous rectification MOS tube on the second differential circuit and the feedback signal output by the second comparator. After the output of the second comparator jumps from a high level to a low level, the feedback signal will generate a threshold voltage for latching the output of the second comparator; When triggered by the comparator start signal Dsp_start_pwm, the second comparator cancels the influence of the threshold voltage of the negative input terminal for latching the output of the second comparator, so that the second comparator outputs a current comparison trigger signal Ien at the output terminal of the second comparator according to the current size of the current signal GND input at the positive input terminal and the current signal GND1 input at the negative input terminal.

6. The control device according to claim 5, characterized in that: The first differential circuit includes: a sixth inverter, an eighth resistor, a second diode, and a second resistor. The comparator start signal Dsp_start_pwm passes through the sixth inverter, the eighth resistor, the second diode and merges with the current signal GND passing through the second resistor to be input into the positive input terminal of the second comparator.

7. The control device according to claim 6, characterized in that: The second differential circuit includes: a fourth resistor, a first diode, a seventh resistor, and a seventh inverter. The current signal GND1 passes through the fourth resistor and merges with the low-level current comparison trigger signal Ien passing through the seventh inverter, the seventh resistor, and the first diode to be input into the positive input terminal of the second comparator.

8. The control device according to claim 7, characterized in that: The resistance value of the seventh resistor is greater than the resistance value of the eighth resistor.

9. The control device according to claim 5, characterized in that: A capacitor is connected between the first differential circuit and the second differential circuit, and the capacitor is used to maintain the voltage difference between the first differential circuit and the second differential circuit to ensure that the control signal SR_COL_PWM of the secondary synchronous rectification MOS tube is in a valid state within a period of time.

10. The control device according to claim 7, characterized in that: The first differential circuit further includes a first pull-up resistor, and the second differential circuit further includes a fifth pull-up resistor, wherein the first pull-up resistor and the fifth pull-up resistor have the same resistance value and are used to balance the voltage of the first differential circuit and the second differential circuit.

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